CN103368574A

CN103368574A - Digital-to-analog convertor

Info

Publication number: CN103368574A
Application number: CN201310201181XA
Authority: CN
Inventors: 李�真
Original assignee: Suzhou Baker Microelectronics Co Ltd
Current assignee: Suzhou Baker Microelectronics Co Ltd
Priority date: 2013-05-27
Filing date: 2013-05-27
Publication date: 2013-10-23

Abstract

The invention discloses a digital-to-analog convertor (DAC) which is characterized in that the output end of a sub-word pair in a DAC circuit is obtained through modulating the bias voltage of a differential buffer amplifier and calculating the sum. The invention also provides embodiments of different alternative DACs, wherein the input stage of one operational amplifier responds to the modulation of the offset voltage of one digital signal differential buffer amplifier, and linear and monotonicity errors caused by inaccurate components are eliminated by using an interpolation technology.

Description

Digital analog converter

Technical field

The present invention relates to digital analog converter.More particularly, on the one hand, it has the architecture of the segmentation digital analog converter of improvement, on the other hand, provides the conversion of digital to analogy, and one of them analog output voltage is relevant with a digital input word of certain monotonic function.

Background technology

A kind of digital analog converter (DAC) has segmental structure, and its typical case's running is the DAC circuit of controlling by the sub-word that a digital input word is divided into different piece.For example, a digital input word can be divided into the sub-word of more important (being MS) and the sub-word of not too important (being LS), then the sub-word of MS is used to produce first intermediate current or voltage signal, the LS word of the voltage signal response that produces with the second intermediate current or addition.The structure of this segmentation can reduce especially effectively provides the have high-resolution number of resistive element of DAC of (for example 12).Yet, in the situation of the not output of the signal generating circuit of buffering, may make the signal generating circuit of M signal summation, under excessive loading condition, export.On the other hand, the output of sort buffer being added to each signal generating circuit usually can be introduced noise and increase cost and the complexity of DAC.

Provide a buffer to increase the weight of another potential problem by the output at each signal generating circuit, the transmission characteristic among the DAC does not just have monotonicity.In a desirable digital-to-analog converter (DAC), the corresponding numeral input of analog output voltage is a monotonic function, that is to say, the increase of numeral input should cause the increase of analog output voltage, and has reduced the decline that the digital quantity input causes analog output voltage.In many application, the non-dull DAC as in control system can cause serious problem, so monotonicity is vital.Yet in many actual conditions, because assembly produces error inevitably among the DAC, monotonicity always can not realize.

For example, typical 4 bit DAC, it uses simple binary weighting to generate analog output voltage addition binary zero .5,0.25,0.125 and 0.0625 times of volt.As everyone knows, the weight of this selection is so that the increase of numeral input always causes simulating the increase of output.

For example, in such DAC, the character string 0111 of numeral input is 0 (0.5) 1 (0.25) 1 (0.125) 1 (0.0625)=0.4375 volt with the analog output voltage that generates.If the numeral input is incremented to 1000, analog output voltage is elevated to 1 (0.5) 0 (0.25) 0 (0.125) 0 (0.0625)=0.5 volt.Therefore, just as expected, the increment of numeral input causes simulation output to increase.

Yet if the binary system weights are inaccurate, for example, because the resistive element error, the relation between the input and output of this dullness may be lost.Suppose that weight is actually 0.47,0.27,0.14, and 0.07 volt, rather than the ideal value that provides above.In this case, the analog output voltage of a corresponding digital input end 0111 is 0 (0.47) 1 (0.27) 1 (0.14) 1 (0.07)=0.48 volt.When numeral input is incremented to 1000, actual analog output voltage is reduced to 1 (0.47) 0 (0.27) 0 (0.14) 0 (0.07)=0.47 volt.Therefore, in this case analog output voltage is not the monotonic function of digital input port.

It is not dullness that mistake mentioned above causes DAC I/O relation, and these add up to many binary weighting voltages, has that many position DAC's is particularly general that is:.Yet these equipment exactly need to provide accurately, the conversion of dull digital to analogy.

In view of the foregoing, provide a kind of DAC of segmentation to implement very simple, it provides exempts the loading problem relevant with the simulation addition of the M signal that does not cushion.

It can further provide a kind of DAC of segmentation, and it does not need an independent buffer circuit to be present between the output and DAC summing circuit of each signal generating circuit.

This also is desirable, and a kind of circuit is provided, and is used for converting a digital input word to an analog output voltage, produces the monotonic function of digital input word by above-mentioned analog output voltage.

Summary of the invention

An object of the present invention is to provide a kind of have the segmentation DAC of a simple architecture and the summation technology that a kind of Novel free removes the loading problem.

Another object of the present invention provides a kind of DAC, wherein, is avoided in the problem of keeping the monotonicity that produces from the assembly inexactness.

Technical solution of the present invention

According to foregoing of the present invention and other purpose, the DAC of a segmentation, described the offset voltage of the differential amplifier that one of them sub-word modulates the output of DAC circuit, this may be a unit gain buffer amplifier or a different gains amplifier.Also described the alternate example of various DAC and the input stage of an operational amplifier, wherein the modulation in response to the offset voltage of the differential amplifier of a digital signal is the interpositioning that is used for eliminating from the error of the inaccurate linearity that causes of assembly and monotonicity by using.

Description of drawings

In conjunction with following detailed description and accompanying drawing, similar reference symbol represents identical parts in the accompanying drawing, and wherein, foregoing of the present invention and other purpose are apparent:

Fig. 1 is the block diagram of the dull DAC of a routine;

Fig. 2 is the block diagram of existing segmentation DAC;

Fig. 3 is the segmentation DAC of an embodiment, the block diagram of the M signal that obtains according to the bias voltage addition of passing a differential amplifier that is modulated in principle of the present invention;

Fig. 4 is another example of the present invention, is the block diagram of a segmentation, interpolation DAC;

Fig. 5 is a preferred embodiment of the present invention, is the frame principle figure of a segmentation, interpolation DAC;

Fig. 6 is that the input phase according to the differential amplifier of the interpolation of principle of the present invention is realized schematic diagram in the example.

Embodiment

The exemplary that conventional N position DAC provides a bonding tonality conversion is illustrated in Fig. 1 with the form of rough schematic view.DAC100 comprises one group 2 ^NThe resistive element 101 that individual node links to each other and one group 2 ^N Individual switching device 102 couplings, it is connected to unity gain buffer 109 inputs, is directly connected to element 103 and passes through original paper 108.Although understand a specific example of buffer 109, but can use the buffering area of any routine.Current source 107 has promoted the source electrode of

PMOS transistor

103 and 104 in the buffer 109.

Transistor

103 and 104 drain electrode are coupled to the drain electrode of nmos pass transistor 105 and 106.

Transistor

105 and 106 forms current mirror.The signal inversion amplifier 108 of high-gain provides negative feedback by the drain electrode of transistor 103 and the grid of transistor 104.This feedback guarantees that the drain current of

transistor

105 and 106 equates basically.Conversely, this point guarantees that the grid voltage of

transistor

103 and 104 equates basically.Therefore, output voltage VO UT is substantially equal to V ₁The time, be output as group of switching elements 102.

Group of switching elements 102 and resistive element group 101 are used to provide an analog output voltage, and this is to be determined by a digital input word.In Fig. 1, group 101 and group 102 are expressed as conventional resistive element and switching device.But they can be realized with any easily mode.For example, the resistive element group can realize by the resistance material in an integrated circuit with various, and switching device can be MOS switch or transmission gate.Only have at any one time a switching device to be closed in group 102, determine that by the numeral input specific switching device is closed.Particularly, the input of buffer amplifier is connected to the equivalence numeral input that number between ground nodes and the resistive element node equals decimal number k.For example, during N=4, a digital input end is 0000 (during k=0), and switching device group is the most closely sealed; And numeral input 0001 (during k=1), next switching device group sealing; The rest may be inferred, until when an input is 1111 (K=15), is closed at the switching device of the top of group.Determine the decoding of the digital input word that the mobile device of pent switching needs, can finish in the mode of any routine.The accurate mode that group 101, group 102 and necessary decoding are carried out does not consist of a part of the present invention.

The monotonic function that any two voltages at intersection are the resistive element numbers between this specific node and the ground nodes in the resistive element group 101, the resistive element of this number equal the decimal equivalent k of numeral input.Therefore, the input of the numeral of the aanalogvoltage on the input of buffer amplifier is a monotonic function.This monotonicity is guaranteed with the actual value of each resistive element irrelevant.Yet if all resistive elements have equal value, then this analog output voltage will provide linear function a: V of numeral input _OUT=k VEF _RE/ 2 ^N

Although monotonicity guarantees to some extent, when bit number N uprised, DAC Fig. 1 was not in the preferred example, because in this example, DAC needs too many switch element and resistive element.Carried out some trials and overcome the so many switch elements of use and the shortcoming of resistive element, but these trials all cause monotonicity to guarantee, or so that DAC becomes loaded down with trivial details and expensive.

Fig. 2 shows and use a typical segmentation in the skeleton diagram of the custom circuit of a DAC, to reduce the number of switch element and resistive element.In this circuit, the digital input word of N position is divided into two sub-words.A sub-word (MS) is most important sub-word, corresponding to the most important position of M, and other sub-word, i.e. and the sub-word of unessential (LS), the most unessential position of corresponding L, wherein, M+L=N.k _LAnd k _MRepresent respectively the decimal system equivalence of LS and MS word, and with digital input word decimal number equivalent relation be: k=2 ^Lk _M+ k _L(1)

The sub-word of MS is coupled to most important DAC (MSDAC) 201.MSDAC201 is by reference voltage V _REFProvide, and its output is provided by following formula: V _M=k _MV _REF/ 2 ^MLS word is coupled to the most unessential DAC (LSDAC) 202.LSDAC202 is by reference voltage V _REF/ 2 ^MProvide.This reference voltage is so that when the input of MSDAC201 increased progressively a bit, the Full-span output of LSDAC202 equaled V _MIn variable quantity.Therefore the output of LSDAC202 is satisfied: V _L=k _LV _REF/ (2 ^M2 ^L)=k _LV _REF/ 2 ^N, k wherein _LIt is the decimal equivalent of LS word.

The output of MSDAC201 and LSDAC202 is added together by analog adder 207, to produce output voltage V _OUTAnalog adder 207 comprises resistive element 203,204,205 and 208, and amplifier 206.If resistive element 203,204,205 and 208 equates basically, so, analog adder 207 has unified gain.Has unit gain, V _OUTProvided by following formula:

V _OUT＝k _MV _REF/2 ^M+k _LV _REF/2 ^N

＝(2 ^L?k _M+k _L)V _REF/2 ^N

＝kV _REF/2 ^N

Therefore, output voltage is by digital input word K control, and can be from zero to V _REFGamut in change.

Reduce the quantity of resistive element and required switching device than the segmentation DAC of DAC Fig. 2 of Fig. 1 bonding tonality.Suppose that MSDAC201 and LSDAC202 have the structure of DAC shown in Figure 1 separately, then the total quantity of required resistive element is 2 ^M+ 2 ^L, it can less than DAC among Fig. 1 required 2 ^NIndividual resistive element.The quantity of required switching device also reduces identical amount.

Yet the DAC of segmentation has shortcoming among Fig. 2.For example, if resistor 203 and 204 is directly connected to corresponding switches set, they can load related resistive element group and disturb the linearity of DAC.This requires a buffering area, and as shown in Figure 1, buffer 109 is included in MSDAC201 and the LSDAC202 of each.Such buffering is introduced noise, has oneself variation and drift, must be compensated, and increases simultaneously the complexity of DAC.

In addition, although segmentation allows the number of resistive element and switching device significantly to be reduced,, it can not the bonding tonality.As the DAC of previously described binary weighting, the analog output voltage of the DAC of a segmentation is to obtain in the following manner a plurality of aanalogvoltage additions.The Full-span output of LSDAC202 must equal each variable quantity of the generation along with the increase of MS word in the MSDAC output.If do not reach this equality, if particularly the Full-span output of LSDAC202 is greater than the increment of at least one MSDAC201, so nonmonotonic behavior meeting occurs.

The present invention shows a new method, the conversion of digital to analogy, thus reduce the number of switch element and resistive element, and the Organization Chart 2 of the DAC that has simplified.Further bonding tonality in the embodiment.Be shown in Fig. 5 and discussed below in the preferred embodiments of the present invention, interpolation is for the number that provides a DAC to use simultaneously a little resistive element and switching device, and assurance is dull simultaneously.

Fig. 3 is the DAC300 of segmentation, and the architecture of simplifying DAC200 by the present invention illustrates.Segmentation DAC200 and DAC300 use two sub-words.Yet, only have a resistive element connected in series to be used, and the total quantity of required resistive element is 2 ^P, wherein, P is larger among L and the M, for the purpose of this description, P will be assumed that and equal M, but this hypothesis is dispensable.

DAC300 obtains from DAC100, and the length of the group 101 by making resistive element is from 2 ^NReduce to 2 ^M, and insertion switch device group 301, transistor 302,303 and current source 304.MS word control switch element group 102, and LS word control switch device group 301.

The output of LS switching device group 301 is coupled to the most unessential differential transconductance level (LSDTS) 305, and it comprises current source 304 and transistor 302 and 303.The second input of differential transconductance level 305 is grounded.

The output of MS switching device group 102 is coupled to the input of most important differential transconductance level (MSDTS) 306, and it comprises current source 107 and transistor 103 and 104.

Transistor

103 and 104 drain electrode are respectively the output of the transconductance stage 306 of the first and second differential currents.Flow through the difference between the electric current of drain electrode of

transistor

103 and 104, comprise the differential current that transconductance stage 306 produces.The second input of differential transconductance level 306 is coupled to output V _OUTThis negative feedback paths guarantees that the electric current of the drain electrode of

inflow transistor

105 and 106 equates basically.

In order to understand the operation of this circuit, at first consider it and switching device group 301, transistor 302,303 relation, and current source 304 has been removed.Therefore, this exports the only MS word k of suspension control switch device group 102 _MImpact.In this case, DAC100 and DAC300 have identical form.Therefore, the MS of DAC partly is dull, and its output voltage is by following formula: V _OUT=k _MV _REF/ 2 ^M(2)

Again introduce now the switching device group 301 switched, transistor 302,303 and current source 304.Equate that (

transistor

302 and 303 drain electrode generate respectively the output of the transconductance stage 305 of the first and second differential currents if flow out the electric current of the drain electrode of

transistor

302 and 303, and the differences between the electric current that flows together from these drain electrodes comprise the differential current that a differential transconductance stage 305 produces), so, because

transistor

105 and 106 forms current mirror, output V _OUTNot being subjected to is affected by the existence of assembly 301 to 304.When the grid voltage of

transistor

302 and 303 equated, equal electric current will flow through.Because the grounded-grid of transistor 303, k will occur in this _L=0, Simultaneous Switching device group 301a closes.

If k _LBe not 0, the voltage of supplying with to the grid of transistor 302 by switching device group 301 is V _L=k _LV _REF/ 2 ^M

This will cause a differential current dI=k from LSDTS305 _LV _REFg _ML/ 2 ^M(3)

G wherein _MLIt is the mutual conductance of LSDTS305.

Recall, the variation of the output voltage that negative feedback causes, two mobile electric currents equate basically in the current mirror to force.Therefore, output voltage must change by variable dV, is the equal but opposite differential current from MSDTS306 thereby produce one with the differential current of LSDTS305.Therefore, the differential current dI=g of MSDTS306 _MMDV (4)

G wherein _MMIt is the mutual conductance of MSDTS306.The offset voltage V that the variation of dV can be interpreted as demarcating _OS, it produces in buffer 109, and by adding a differential current from LSDTS305, this differential current is determined by LS word.

With formula (3) substitution equation (4) with find the solution variation at output voltage, provide formula:

dV＝(g _mL/g _mM)k _L?V _REF/2 ^M。

This variation is added in the output voltage that has existed, and this output voltage is determined by MS word given in the equation (2).The output voltage V that produces _OUT=k _MV _REF/ 2 ^M+ (g _ML/ g _MM) k _LV _REF/ 2 ^M..(5)

Transconductance ratio g in the superincumbent equation _ML/ g _MMBe a parameter, by transistor 103,104,302 and 303 geometry are controlled by current source 107 and 304.A kind of easily when transconductance ratio obtains, it is 2 that

transistor

103 and 104 has width ^LDoubly greater than to

transistor

302 and 303, and current source 107 generation current sources 304 2 ^LDoubly.In this case,

transistor

103 and 104 mutual conductance are 2 of

transistor

302 and 303 ^LTimes, or g _ML/ g _MM=2 ^-L

Output voltage is provided by following formula:

V _OUT＝(k _M+2 ^-Lk _L)V _REF/2 ^N

＝(2 ^L?k _M+k _L)V _REF/2 ^M+L

＝kV _REF/2 ^N

Therefore, by selecting suitable mutual conductance ratio, the equivalent decimal system of the output voltage of DAC300 and digital input word k is proportional.The sub-word control voltage of LS adds in the output voltage of being determined by MS word.If select suitable mutual conductance than the resistive element exact matching in group 307, the output voltage that LS word is revised provides auxiliary voltage, and it is between k _MV _REF/ 2 ^M(k _M+ 1) V _REF/ 2 ^MBetween.

DAC300 only needs resistive element and the switching device of peanut.But it still has certain limitation.Specifically, two adjacent intersections (or tap) in the inreal insertion resistive element of the DAC300 group 307, the scope of namely LSDTS305 definition is not definitely to be two adjacent taps in the group 307, but the group 307 between the tap of bottom.In addition, the scope of 305LSDTS is subjected to ratio g _ML/ g _MMImpact.Therefore, the monotonicity of DAC300 depends on the accurate control from the resistive element voltage increment of junction resistance element group 307, depends on the accurate control of transistor 103,104,302 and 303 mutual conductances.

More specifically, if all resistive elements of organizing in 307 are basically unequal, not uniform (being that so-called terraced tap makes a mistake) from the voltage increment between the resistive element knot.If under normal conditions, M is greater than L, LSDTS305 all the time from organize 307 2 ^LNearest first obtains its input in the individual resistive element, and MSDTS306 obtains its input from organizing in 307 gamuts.This is a shortcoming, because for monotonicity, DAC300 depends on a fact, namely these 2 ^LIndividual near the voltage at earth resistance element two ends be equal to organize any single resistive element two ends in 307 voltage 2 ^LDoubly.This is similar to the requirement of DAC200, and namely the Full-span output of LSDAC should equal the output increment of MSDAC.If voltage increment disunity between tap, the voltage increment that flows out from tap excavates, and DAC300 can not meet this requirement, and the behavior of nonmonotonicity may occur.

The operation of DAC300 dullness also requires transconductance ratio g _ML/ g _MMKept exactly 2 ^LYet, the impact of the common-mode voltage when mutual conductance is subject to LSDTS305 and MSDTS306 work.Because LSDTS305 is always from organizing 2 of 307 ground connection ^LIndividual resistive element obtains its input, and MSDTS306 obtains its input from organizing 307 gamut, and these common-mode voltages are always not equate, and are even not similar.Therefore, the mutual conductance ratio may change, and nonmonotonic behavior may occur.

Fig. 4 has illustrated a new digital analog converter 400, it uses the principle of DAC300 and has solved the problem of the sensitivity of tap error, i.e. interpolation voltage between the tap in the resistive element group, namely the LSDTS scope is that the virtual voltage of the tap of being crossed over by LSDTS determines.Particular case when Fig. 4 illustrates L=2, but any value of L and M all DAC400 be achieved.

DAC400 is not input to its two differential transconductance levels from the different piece derivation of two resistive element groups, and does not require that the both end voltage of resistive element is uniformly in group, to guarantee monotonicity.In addition, at DAC400,

transistor

302 and 303 is divided into Darlington 409 and 410 (be coupled to current source 411 and consist of LSDTS408), and every contains 2 ^LIndividual sub-transistor and all sub transistorized grid voltages differ at most V _REF/ 2 ^MIn Fig. 4, Darlington 409, and Darlington 410 also comprises four sub-transistor 410a-d.Because this a little transistor all has about equally geometry, drain current about equally and similar grid voltage, so its mutual conductance all is roughly the same.

Resistive element group 401 and the switching device group 402 of switching are used to provide two simulation outputs, rather than one.Switching device group 402 by the sub-word control of MS numeral provides output voltage V ₁=k _MV _REF/ 2 ^M, V ₂=(k _M+ 1) V _REF/ 2 ^MThe sub-word control switch device group 404 of LS numeral.Switching device 405,406 and 407 is illustrated in their normal position and k _L=0 is consistent, voltage V ₁Be coupled to respectively sub-transistor 409b, the grid of 409c and 409d.If k _L=1 o'clock, switching device 405 was moved to its position that substitutes; If k _L=2 o'clock, switching device 405 and 406 was moved to its position that substitutes; If k _L=3, switchgear 405,406 and 407 all is moved to its position that substitutes.In the ordinary course of things, at the k of the switching device of switching device group 404 _LThe alternative site at them, and 2 ^L-k _LIt is the normal position at them.When the position that substitutes, switchgear 405,406 and 407 grid voltage V2 are coupled to respectively sub-transistor 409b, 409c and 409d.

As previously mentioned, if k _L=0 o'clock, switch element 405,406 and 407 all was the normal position at them.Therefore, all transistorized grids at LSDTS408 all are coupled to V ₁, and the electric current that these transistorized drain electrodes are flowed out equates basically.Therefore, in this case, do not affect output voltage at LS word.The grid of transistor 103 is coupled to V ₁, and the negative feedback of the grid of transistor 104 output can guarantee that output voltage is substantially equal to V ₁, or V _OUT=k _MV _REF/ 2 ^M(6)

If k _LNon-vanishing, the grid in the sub-transistor of Darlington 409 is coupled to V ₂, and 2 ^L-k _LBe coupled to V ₁The grid of Darlington 410 also all is coupled to V1.By this way, corresponding to k _LThe convergent-divergent summation is the input of Darlington 409, and this will cause LSDTS408 to produce the difference output current of modulation.

If transistor 409 all 2 ^LIndividual sub-transistor has identical small signal, and LSDTS408 can produce certain difference output current.The ratio of output current and input voltage is g _ML, this parameter is passed through the value of current source 411 by the geometric properties decision of transistor 409 and 410.If the transistorized grid of any single son of Darlington 409 is provided a little signal voltage, every other sub-transistor all is coupled to V ₁, the ratio of output current and input voltage will be g _ML/ 2 ^L(perhaps as shown in Figure 4 g _ML/ 4).Therefore, the difference output current dI=k of LSDTS408 _Lg _ML(V ₂-V ₁)/2 ^L

Note that V ₂-V ₁The voltage at each the resistive element two ends in group 401, by V _REF/ 2 ^MProvide, so that dI=k _Lg _MLV _REF/ (2 ^M2 ^L)=k _Lg _MLV _REF/ 2 ^N(7)

Because negative feedback, this differential current is by the variation dI=g of output voltage _MMThe dV balance that dV provides.(8)

In equation (7) substitution equation (8), and find the solution variation at output voltage, dv=(g _ML/ g _ML) k _LV _REF/ 2 ^N

This variation is added to existing output voltage, and this sub-word by MS determines, and provides at equation (6).Consequent output voltage V _OUT=k _MV _REF/ 2 ^M+ (g _ML/ g _MM) k _LV _REF/ 2 ^N(9)

In DAC300, g is compared in the mutual conductance in the superincumbent equation _ML/ g _MMCan controlled parameter.Along with g _ML/ g _MM=1 o'clock, the output voltage as by equation (9) definition became V _OCT=(2 ^Lk _M+ k _L) V _REF/ 2 ^N=k V _REF/ 2 ^N

Therefore, by selecting suitable mutual conductance ratio, the decimal system equivalence of the output voltage of DAC400 and digital input word k is proportional.

The voltage of the output voltage of being determined by MS word is added in the control of the sub-word of LS to.If select suitable mutual conductance ratio, LS word provides voltage increment to be inserted in the output voltage, so that it is positioned at k _MV _REF/ 2 ^M(k _M+ 1) V _REF/ 2 ^MBetween.

According to principle of the present invention, can use various alternative design to realize LSDTS408.For example, Darlington 410 can change a transistor that geometrical equivalence is single into.In addition, each Darlington can comprise greater or less than 2 ^LIndividual transistor, and different geometry associativities is also arranged between the transistor.

As above-mentioned, the sensitivity that DAC400 group has been removed the tap error circuit, its reduces the common-mode voltage that the transistorized mutual conductance with the differential transconductance level changes.Yet, still need mutual conductance to compare g _ML/ g _MMKeep accurately.If accurately do not keep the mutual conductance ratio, nonmonotonic behavior may occur.

The mutual conductance of accurately determining among the DAC500 in Fig. 5 has not needed than, the figure shows the most preferred embodiment of the present invention.No matter the behavior of also maintenance bond monotonicity of embodiment is group tap error.Situation shown in Fig. 5 is L=2.Obviously, this number is arbitrarily, and any value of L and M can realize DAC500.

DAC500 uses identical resistive element group and switching device group such as DAC400, and uses identical Darlington.Yet DAC500 does not have independent MS and LS differential transconductance level.DAC500 has a single DTS, and it has compound PMOS transistor 409 and 410.Current source 411 provides source electrode for

transistor

409 and 410, and their drain electrode (forming respectively the first and second differential currents of transconductance stage 408), and it is coupled to the drain electrode of nmos pass transistor 105 and 106.

Transistor

105 and 106 is connected current mirror.The drain electrode of transistor 105 is coupled to the input of high-gain inverting amplifier 108.The output of amplifier 108 is fed back to the grid of transistor 410, and the output voltage V of DAC500 is provided _Out

As at DAC400, control switch device group 402 by the sub-word of MS numeral so that V ₁=k _MV _REF/ 2 ^M(10)

V ₂＝(k _M+1)V _REF/2 ^M。(11)

The sub-word control switch device group 404 of LS numeral makes k _LSwitching device be switched to they alternative site and 2 ^L-k _LSwitching device remains on their normal position.

The differential pair that differential pair 409-410 can be counted as by four sons forms, and is respectively 409a-410a, 409b-410b, 409C-410c and 409D-410D.If the right geometry of every height is identical, all sons be to will having mutual conductance about equally so, and the right mutual conductance of every height will equal a composite difference to 1/2 of the mutual conductance of 409-410 ^L

The increment of LS word is produced by a switching device group 404, with the grid of a Darlington 409 from V ₁Be transformed into V ₂If LS word is zero, the grid of all Darlingtons 409 is coupled to V ₁, V _OUTTo be substantially equal to V ₁, because V ₁=k _MV _REF/ 2 ^M, V _OUTAnd k _MWill be about equally.Yet, if the grid of all Darlingtons 409 (purpose in order to discuss comprises 409a) is coupled to V ₂, V so _OUTTo be substantially equal to V ₂, because V ₂=(k _M+ 1) V _REF/ 2 ^M, V _OUTBe substantially equal to (k _M+ 1) V _REF/ 2 ^MIn the situation that these two extreme, if only have the grid of a Darlington 409 to be coupled to V2, and remaining 2 ^L-1 is coupled to V1, and VOUT will be substantially equal to V1 and add 1/2 of difference between 1/2L times of V1 and the V2 so ^LThat is to say, when a sub-transistor of the grid that switches to V2 from V1, VOUT will move (V to V2 from V1 ₂-V1)/2 ^LSimilarly, when the transistorized grid of every height switches to V2 from V1 subsequently, VOUT will further move (V towards V2 ₂-V ₁) 2 ^LIf all sub transistorized grids switch to V2,, VOUT will equal V2 (but in the example of Fig. 4, grid device 409a does not switch to V2).In the ordinary course of things, V _OUT=V ₁+ k _L(V ₂-V ₁)/2 ^L(12)

The increment of MS word is so that switches set 402 mobile V1 and V2 on group 401.k _LWhen getting maximum, the grid of the transistor 409 except switches to V2 (namely except the grid of 409a), output voltage V _OUTTo be an increment that is lower than V2, or V _OUT=V ₁+ (2 ^L-1) (V ₂-V ₁)/2 ^L=V ₂-(V ₂-V ₁)/2 ^LDAC exports next step and occurs, and all switches of switches set 404 turn back to V1, MS switches set 402 tap of rising, so that V1 has the original value of V2, and the V2 of the MS tap of having risen.At this moment, the grid of all Darlingtons 409 switches to the new value (being the original value of V2) of V1.Then V _OUTChange into to new V1 value (the namely old value of present V2) from its old value (increment under the old value of V2).Therefore, along with LS word resets and the sub-word of MS increases, the output voltage increment (V that moves up ₂-V ₁)/2 ^L, and monotonicity also is guaranteed.

With equation (10) and (11) substitution (12), cause after the certain operations:

V _OUT＝(2 ^L?k _M+k _L)V _REF/2 ^N

＝kV _REF/2 ^N

Therefore, DAC500 provides the conversion of the digital to analogy of dullness, is independent of group tap error, and does not need accurate mutual conductance than control, and the sub-fraction of resistive element and switching device is also arranged.

Fig. 6 shows the input stage 600 of interpolative operation amplifier of the present invention, and this extracts from Fig. 5.This input stage can be used in the digital-to-analog converter application program in addition.Its effectiveness is from the fact, and namely it is used in node 604 a simulation output V is provided _OUT, can carry out interpolation between two analog inputs,

node

601 and 602 V1 and V2.Circuit 600 can be broad sense, by from 604 output nodes to 601, feedback network of any input node coupling of 602 and 603.In addition, the grid of Darlington 410 does not need whole linking together as Fig. 6.

The circuit of Fig. 3 to 5 (especially DAC300) can be used as digital-to-analog converter.In this application, LS word can replace control bit to be used for correcting the error of MS word conversion.In this case, LS word does not add more resolution, but proofreaies and correct each MS tap error by the LS circuit that applies a unique figure adjustment word.The correction that the tap that specific figure adjustment word is selected by the MS word needs determines.The word of figure adjustment can be stored in a position of being determined by the MS word in the internal storage (not shown).Memory device just can automatic coupling to the corresponding figure adjustment word of LS circuit.

Therefore, circuit is utilized for the M signal summation in the DAC of a segmentation, and be used for converting a digital input word to analog output voltage, so that analog output voltage is the monotonic function of digital input word, this circuit uses the minimum number of switch element and resistive element.

Although various elements are connected to other element in the preferred embodiment of circuit, one it will be appreciated by one of skill in the art that, this connection to direct assembly with being connected may be dispensable, can interconnect between the shown coupling assembling, and not break away from spirit of the present invention.To understand also that those skilled in the art except said elements, the present invention also is adaptable.For example, buffer 109 and interpolative operation amplifier shown in Figure 5 may be by the feedback configuration of the negative input end that outputs to it from it, gain except unit is arranged, this circuit can expand to LS or the MS position of any amount, the switch of switching device group 404 can increase by one (thermometer-code) at every turn or switch to binary combination (1,2,4,8 etc.), if necessary, this circuit can design and comprise bipolar transistor.It and bias current compensation prevent the overload of resistive element group, rather than MOS transistor, and circuit can use in AD converter.Any type of DAC can produce resistive element group 401 and the switching device group 402 that two adjacent rank are used for replacing Fig. 4 or Fig. 5.In addition, the operational amplifier of Fig. 6 can be used for other to be used, and without DAC, carries out interpolation between any two voltages.In addition, the difference current that the current mirrors that

transistor

105 and 106 forms and inverting amplifier 108 consist of the single ended output voltage switching stage together can change in fact other any differential currents of the electric pressure converter of conventional Amplifier Design into.The present invention is embodied by instantiation, and specification is that explanation of the present invention is not limited the present invention.Therefore, as long as no breaking away from essence of the present invention and meeting definition in the claim, make various modifications at above-mentioned example and still belong to category of the present invention.

Claims

1. digital analog converter, it is characterized in that: a circuit can convert digital input signals to the analog output signal of corresponding this digital signal of expression of energy, this digital signal comprises a plurality of positions, be divided into first group of M significant bits and second group of L time significant bits, this circuit comprises: the first and second signal generation devices are used for converting to and corresponding the first and second bit groups of the first and second quantized analog signals;

Amplifier installation is coupled to above-mentioned the first and second signal generation devices, a simulation output node is arranged and produce an analog output signal at this Nodes, this amplifier installation comprises: the first differential transconductance level produces first differential current, this current response in the first quantized analog signal and from the simulation output node feedback signal between poor, wherein, the first differential current can cause amplifier installation the first assembly to produce an analog output signal, value in this signal and the first bit group is roughly proportional, and the second differential transconductance level produces the second differential current, poor between above-mentioned the second quantized analog signal and reference signal of this current response, the second differential current is combined in the first differential current of amplifier installation, to offset the analog output signal that is produced by the second assembly, the value in this signal and the second bit group is roughly proportional.

2. digital analog converter according to claim 1, it is characterized in that: the first and second signal generation apparatus comprise a ladder shaped resistance element, have a plurality of voltage taps, be used for selecting a voltage tap to provide the first and second quantized analog signals to be coupled to separately corresponding one group of switching device.

3. digital analog converter according to claim 2, it is characterized in that: the first and second differential transconductance levels have one with respect to the analog output signal of the mutual conductance proportional zoom of the first component second component.

4. digital analog converter according to claim 3, it is characterized in that: differential current comprises a current mirror and an inverting amplifier to the translate phase of voltage, inverting amplifier has an input and an output, its input is coupled in the difference current output device of the first differential transconductance, for example, the output of inverting amplifier provides analog output signal.

5. digital analog converter according to claim 4, it is characterized in that: the circuit that the first and second differential transconductance levels define respectively helps the first and second voltage components of analog output signal, the value of the first and second corresponding one voltage components in first of the value of each proportional relation and the second hyte of the second bit group, and the proportionate relationship of wherein said the second composition is determined by the ratio of the mutual conductance of above-mentioned the first and second differential transconductance levels at least in part.

6. digital analog converter according to claim 5 is characterized in that: the circuit that defines in above-mentioned first group of switching device and the second group of switching device is normally by the Digital Signals corresponding to the first bit group; The 3rd group of switching device is by the Digital Signals corresponding to the second bit group; The 3rd group of switching device is coupled in first group of switching device and second group of switching device, and the output of the second differential transconductance device is provided.

7. digital analog converter according to claim 6, it is characterized in that: above-mentioned the second differential transconductance level comprises: a current source; The first Darlington has a plurality of transistors, and the first Darlington has a plurality of inputs, and this input is corresponding to first group of input of above-mentioned the second differential transconductance level; The second Darlington has a plurality of transistors, and the second Darlington has a plurality of inputs, and this input is corresponding to second group of input of above-mentioned the second differential transconductance level; The second Darlington is coupled in the one the second difference currents output of current source and the second differential transconductance level; Above-mentioned each Darlington comprises 2 two transistors.

8. digital analog converter according to claim 7, it is characterized in that: an operation amplifier circuit carries out interpolation between the first and second analog input signals, this circuit is based on the digital signal of L bit and have minimum and peak, and this operational amplifier comprises:

Differential stage has a composite inputting device, and its at least one input is coupled to receive the first analog input signal, and contains at least L control input end, and this differential stage produces an analog output signal, and the first assembly represents the first analog input signal;

At least contain L switching device and be coupled to the control input end, be used for parameter in response to the side-play amount of the digital signal of L bit of modulation, wherein the second assembly is added to analog output signal, the value of the second assembly is a monotonic function of L bit digital signal, so that analog output signal is in response to the mumber.min_value of L bit, express substantially the first analog input signal, in response to the maximum of the digital sub-word of L bit, express substantially the second analog input signal.

9. digital analog converter according to claim 8, it is characterized in that: the digital correction signal of above-mentioned L position is stored in the determined position of digital input signals of the M position in the memory.