CN103368528B - Agitator - Google Patents
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- CN103368528B CN103368528B CN201310321029.5A CN201310321029A CN103368528B CN 103368528 B CN103368528 B CN 103368528B CN 201310321029 A CN201310321029 A CN 201310321029A CN 103368528 B CN103368528 B CN 103368528B
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- 238000007493 shaping process Methods 0.000 claims abstract description 39
- 230000005540 biological transmission Effects 0.000 claims description 35
- 230000003139 buffering effect Effects 0.000 claims description 3
- 238000004513 sizing Methods 0.000 claims description 2
- 101100464779 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CNA1 gene Proteins 0.000 description 12
- 101150110971 CIN7 gene Proteins 0.000 description 10
- 101150110298 INV1 gene Proteins 0.000 description 10
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 7
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 7
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 6
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 4
- 101100464782 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CMP2 gene Proteins 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 101150070189 CIN3 gene Proteins 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 238000003359 percent control normalization Methods 0.000 description 1
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Abstract
The open a kind of agitator of the present invention, at least includes: charge-discharge modules, connects a supply voltage, produce a sawtooth waveforms by discharge and recharge and export to Shaping Module；Shaping Module, has two inputs, connects the sawtooth waveforms output of a reference voltage and this charge-discharge modules respectively, delivers to duty cycle adjustment module by producing a burst pulse after comparing this reference voltage with sawtooth waveforms output；Duty cycle adjustment module, the burst pulse obtained is divided, to obtain the clock signal that dutycycle is 50%, the present invention only need to use better simply charge-discharge circuit and comparator, d type flip flop to achieve that the clock signal that dutycycle is 50%, not only area savings 50%, optimize power consumption, and dutycycle is more accurate.
Description
Technical field
The present invention, about a kind of agitator, particularly relates to the agitator that a kind of dutycycle is 50%.
Background technology
EEPROM(Electrically Erasable Programmable Read-Only Memory, electric erasable and programmable
Journey read only memory) it is frequently necessary to utilize the clock needed for agitator generation high voltage electricity pump, general electric charge pump is at clock duty
Higher than efficiency when being 50%.Fig. 1 is the circuit diagram of traditional agitator, and Fig. 2 is that the simulation result of traditional oscillators shows
It is intended to.As shown in Figures 1 and 2, agitator includes transmission gate T1/T2, current source I1/I2, comparator CMP1/CMP2, NAND gate
AND1/AND2 and phase inverter INV1/INV2/INV3/INV4/INV5, its ultimate principle is: time initial, VC is 0, comparator
CMP1 output low level 0, comparator CMP2 exports high level 1, then NAND gate AND1 output high level 1, NAND gate AND2 by
Being 1 in two inputs and export CK0 is 0, and the NAND gate AND1 output anti-phase low level 0 that obtains of high level 1 inverted device INV1,
This low level 0 controls transmission gate T2 and closes, and NAND gate AND1 output high level 1 inverted device INV1, INV2 is anti-phase obtains high electricity
Flat 1, this high level 1 controls transmission gate T1 and opens, and current source I1 charges to electric capacity C, when VC is increased over Vref-, compares
Device CMP1 exports high level 1, and at VC, <before Vref+, comparator CMP2 exports high level 1, when VC is more than Vref+, comparator
CMP2 output low level 0, CK0 becomes high level 1 therewith, and NAND gate AND1 exports become 0 because two inputs are 1, this low electricity
Mean longitude phase inverter INV1 anti-phase output high level 1, this high level opens transfer tube T2 by electric capacity C electric discharge, NAND gate AND1 simultaneously
Output low level 0 obtain low level 0 through two phase inverters INV1, INV2 are anti-phase, this low level closing transmission pipe T1, cut-out is filled
Electric pathway, thus VC begins to decline, when VC is brought down below Vref-, comparator CMP1 output low level 0 makes NAND gate AND1
Output becomes high, and NAND gate AND2 exports CK0 because of two inputs become low level 0 for high level 1, and the maintenance that so goes round and begins again is steady
Fixed vibration, CK0 obtains exporting CKOUT through 3 inverter buffer.
Visible, traditional oscillators generally requires two comparators and complexity to obtain the clock signal that dutycycle is 50%
Control circuit of duty ratio, so cause circuit area big, power consumption is high, is unfavorable for circuit design.
Summary of the invention
For overcoming what above-mentioned prior art existed to cause the problem that the big power consumption of circuit area is high, the main object of the present invention exists
In providing a kind of agitator, it need to use better simply charge-discharge circuit and comparator, d type flip flop to achieve that dutycycle is
The clock signal of 50%, not only area savings 50%, optimizes power consumption, and dutycycle is more accurate.
For reaching above and other purpose, the present invention provides a kind of agitator, at least includes:
Charge-discharge modules, connects a supply voltage, produces a sawtooth waveforms by discharge and recharge and exports to Shaping Module；
Shaping Module, has two inputs, connects the sawtooth waveforms output of a reference voltage and this charge-discharge modules respectively, passes through
Produce a burst pulse after this reference voltage is compared with sawtooth waveforms output and deliver to duty cycle adjustment module；
Duty cycle adjustment module, divides the burst pulse obtained, to obtain the clock signal that dutycycle is 50%.
Further, this Shaping Module outputs it and feeds back to this charge-discharge modules to control its discharge and recharge
Further, this charge-discharge modules includes a constant-current source, a transmission gate, an electric capacity, a NMOS tube, the first phase inverter
And second phase inverter, wherein this constant-current source, this transmission gate and this capacitances in series are between this supply voltage and ground, this transmission gate with
The intermediate node of this electric capacity is connected to this Shaping Module to export this sawtooth waveforms, simultaneously the intermediate node of this transmission gate and this electric capacity
Being also attached to the drain electrode of this NMOS tube, this NMOS tube source ground, grid connects the outfan of this first phase inverter, and this is first anti-phase
The outfan of device be connected to this transmission gate also by this second phase inverter, the input of this first phase inverter terminates this Shaping Module
Outfan, to obtain forward burst pulse after the burst pulse that this Shaping Module produces being buffered, feeds back this forward burst pulse
To charge-discharge modules to control its discharge and recharge
Further, this charge-discharge modules includes a constant-current source, a transmission gate, an electric capacity and a PMOS, wherein should
Constant-current source, this transmission gate and this electric capacity are connected in series with between this supply voltage and ground, and this transmission gate connects with the intermediate node of this electric capacity
Be connected to this Shaping Module to export this sawtooth waveforms, simultaneously the intermediate node of this transmission gate and this electric capacity be also attached to this PMOS it
Source electrode, this PMOS grid connects the outfan of this Shaping Module, grounded drain, and the outfan of this Shaping Module is also connected to this simultaneously
Transmission gate.
Further, this Shaping Module includes a comparator, and this comparator in-phase input end connects this reference voltage, anti-phase defeated
Entering to be terminated at the outfan of this charge-discharge modules, this comparator is defeated after being compared with the output of this charge-discharge modules by this reference voltage
Go out burst pulse.
Further, this duty cycle adjustment module at least includes a d type flip flop, and the input end of clock of this d type flip flop connects this
The output of comparator, reversed-phase output connects input, and after the output of this Shaping Module being divided, positive output end exports
Dutycycle is the clock signal of 50%.
Further, this duty cycle adjustment module also includes that the 3rd phase inverter, the 3rd inverter input connect this shaping
Module, output terminates the input end of clock of this d type flip flop, to divide again after anti-phase for the output of this Shaping Module, output
Dutycycle is the clock signal of 50%.
Further, this d type flip flop is except 2 frequency dividers.
Compared with prior art, one agitator of the present invention utilizes charge-discharge modules to produce a sawtooth waveforms, passes through sizing die
Block compares generation one burst pulse to the output of reference voltage and charge-discharge modules, and this burst pulse is passed through duty cycle adjustment
Module divides, it is thus achieved that dutycycle is the clock signal of 50%, compares traditional oscillators, the circuit of the present invention not only area savings
About 50%, power consumption is optimized, and the dutycycle of the clock signal obtained is more accurate.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of traditional agitator；
Fig. 2 is the simulation result schematic diagram of traditional oscillators；
Fig. 3 is the circuit diagram of the first preferred embodiment of a kind of agitator of the present invention；
Fig. 4 is the simulation result schematic diagram of present pre-ferred embodiments；
Fig. 5 is the circuit diagram of the first preferred embodiment of a kind of agitator of the present invention.
Detailed description of the invention
Below by way of specific instantiation accompanying drawings embodiments of the present invention, those skilled in the art can
Further advantage and effect of the present invention is understood easily by content disclosed in the present specification.The present invention also can be different by other
Instantiation implemented or applied, the every details in this specification also can based on different viewpoints and application, without departing substantially from
Various modification and change is carried out under the spirit of the present invention.
Fig. 3 is the circuit diagram of the first preferred embodiment of a kind of agitator of the present invention.As it is shown on figure 3, the present invention
Plant agitator, including: charge-discharge modules 301, Shaping Module 302 and duty cycle adjustment module 303.
Wherein, charge-discharge modules 301 connects a supply voltage VDD, produces a sawtooth waveforms VC output to whole by discharge and recharge
Shape module 302；Shaping Module 302, its input connects the sawtooth waveforms output VC of a reference voltage Vref and charge-discharge modules, logical
Cross and produce burst pulse CK0 after reference voltage Vref and sawtooth waveforms output VC is compared and deliver to duty cycle adjustment module 303,
Meanwhile, Shaping Module 302 also outputs it and feeds back to charge-discharge modules 301 to control its discharge and recharge；Duty cycle adjustment module 303
Burst pulse CK0 obtained is divided, obtains the clock signal that dutycycle is 50%.
In first preferred embodiment of the present invention, charge-discharge modules 301 include constant-current source I1, transmission gate T1, electric capacity C,
NMOS tube N1, the first phase inverter INV1 and the second phase inverter INV2, wherein constant-current source I1, transmission gate T1 and electric capacity C are connected in series with electricity
Between source voltage VDD and ground, the intermediate node of transmission gate T1 and electric capacity C is connected to Shaping Module 302 export sawtooth waveforms VC, together
Time transmission gate T1 and electric capacity C intermediate node be also attached to the drain electrode of NMOS tube N1, NMOS tube N1 source ground, grid connects first
The outfan of phase inverter INV1, the outfan of the first phase inverter INV1 be connected to transmission gate T1 also by the second phase inverter INV2,
The outfan of the input termination Shaping Module 302 of the first phase inverter INV1, to enter burst pulse CK0 that Shaping Module 302 produces
Obtain forward burst pulse CK1 after row buffering, forward burst pulse CK1 is fed back to charge-discharge modules 301 to control its discharge and recharge.
Shaping Module 302 includes a comparator CMP1, and comparator CMP1 in-phase input end vp connects reference voltage Vref, anti-phase
Input vn is connected to the outfan of charge-discharge modules 301, i.e. receives the sawtooth waveforms VC that charge-discharge modules 301 produces, comparator
Reference voltage Vref is compared output burst pulse CK0 afterwards by CMP1 with VC；Duty cycle adjustment module 303 at least includes a d type flip flop
D1, the input end of clock of d type flip flop D1 meets the output CK0 of comparator CMP1, and reversed-phase output Q meets input D, to be entered by CK0
After row frequency dividing, positive output end Q output duty cycle is clock signal CKOUT of 50%, it is also preferred that the left duty cycle adjustment module 303 is also
Including the 3rd phase inverter INV3, the 3rd phase inverter INV3 input termination Shaping Module 302, output termination d type flip flop D1 time
Clock input, to divide after anti-phase for CK0, output duty cycle is clock signal CKOUT of 50% again.
Time initial, VC is 0, and owing to it connects comparator CMP1 inverting input, comparator CMP1 in-phase input end connects reference
Voltage Vref, therefore comparator CMP1 output CK0 is 1, is 0 through the first anti-phase CK1 of obtaining of phase inverter INV1, the low level 0 of CK1 is closed
Closing NMOS tube N1, CK1 is high level 1 through the second anti-phase CK2 of obtaining of phase inverter INV2, and the high level 1 of CK2 is opened transfer tube T1 and connect
Logical constant-current source I1, constant-current source I1 charge to electric capacity C through transfer tube T1, and when VC is increased over Vref, comparator CMP1 exports
Low level 0, i.e. CK0 step-down, then CK1 uprises, and opens NMOS tube N1 and is discharged by electric capacity C, CK2 step-down closing transmission pipe simultaneously
T1, constant-current source I1 are cut-off, and electric capacity C does not has a charge path and only this discharge path of NMOS tube N1, and VC will quickly decline, from
And making CK0 quickly reply high level, such CK0 is a negative-going pulse with narrower groove.Fig. 4 is that the present invention is the most real
Executing the simulation result schematic diagram of example, as shown in Figure 4, CK1 is a forward burst pulse.Negative sense burst pulse CK0 is through the 3rd phase inverter
Being sent to the input end of clock of d type flip flop D1 after INV3 buffering, the output CKOUT of this d type flip flop D1 is a dutycycle
The clock of 50%, in present pre-ferred embodiments, d type flip flop D1 is except 2 frequency dividers, and the present invention is not limited.
Fig. 5 is the circuit diagram of the second preferred embodiment of a kind of agitator of the present invention.The most real in the present invention second
Executing in example, charge-discharge modules 301 includes constant-current source I1, transmission gate T1, electric capacity C and PMOS P1, wherein constant-current source I1, transmission
Door T1 and electric capacity C is connected in series with between supply voltage VDD and ground, and the intermediate node of transmission gate T1 and electric capacity C is connected to Shaping Module
302 to export sawtooth waveforms VC, and the intermediate node of transmission gate T1 and electric capacity C is also attached to the source electrode of PMOS P1, PMOS simultaneously
Grid connects the outfan CK0 of Shaping Module 302, grounded drain, and the outfan CK0 of Shaping Module 302 is also connected to transmission gate simultaneously
T1.Other parts are the most identical with the first preferred embodiment, and at this, then it will not go into details.
Visible, one agitator of the present invention utilizes charge-discharge modules to produce a sawtooth waveforms, by Shaping Module to reference to electricity
The output of pressure and charge-discharge modules compares generation one burst pulse, and this burst pulse is divided by duty cycle adjustment module,
Obtain the clock signal that dutycycle is 50%, compare traditional oscillators, the circuit of the present invention not only area savings about 50%, merit
Consumption is optimized, and the dutycycle of the clock signal obtained is more accurate.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any
Above-described embodiment all can be modified under the spirit and the scope of the present invention and change by skilled person.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (6)
1. an agitator, at least includes:
Charge-discharge modules, connects a supply voltage, produces a sawtooth waveforms by discharge and recharge and exports to Shaping Module；
Shaping Module, has two inputs, connects the sawtooth waveforms output of a reference voltage and this charge-discharge modules respectively, by this
Reference voltage produces a burst pulse after comparing with sawtooth waveforms output and delivers to duty cycle adjustment module；
Duty cycle adjustment module, divides the burst pulse obtained, to obtain the clock signal that dutycycle is 50%；
Wherein, this Shaping Module outputs it and feeds back to this charge-discharge modules to control its discharge and recharge；This charge-discharge modules includes
One constant-current source, a transmission gate, an electric capacity, a NMOS tube, the first phase inverter and the second phase inverter, wherein this constant-current source, this transmission
Door and this capacitances in series are between this supply voltage and ground, and this transmission gate is connected to this Shaping Module with the intermediate node of this electric capacity
To export this sawtooth waveforms, the intermediate node of this transmission gate and this electric capacity is also attached to the drain electrode of this NMOS tube, this NMOS tube simultaneously
Source ground, grid connects the outfan of this first phase inverter, the outfan of this first phase inverter also by this second phase inverter
Being connected to this transmission gate, the input of this first phase inverter terminates the outfan of this Shaping Module, narrow with produced by this Shaping Module
Pulse obtains forward burst pulse after buffering, this forward burst pulse feeds back to charge-discharge modules to control its discharge and recharge.
2. a kind of agitator as claimed in claim 1, it is characterised in that: this charge-discharge modules includes a constant-current source, a transmission
Door, an electric capacity and a PMOS, wherein this constant-current source, this transmission gate and this electric capacity are connected in series with between this supply voltage and ground,
The intermediate node of this transmission gate and this electric capacity is connected to this Shaping Module to export this sawtooth waveforms, this transmission gate and this electric capacity simultaneously
Intermediate node be also attached to the source electrode of this PMOS, this PMOS grid connects the outfan of this Shaping Module, grounded drain, with
Time this Shaping Module outfan be also connected to this transmission gate.
3. a kind of agitator as claimed in claim 1 or 2, it is characterised in that: this Shaping Module includes a comparator, and this compares
Device in-phase input end connects this reference voltage, and anti-phase input is terminated at the outfan of this charge-discharge modules, and this comparator is by this reference
Voltage exports burst pulse after comparing with the output of this charge-discharge modules.
4. a kind of agitator as claimed in claim 3, it is characterised in that: this duty cycle adjustment module at least includes that a D triggers
Device, the input end of clock of this d type flip flop connects the output of this comparator, and reversed-phase output connects input, with by this Shaping Module
After output divides, positive output end output duty cycle is the clock signal of 50%.
5. a kind of agitator as claimed in claim 4, it is characterised in that: this duty cycle adjustment module also includes that the 3rd is anti-phase
Device, the 3rd inverter input connects this Shaping Module, and output terminates the input end of clock of this d type flip flop, with by this sizing die
Dividing after the output of block is anti-phase, output duty cycle is the clock signal of 50% again.
6. a kind of agitator as claimed in claim 5, it is characterised in that: this d type flip flop is except 2 frequency dividers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310321029.5A CN103368528B (en) | 2013-07-26 | 2013-07-26 | Agitator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310321029.5A CN103368528B (en) | 2013-07-26 | 2013-07-26 | Agitator |
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| CN103368528A CN103368528A (en) | 2013-10-23 |
| CN103368528B true CN103368528B (en) | 2016-12-28 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104578756B (en) * | 2014-12-25 | 2017-10-13 | 长安大学 | A kind of DC DC pierce circuits of dual output |
| CN105703712B (en) * | 2015-12-31 | 2019-04-09 | 峰岹科技（深圳）有限公司 | High-precision RC oscillator |
| CN110220924B (en) * | 2019-05-24 | 2024-09-20 | 北京中泰通达科技发展有限公司 | Dangerous liquid detection device and detection method |
| CN111181552B (en) * | 2020-01-08 | 2023-03-24 | 电子科技大学 | Bidirectional frequency synchronous oscillator circuit |
| CN113490303B (en) * | 2021-07-19 | 2025-02-28 | 上海裕芯电子科技有限公司 | An intelligent discharge circuit |
| CN113938004B (en) * | 2021-08-31 | 2024-04-05 | 西安电子科技大学 | Voltage doubling inverter, power supply voltage conversion circuit and electronic product |
| CN115459747B (en) * | 2022-08-12 | 2023-09-01 | 北京伽略电子股份有限公司 | Sawtooth wave generating circuit with phase detection function and control method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5990753A (en) * | 1996-01-29 | 1999-11-23 | Stmicroelectronics, Inc. | Precision oscillator circuit having a controllable duty cycle and related methods |
| US6348821B1 (en) * | 1998-07-30 | 2002-02-19 | Stmicroelectronics S.R.L. | Frequency doubler with 50% duty cycle output |
| CN101409553A (en) * | 2008-11-20 | 2009-04-15 | 四川登巅微电子有限公司 | Phase delay line structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6967508B2 (en) * | 2004-03-04 | 2005-11-22 | Texas Instruments Incorporated | Compact frequency doubler/multiplier circuitry |
| US8884676B2 (en) * | 2011-08-23 | 2014-11-11 | National Semiconductor Corporation | Clock generator with duty cycle control and method |
-
2013
- 2013-07-26 CN CN201310321029.5A patent/CN103368528B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5990753A (en) * | 1996-01-29 | 1999-11-23 | Stmicroelectronics, Inc. | Precision oscillator circuit having a controllable duty cycle and related methods |
| US6348821B1 (en) * | 1998-07-30 | 2002-02-19 | Stmicroelectronics S.R.L. | Frequency doubler with 50% duty cycle output |
| CN101409553A (en) * | 2008-11-20 | 2009-04-15 | 四川登巅微电子有限公司 | Phase delay line structure |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140509 |
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Effective date of registration: 20140509 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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