CN103368360A - Switching power supply control method, switching power supply control circuit and switching power supply - Google Patents
Switching power supply control method, switching power supply control circuit and switching power supply Download PDFInfo
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Abstract
The invention discloses a switching power supply control method, a switching power supply control circuit and a switching power supply. A driving signal used for driving a main power level circuit to start according to different frequencies is generated and sent according to a first control signal and a second control signal, even if the system is located at a light load mode, the main power level circuit can also start and close corresponding frequency according to the driving signal instead of entering a sleep state so as to avoid the problem of low regulation ability of the main power level circuit on output voltage caused by overlow voltage on an output capacitor at the light load mode of the system, and noise capable of being heard by a human ear caused by the starting frequency of the main power level circuit is also avoided.
Description
Technical field
The present invention relates to the switch power technology field, relate in particular to a kind of Switching Power Supply control method, switching power source control circuit and Switching Power Supply.
Background technology
In the Switching Power Supply that adopts the peak current control mode, we adopt the output signal of error amplifier as the reference quantity of peak current usually, therefore, by high clamper value and low clamper value are set for the output signal of error amplifier, can obtain maximum and the minimum value of peak current.When the output signal of error amplifier was hanged down clamper, the expression system had entered the underloading pattern, and in the prior art, when system entered the underloading pattern, its most of modules were in the sleep state of closing.
This control mode of prior art can be saved system works in the power consumption of underloading pattern, but because under the underloading pattern, system master's power stage circuit enters sleep state and quits work, the energy of load can only be provided by output capacitance; When the voltage on the output capacitance was lower than certain value, system controlled main power stage circuit according to feedback signal and restarts; At main power stage circuit to the response speed of feedback signal not simultaneously, the time that system resumes work also can be different; When response speed was slower, low situation may appear in the voltage on the output capacitance, at this moment, will cause the main power stage circuit of system to restart rear regulating power reduction to output voltage.And when response speed slowly to a certain extent the time, even the frequency that causes the master of system power stage circuit to start can be reduced to the scope that people's ear can be heard, and then produces noise.
Summary of the invention
In view of this, the invention provides a kind of Switching Power Supply control method, switching power source control circuit and Switching Power Supply, low and can produce the problem of noise to the output voltage regulating power to solve prior art.
To achieve these goals, the existing scheme that proposes is as follows:
A kind of Switching Power Supply control method, the main power stage circuit for the control switch power supply may further comprise the steps:
Receive output voltage feedback signal and the output voltage reference signal of described main power stage circuit, and described output voltage feedback signal and described output voltage reference signal are compared and enlarged, generate and send the output voltage error signal;
Receive maximum output voltage error signal, instantaneous peak value voltage signal, drive signal and described output voltage error signal, when described output voltage error signal during greater than described maximum output voltage error signal, with described output voltage error signal clamper in described maximum output voltage error signal; And described output voltage error signal and instantaneous peak value voltage signal compared and generate comparative result, generate minimum ON time signal according to described driving signal, and generate and send the first control signal according to described comparative result and described minimum ON time signal;
Receive minimum output voltage error signal and described output voltage error signal, described output voltage error signal and minimum output voltage error signal are compared, and generate and send the second control signal according to comparative result;
Receive described the first control signal and the second control signal, according to described the first control signal and the second control signal, generate and send described driving signal to described main power stage circuit, drive described main power stage circuit and start according to different frequencies.
Preferably, when described output voltage error signal during greater than the maximum output voltage error signal, with described output voltage error signal clamper in described maximum output voltage error signal; Making described the first control signal is effective status when described peak voltage signal reaches described maximum output voltage error signal, and the frequency of described the second control signal is fixed frequency; Take the switching frequency of controlling the switching tube in the described main power circuit and ON time as fixed value, and the inductance peak current of controlling in the described main power circuit is stabilized in the maximum induction peak current.
Preferably, when described output voltage error signal during less than the maximum output voltage error signal and greater than the minimum output voltage error signal, making described the first control signal is effective status when described peak voltage signal reaches described output voltage error signal, and the frequency of described the second control signal is fixed frequency; Take the switching frequency of controlling the switching tube in the described main power circuit as fixed value, but ON time is followed described output voltage error signal intensity, and the inductance peak current of controlling in the described main power circuit is followed described output voltage error signal intensity.
Preferably, when described output voltage error signal during less than the minimum output voltage error signal, making described the first control signal is effective status when the ON time of described switching tube reaches minimum ON time, and the frequency of described the second control signal is followed described output voltage error signal intensity; Take the ON time of controlling the switching tube in the described main power circuit as fixed value, but switching frequency is followed described output voltage error signal intensity, and the inductance peak current of controlling in the described main power circuit is stabilized in the minimum inductance peak current.
Preferably, when described output voltage error signal during less than certain value, control described main power circuit and enter sleep pattern.
A kind of switching power source control circuit links to each other with Switching Power Supply master power stage circuit, and described switching power source control circuit comprises:
Error signal generation circuit, an input of described error signal generation circuit receive output voltage feedback signal as the input of described switching power source control circuit, link to each other with described main power stage circuit output; Described error signal generation circuit also receives the output voltage reference signal, and described output voltage feedback signal and described output voltage reference signal are compared and enlarged, and generates and sends the output voltage error signal;
The peak current control circuit, the input of described peak current control circuit links to each other with described error signal generation circuit output, receives described output voltage error signal; Described peak current control circuit also receives maximum output voltage error signal, instantaneous peak value voltage signal and drives signal, when described output voltage error signal during greater than described maximum output voltage error signal, with described output voltage error signal clamper in described maximum output voltage error signal; And described output voltage error signal and instantaneous peak value voltage signal compared and generate comparative result, generate minimum ON time signal according to described driving signal, and generate and send the first control signal according to described comparative result and described minimum ON time signal;
Frequency control circuit, the input of described frequency control circuit links to each other with described error signal generation circuit output, receives described output voltage error signal; Described frequency control circuit also receives the minimum output voltage error signal, described output voltage error signal and minimum output voltage error signal is compared, and generate and send the second control signal according to comparative result;
Drive signal generation circuit, the first input end of described drive signal generation circuit links to each other with described peak current control circuit output, receives described the first control signal; The second output of described drive signal generation circuit links to each other with described frequency control circuit output, receives described the second control signal; Described drive signal generation circuit is according to described the first control signal and the second control signal, generate and send described driving signal to described peak current control circuit and described main power stage circuit, drive described main power stage circuit and start according to different frequencies, the output of described drive signal generation circuit is the output of described switching power source control circuit.
Preferably, described error signal generation circuit comprises:
Error amplifier, the inverting input of described error amplifier receives described output voltage feedback signal as described error signal generation circuit input; The in-phase input end of described error amplifier receives the output voltage reference signal; The output of described error amplifier is the output of described error signal generation circuit, produces described output voltage error signal.
Preferably, described peak current control circuit comprises:
The first comparator, the inverting input of described the first comparator receives described output voltage error signal as described peak current control circuit input, and the in-phase input end of described the first comparator receives described instantaneous peak value voltage signal;
High clamp circuit, an end of described high clamp circuit links to each other with described the first comparator inverting input, receives described output voltage error signal, and the other end of described high clamp circuit receives described maximum output voltage error signal; When described output voltage error signal during greater than described maximum output voltage error signal, with described output voltage error signal clamper in described maximum output voltage error signal;
Time signal produces circuit, and the input that described time signal produces circuit receives described driving signal, and described time signal produces the output of circuit and exports described minimum ON time signal;
With door, the input of described and door links to each other with the output that described the first comparator and described time signal produce circuit respectively, described with output be the output of described peak current control circuit, generate described the first control signal; When described output voltage error signal greater than the maximum output voltage error signal, and the described peak voltage signal that receives of described the first comparator is when reaching described maximum output voltage error signal, described described the first control signal that becomes with the pupil is effective status; When described output voltage error signal less than the maximum output voltage error signal and greater than the minimum output voltage error signal, and when the described peak voltage signal that described the first comparator receives reached described output voltage error signal, described described the first control signal that becomes with the pupil was effective status; When described output voltage error signal less than the minimum output voltage error signal, and the described time signal minimum ON time that produces circuit evolving is when being high level, described described the first control signal that becomes with the pupil is effective status.
Preferably, described high clamp circuit is the first diode; The positive pole of described the first diode links to each other with described the first comparator inverting input, receives described output voltage error signal; The negative pole of described the first diode receives described maximum output voltage error signal.
Preferably, described high clamp circuit comprises: mirror current source and voltage follower;
One end of described mirror current source links to each other with described the first comparator inverting input, receives described output voltage error signal; The other end of described mirror current source links to each other with the output of described voltage follower;
The in-phase input end of described voltage follower receives described maximum output voltage error signal.
Preferably, described time signal generation circuit comprises:
Push-pull circuit, described push-pull circuit are connected between the current source of power supply and ground connection, and the input of described push-pull circuit receives described driving signal;
Electric capacity, an end of described electric capacity links to each other with the output of described push-pull circuit, the other end ground connection of described electric capacity;
Schmidt trigger, the input of described Schmidt trigger links to each other with the output of described push-pull circuit, and the output of described Schmidt trigger is exported described minimum ON time signal.
Preferably, described frequency control circuit comprises:
Operational transconductance amplifier, the inverting input of described operational transconductance amplifier receive described output voltage error signal as described frequency control circuit input, and the in-phase input end of described operational transconductance amplifier receives described minimum output voltage error signal; Described output voltage error signal and minimum output voltage error signal are compared, and the output comparative result;
One-way conduction circuit, the input of described one-way conduction circuit links to each other with described operational transconductance amplifier output, described one-way conduction circuit determines whether conducting according to the described comparative result that receives, and when described one-way conduction circuit conducting, described comparative result is transmitted;
Oscillator, the input of described oscillator links to each other with the output of described one-way conduction circuit, when described one-way conduction circuit conducting, receive described comparative result, and generate and send the second control signal that frequency is followed described output voltage error signal intensity according to described comparative result; When described not conducting of one-way conduction circuit, the frequency of described the second control signal that generates and sends is the natural frequency of described oscillator inside; The output of described oscillator is the output of described frequency control circuit.
Preferably, described drive signal generation circuit comprises: rest-set flip-flop;
The reset terminal R of described rest-set flip-flop is the first input end of described drive signal generation circuit;
The set end S of described rest-set flip-flop is the second input of described drive signal generation circuit;
The output Q of described rest-set flip-flop is the output of described drive signal generation circuit;
When described output voltage error signal during greater than the maximum output voltage error signal, switching frequency and ON time that described rest-set flip-flop is controlled the switching tube in the described main power circuit are fixed value, and the inductance peak current of controlling in the described main power circuit is stabilized in the maximum induction peak current.
When described output voltage error signal during less than the maximum output voltage error signal and greater than the minimum output voltage error signal, the switching frequency that described rest-set flip-flop is controlled the switching tube in the described main power circuit is fixed value, but ON time is followed described output voltage error signal intensity, and the inductance peak current of controlling in the described main power circuit is followed described output voltage error signal intensity.
When described output voltage error signal during less than the minimum output voltage error signal, the ON time that described rest-set flip-flop is controlled the switching tube in the described main power circuit is fixed value, but switching frequency is followed described output voltage error signal intensity, and the inductance peak current of controlling in the described main power circuit is stabilized in the minimum inductance peak current.
When described output voltage error signal during less than certain value, described rest-set flip-flop is controlled described main power circuit and is entered sleep pattern.
A kind of Switching Power Supply comprises main power stage circuit and the described switching power source control circuit of above-mentioned any one.
Can find out from above-mentioned technical scheme, Switching Power Supply control method disclosed by the invention, according to described the first control signal and the second control signal, generate and send and drive the driving signal that described main power stage circuit starts according to different frequency, when even system is in the underloading pattern, described main power stage circuit also can carry out according to described driving signal unlatching and the shutoff of corresponding frequencies, and can not enter sleep state, and then also avoided system when the underloading pattern, the problem that the described main power stage circuit that brownout on the output capacitance causes is low to the regulating power of output voltage, and the frequency of having avoided described main power stage circuit to start can be reduced to the noise that scope that people's ear can hear produces.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is Switching Power Supply control method flow chart disclosed by the invention;
Fig. 2 is disclosed another Switching Power Supply control method flow chart of another embodiment of the present invention;
Fig. 3 is disclosed another Switching Power Supply control method flow chart of another embodiment of the present invention;
Fig. 4 is disclosed another Switching Power Supply control method flow chart of another embodiment of the present invention;
Fig. 5 is disclosed another Switching Power Supply control method flow chart of another embodiment of the present invention;
Fig. 6 is the signal relation figure of the disclosed switching power source control circuit of another embodiment of the present invention;
Fig. 7 is the disclosed switching power circuit block diagram of another embodiment of the present invention;
Fig. 8 is the disclosed switching power source control circuit structure chart of another embodiment of the present invention;
Fig. 9 is disclosed another switching power source control circuit structure chart of another embodiment of the present invention;
Figure 10 is disclosed another switching power source control circuit structure chart of another embodiment of the present invention;
Figure 11 is disclosed another switching power source control circuit structure chart of another embodiment of the present invention;
Figure 12 is disclosed another switching power source control circuit structure chart of another embodiment of the present invention;
Figure 13 is disclosed another switching power source control circuit structure chart of another embodiment of the present invention;
Figure 14 is the circuit theory diagrams of the disclosed one-way conduction circuit of another embodiment of the present invention and oscillator;
Figure 15 is the circuit theory diagrams of disclosed another one-way conduction circuit of another embodiment of the present invention and oscillator;
Figure 16 is disclosed another switching power source control circuit structure chart of another embodiment of the present invention;
Figure 17 is disclosed another switching power source control circuit structure chart of another embodiment of the present invention;
Figure 18 is the signal waveforms of the disclosed switching power source control circuit of another embodiment of the present invention;
Figure 19 is the signal waveforms of disclosed another switching power source control circuit of another embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The invention provides a kind of Switching Power Supply control method, be used for the main power stage circuit of control switch power supply, low and can produce the problem of noise to the output voltage regulating power to solve prior art.
Concrete, as shown in Figure 1, may further comprise the steps:
S101, receive output voltage feedback signal FB and the output voltage reference signal REF of described main power stage circuit, and output voltage feedback signal FB and output voltage reference signal REF are compared and enlarged, generate and send output voltage error signal V
e
Wherein, the output voltage error signal V that generates according to output voltage feedback signal FB and output voltage reference signal REF
e, can characterize the output voltage feedback signal FB of described main power stage circuit and the relation between the output voltage reference signal REF.
S102, reception maximum output voltage error signal V
H, instantaneous peak value voltage signal V
IPK, drive signal V
qAnd output voltage error signal V
e, as output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, with output voltage error signal V
eClamper is at maximum output voltage error signal V
HAnd with output voltage error signal V
eWith instantaneous peak value voltage signal V
IPKCompare and generate comparative result, according to driving signal V
qGenerate minimum ON time signal T
On.min, and according to described comparative result and minimum ON time signal T
On.minGenerate and send the first control signal V
K1
Wherein, maximum output voltage error signal V
HOutput voltage error signal V when sign inductance peak current is the maximum induction peak current
eMagnitude of voltage; Instantaneous peak value voltage signal V
IPKCharacterize magnitude of voltage corresponding to inductance peak current; Drive signal V
qGenerated by step S104.
S103, reception minimum output voltage error signal TH and output voltage error signal V
e, with output voltage error signal V
eTH compares with the minimum output voltage error signal, and generates and sends the second control signal V according to comparative result
K2
Output voltage error signal V when wherein, minimum output voltage error signal TH sign inductance peak current is the minimum inductance peak current
eMagnitude of voltage; The second control signal V
K2Frequency depend on output voltage error signal V
eDescribed comparative result with minimum output voltage error signal TH.
S104, reception the first control signal V
K1And the second control signal V
K2, according to the first control signal V
K1And the second control signal V
K2, generate and send and drive signal V
qTo described main power stage circuit, drive described main power stage circuit and start according to different frequencies;
Concrete, the first control signal V
K1And the second control signal V
K2Frequency will determine to drive signal V
qFrequency; The driving signal V that generates
qBe used for feeding back to step S102 on the one hand, be used on the other hand driving described main power stage circuit and start according to different frequencies, realize the control to described main power stage circuit.
The disclosed Switching Power Supply control method of the present embodiment is according to the first control signal V
K1With the second control signal V
K2, generate and send and drive the driving signal V that described main power stage circuit starts according to different frequency
qEven when system was in the underloading pattern, described main power stage circuit also can be according to driving signal V
qCarry out unlatching and the shutoff of corresponding frequencies, and can not enter sleep state, and then also avoided system when the underloading pattern, the problem that the described main power stage circuit that brownout on the output capacitance causes is low to the regulating power of output voltage, and the frequency of having avoided described main power stage circuit to start can be reduced to the noise that scope that people's ear can hear produces.
Another embodiment of the present invention also provides another Switching Power Supply control method, as shown in Figure 2, may further comprise the steps:
S201, receive output voltage feedback signal FB and the output voltage reference signal REF of described main power stage circuit, and output voltage feedback signal FB and output voltage reference signal REF are compared and enlarged, generate and send output voltage error signal V
e
S202, reception maximum output voltage error signal V
H, instantaneous peak value voltage signal V
IPK, drive signal V
qAnd output voltage error signal V
e, as output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, with output voltage error signal V
eClamper is at maximum output voltage error signal V
HAnd with output voltage error signal V
eWith instantaneous peak value voltage signal V
IPKCompare and generate comparative result, according to driving signal V
qGenerate minimum ON time signal T
On.min, and according to described comparative result and minimum ON time signal T
On.minGenerate and send the first control signal V
K1As output voltage error signal V
eGreater than maximum output voltage error signal V
H, and peak voltage signal V
IPKReach maximum output voltage error signal V
HThe time, the first control signal V
K1Be effective status;
Concrete, peak voltage signal V
IPKWhen described main power circuit starts, be to rise to gradually peak value, then descended by peak value, until the switching tube in the described main power circuit turn-offs; In said process, as peak voltage signal V
IPKReach maximum output voltage error signal V
HThe time, the first control signal V
K1Be effective status.
S203, reception minimum output voltage error signal TH and output voltage error signal V
e, with output voltage error signal V
eTH compares with the minimum output voltage error signal, and generates and sends the second control signal V according to comparative result
K2As output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, the second control signal V
K2Frequency be fixed frequency f
f
Concrete, as output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, illustrate that this moment, system was in the fully loaded situation of load, the second control signal V
K2Frequency be fixed frequency f
f
S204, reception the first control signal V
K1And the second control signal V
K2, according to the first control signal V
K1And the second control signal V
K2, generate and send and drive signal V
qTo described main power stage circuit, drive described main power stage circuit and start according to different frequencies; As output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, drive signal V
qSwitching frequency and the ON time of controlling the switching tube in the described main power circuit are fixed value, and control the inductance peak current I in the described main power circuit
PkBe stabilized in maximum induction peak current I
PkH
Concrete, as output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, illustrate that this moment, system was in the fully loaded situation of load, according to the first control signal V
K1And the second control signal V
K2The driving signal V that generates
q, the switching frequency and the ON time that drive the switching tube in the described main power stage circuit are fixed value, and control the inductance peak current I in the described main power circuit
PkBe stabilized in maximum induction peak current I
PkH
Other control methods are same as the previously described embodiments in the present embodiment, repeat no more herein.
Another embodiment of the present invention also provides another Switching Power Supply control method, as shown in Figure 3, may further comprise the steps:
S301, receive output voltage feedback signal FB and the output voltage reference signal REF of described main power stage circuit, and output voltage feedback signal FB and output voltage reference signal REF are compared and enlarged, generate and send output voltage error signal V
e
S302, reception maximum output voltage error signal V
H, instantaneous peak value voltage signal V
IPK, drive signal V
qAnd output voltage error signal V
e, as output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, with output voltage error signal V
eClamper is at maximum output voltage error signal V
HAnd with output voltage error signal V
eWith instantaneous peak value voltage signal V
IPKCompare and generate comparative result, according to driving signal V
qGenerate minimum ON time signal T
On.min, and according to described comparative result and minimum ON time signal T
On.minGenerate and send the first control signal V
K1As output voltage error signal V
eLess than maximum output voltage error signal V
H, greater than minimum output voltage error signal TH, and peak voltage signal V
IPKReach output voltage error signal V
eThe time, the first control signal V
K1Be effective status;
Concrete, peak voltage signal V
IPKWhen described main power circuit starts, be to rise to gradually peak value, then descended by peak value, until the switching tube in the described main power circuit turn-offs; In said process, as peak voltage signal V
IPKReach output voltage error signal V
eThe time, the first control signal V
K1Be effective status.
S303, reception minimum output voltage error signal TH and output voltage error signal V
e, with output voltage error signal V
eTH compares with the minimum output voltage error signal, and generates and sends the second control signal V according to comparative result
K2As output voltage error signal V
eLess than maximum output voltage error signal V
HAnd during greater than minimum output voltage error signal TH, the second control signal V
K2Frequency be fixed frequency f
f
Concrete, as output voltage error signal V
eLess than maximum output voltage error signal V
HAnd during greater than minimum output voltage error signal TH, illustrate that this moment, system was in the situation of normal operation, the second control signal V
K2Frequency be fixed frequency f
f
S304, reception the first control signal V
K1And the second control signal V
K2, according to the first control signal V
K1And the second control signal V
K2, generate and send and drive signal V
qTo described main power stage circuit, drive described main power stage circuit and start according to different frequencies; As output voltage error signal V
eLess than maximum output voltage error signal V
HAnd during greater than minimum output voltage error signal TH, drive signal V
qThe switching frequency of controlling the switching tube in the described main power circuit is fixed value, but ON time is followed output voltage error signal V
eChange, and control inductance peak current I in the described main power circuit
PkFollow output voltage error signal V
eChange;
Concrete, as output voltage error signal V
eLess than maximum output voltage error signal V
HAnd during greater than minimum output voltage error signal TH, illustrate that this moment, system was in the situation of normal operation, according to the first control signal V
K1And the second control signal V
K2The driving signal V that generates
q, the switching frequency of controlling the switching tube in the described main power circuit is fixed value, but ON time is followed output voltage error signal V
eChange, and the inductance peak current of controlling in the described main power circuit is followed output voltage error signal V
eChange.
Other control methods are same as the previously described embodiments in the present embodiment, repeat no more herein.
Another embodiment of the present invention also provides another Switching Power Supply control method, as shown in Figure 4, may further comprise the steps:
S401, receive output voltage feedback signal FB and the output voltage reference signal REF of described main power stage circuit, and output voltage feedback signal FB and output voltage reference signal REF are compared and enlarged, generate and send output voltage error signal V
e
S402, reception maximum output voltage error signal V
H, instantaneous peak value voltage signal V
IPK, drive signal V
qAnd output voltage error signal V
e, as output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, with output voltage error signal V
eClamper is at maximum output voltage error signal V
HAnd with output voltage error signal V
eWith instantaneous peak value voltage signal V
IPKCompare and generate comparative result, according to driving signal V
qGenerate minimum ON time signal T
On.min, and according to described comparative result and minimum ON time signal T
On.minGenerate and send the first control signal V
K1As output voltage error signal V
eLess than minimum output voltage error signal TH, and the ON time of described switching tube reaches minimum ON time T
On.minThe time, the first control signal V
K1Be effective status;
Concrete, peak voltage signal V
IPKWhen described main power circuit starts, be to rise to gradually peak value, then descended by peak value, until the switching tube in the described main power circuit turn-offs; In said process, when the ON time of described switching tube reaches minimum ON time T
On.minThe time, the first control signal V
K1Be effective status.
S403, reception minimum output voltage error signal TH and output voltage error signal V
e, with output voltage error signal V
eTH compares with the minimum output voltage error signal, and generates and sends the second control signal V according to comparative result
K2As output voltage error signal V
eDuring less than minimum output voltage error signal TH, the second control signal V
K2Frequency f
vFollow output voltage error signal V
eChange;
Concrete, as output voltage error signal V
eDuring less than minimum output voltage error signal TH, illustrate that this moment, system was in the situation of underloading pattern, the second control signal V
K2Frequency f
vFollow output voltage error signal V
eChange.
S404, reception the first control signal V
K1And the second control signal V
K2, according to the first control signal V
K1And the second control signal V
K2, generate and send and drive signal V
qTo described main power stage circuit, drive described main power stage circuit and start according to different frequencies; As output voltage error signal V
eDuring less than minimum output voltage error signal TH, drive signal V
qThe ON time of controlling the switching tube in the described main power circuit is fixed value, but switching frequency is followed output voltage error signal V
eChange, and control inductance peak current I in the described main power circuit
PkBe stabilized in minimum inductance peak current I
PkL
Concrete, as output voltage error signal V
eDuring less than minimum output voltage error signal TH, illustrate that this moment, system was in the situation of underloading pattern, according to the first control signal V
K1And the second control signal V
K2The driving signal V that generates
q, control the switching frequency of the switching tube in the described main power circuit and follow output voltage error signal V
eChange, the ON time of the switching tube in the described main power circuit is fixed value, and controls the inductance peak current I in the described main power circuit
PkBe stabilized in minimum inductance peak current I
PkL
Other control methods are same as the previously described embodiments in the present embodiment, repeat no more herein.
Preferably, another embodiment of the present invention also provides another Switching Power Supply control method, as output voltage error signal V
eDuring less than certain value TS, control described main power circuit and enter sleep pattern.
Other control methods are same as the previously described embodiments in the present embodiment, repeat no more herein.
Another embodiment of the present invention also provides another Switching Power Supply control method, as shown in Figure 5, may further comprise the steps:
S501, receive output voltage feedback signal FB and the output voltage reference signal REF of described main power stage circuit, and output voltage feedback signal FB and output voltage reference signal REF are compared and enlarged, generate and send output voltage error signal V
e
S502, reception maximum output voltage error signal V
H, instantaneous peak value voltage signal V
IPK, drive signal V
qAnd output voltage error signal V
e, as output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, with output voltage error signal V
eClamper is at maximum output voltage error signal V
HAnd with output voltage error signal V
eWith instantaneous peak value voltage signal V
IPKCompare and generate comparative result, according to driving signal V
qGenerate minimum ON time signal T
On.min, and according to described comparative result and minimum ON time signal T
On.minGenerate and send the first control signal V
K1As output voltage error signal V
eGreater than maximum output voltage error signal V
H, and peak voltage signal V
IPKReach maximum output voltage error signal V
HThe time, perhaps as output voltage error signal V
eLess than maximum output voltage error signal V
HAnd greater than minimum output voltage error signal TH, and peak voltage signal V
IPKReach output voltage error signal V
eThe time, or as output voltage error signal V
eLess than minimum output voltage error signal TH, and the ON time of described switching tube reaches minimum ON time T
On.minThe time, the first control signal V
K1Be effective status;
S503, reception minimum output voltage error signal TH and output voltage error signal V
e, with output voltage error signal V
eTH compares with the minimum output voltage error signal, and generates and sends the second control signal V according to comparative result
K2As output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, perhaps as output voltage error signal V
eLess than maximum output voltage error signal V
HAnd during greater than minimum output voltage error signal TH, the second control signal V
K2Frequency be fixed frequency f
fAs output voltage error signal V
eDuring less than minimum output voltage error signal TH, the second control signal V
K2Frequency f
vFollow output voltage error signal V
eChange;
S504, reception the first control signal V
K1And the second control signal V
K2, according to the first control signal V
K1And the second control signal V
K2, generate and send and drive signal V
qTo described main power stage circuit, drive described main power stage circuit and start according to different frequencies; As output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, drive signal V
qSwitching frequency and the ON time of controlling the switching tube in the described main power circuit are fixed value, and control the inductance peak current I in the described main power circuit
PkBe stabilized in maximum induction peak current I
PkHAs output voltage error signal V
eLess than maximum output voltage error signal V
HAnd during greater than minimum output voltage error signal TH, drive signal V
qThe switching frequency of controlling the switching tube in the described main power circuit is fixed value, but ON time is followed output voltage error signal V
eChange, and control inductance peak current I in the described main power circuit
PkFollow output voltage error signal V
eChange; As output voltage error signal V
eDuring less than minimum output voltage error signal TH, drive signal V
qThe ON time of controlling the switching tube in the described main power circuit is fixed value, but switching frequency is followed output voltage error signal V
eChange, and control inductance peak current I in the described main power circuit
PkBe stabilized in minimum inductance peak current I
PkLAs output voltage error signal V
eDuring less than certain value TS, control described main power circuit and enter sleep pattern.
Figure 6 shows that the graph of a relation between each signal in the said process.
Other control methods are same as the previously described embodiments in the present embodiment, repeat no more herein.
Another embodiment of the present invention also provides another switching power source control circuit, and shown in Fig. 7 dotted line frame, the described switching power source control circuit that links to each other with main power stage circuit 101 comprises:
Error signal generation circuit 102, an input of error signal generation circuit 102 link to each other with main power stage circuit 101 outputs as the input of described switching power source control circuit;
Peak current control circuit 103, the input of peak current control circuit 103 links to each other with error signal generation circuit 102 outputs;
Drive signal generation circuit 105, the first input end of drive signal generation circuit 105 links to each other with peak current control circuit 103 outputs, the second input links to each other with frequency control circuit 104 outputs, and the output of drive signal generation circuit 105 is the output of described switching power source control circuit.
Concrete operation principle is:
Error signal generation circuit 102 receives output voltage feedback signal FB and the output voltage reference signal REF of main power stage circuit 101, output voltage feedback signal FB and output voltage reference signal REF are compared and enlarged, generate and send output voltage error signal V
e
Peak current control circuit 103 receives output voltage error signal V
e, maximum output voltage error signal V
H, instantaneous peak value voltage signal V
IPKAnd driving signal V
q, wherein, instantaneous peak value voltage signal V
IPKCharacterize the instantaneous inductor current peak in the main power stage circuit 101, as output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, with output voltage error signal V
eClamper is at maximum output voltage error signal V
HAnd with output voltage error signal V
eWith instantaneous peak value voltage signal V
IPKCompare the generation comparative result, according to driving signal V
qGenerate minimum switching tube ON time signal T
On.min, and according to described comparative result and minimum switching tube ON time signal T
On.minGenerate and send the first control signal V
K1
Drive signal generation circuit 105 receives described the first control signal V
K1With the second control signal V
K2, according to described the first control signal V
K1And the second control signal V
K2, generate and send and drive signal V
qTo peak current control circuit 103 and main power stage circuit 101, control main power stage circuit 101 and start according to different frequencies.
The disclosed switching power source control circuit of the present embodiment, by drive signal generation circuit 105 according to described the first control signal V
K1With the second control signal V
K2, generate and send and drive the driving signal V that main power stage circuit 101 starts according to different frequency
qWhen even system is in the underloading pattern, main power stage circuit 101 also can carry out unlatching and the shutoff of corresponding frequencies according to the driving signal of drive signal generation circuit output, and can not enter sleep state, and then also avoided system when the underloading pattern, the low problem of regulating power of 101 pairs of output voltages of main power stage circuit that the brownout on the output capacitance causes, and the frequency of having avoided system master's power stage circuit 101 to start can be reduced to the noise that scope that people's ear can hear produces.
Another embodiment of the present invention also provides another switching power source control circuit, shown in Fig. 8 dotted line frame, the described switching power source control circuit that links to each other with main power stage circuit 101 comprises: error signal generation circuit 102, peak current control circuit 103, frequency control circuit 104 and drive signal generation circuit 105.
With above-described embodiment difference be:
Error signal generation circuit 102 comprises:
Error amplifier, the inverting input of described error amplifier is as error signal generation circuit 102 inputs; The output of described error amplifier is the output of error signal generation circuit 102.
The in-phase input end of described error amplifier receives output voltage reference signal REF, inverting input receives output voltage feedback signal FB, output voltage feedback signal FB and output voltage reference signal REF are compared and enlarged, by error signal generation circuit 102 output output voltage error signal V
e
In concrete practical application, the way of realization of error signal generation circuit 102 is not limited to foregoing description, also can be the voltage error operational amplifier with compensate function, perhaps other the when circuit that can realize that error amplifies.
The concrete connected mode of other circuit modules and operation principle are identical with embodiment among Fig. 7 in the present embodiment, repeat no more herein.
Another embodiment of the present invention also provides another switching power source control circuit, shown in Fig. 9 dotted line frame, the described switching power source control circuit that links to each other with main power stage circuit 101 comprises: error signal generation circuit 102, peak current control circuit 103, frequency control circuit 104 and drive signal generation circuit 105.
With the embodiment difference among Fig. 7 be:
Peak current control circuit 103 comprises:
The first comparator A1, the inverting input of the first comparator A1 receive output voltage error signal V as peak current control circuit 103 inputs
e, the in-phase input end of the first comparator A1 receives instantaneous peak value voltage signal V
IPK
Time signal produces circuit 1032, and the input that time signal produces circuit 1032 receives driving signal V
q, time signal produces the output of circuit 1032 and exports minimum ON time signal T
On.min
With door, describedly link to each other with the output of the first comparator A1 and time signal generating circuit 1032 respectively with the input of door, described output with door is the output of peak current control circuit 103.
Concrete operation principle is:
Since the high clamping action of high clamp circuit 1031, the output voltage error signal V that the first comparator A1 inverting input receives
eCan be greater than the maximum output voltage error signal V of high clamp circuit 1031 receptions
HAs output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, with output voltage error signal V
eClamper is at maximum output voltage error signal V
HThe output voltage error signal V that the first comparator A1 receives inverting input
eInstantaneous peak value voltage signal V with the in-phase input end reception
IPKCompare and generate comparative result V
b, time signal produces circuit 1032 according to the driving signal V that receives
qGenerate and export minimum ON time signal T
On.minThen comparative result Vb and minimum ON time signal T
On.minInput to described with behind the door, generate described the first control signal V
K1As output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, and the peak voltage signal V of the first comparator A1 reception
IPKReach maximum output voltage error signal V
HThe time, described the first control signal V that becomes with the pupil
K1Be effective status; As output voltage error signal V
eLess than maximum output voltage error signal V
HAnd greater than minimum output voltage error signal TH, and the peak voltage signal V of the first comparator A1 reception
IPKReach output voltage error signal V
eThe time, described the first control signal V that becomes with the pupil
K1Be effective status; As output voltage error signal V
eDuring less than minimum output voltage error signal TH, and time signal produces the minimum ON time signal T that circuit 1032 generates
On.minDuring for high level, described the first control signal V that becomes with the pupil
K1Be effective status.
The concrete connected mode of other circuit modules and operation principle are identical with embodiment among Fig. 7 in the present embodiment, repeat no more herein.
Preferably, in another embodiment, as shown in figure 10, high clamp circuit 1031 is the first diode D1; The positive pole of the first diode D1 links to each other with the first comparator A1 inverting input; The negative pole of the first diode D1 receives maximum output voltage error signal V
H
The concrete connected mode of other circuit modules and operation principle are identical with embodiment among Fig. 7 in the present embodiment, repeat no more herein.
Preferably, in another embodiment, as shown in figure 11, high clamp circuit 1031 comprises: mirror current source and voltage follower;
One end of described mirror current source links to each other with the first comparator A1 inverting input, receives output voltage error signal V
eThe other end of described mirror current source links to each other with the output of described voltage follower;
The in-phase input end of described voltage follower receives maximum output voltage error signal V
H
In concrete practical application, high clamp circuit 1031 does not limit the way of realization of above-mentioned two embodiment, and the personnel in the art as can be known specific implementation form of high clamp circuit 1031 can also be made of other suitable circuit according to concrete applied environment.
The concrete connected mode of other circuit modules and operation principle are identical with embodiment among Fig. 7 in the present embodiment, repeat no more herein.
Preferably, in another embodiment, as shown in figure 12, time signal produces circuit 1032 and comprises:
Push-pull circuit, described push-pull circuit are connected between the current source of power supply and ground connection, and the input of described push-pull circuit receives and drives signal V
q
Capacitor C, an end of capacitor C links to each other with the output of described push-pull circuit, the other end ground connection of capacitor C;
Schmidt trigger, the input of described Schmidt trigger links to each other with the output of described push-pull circuit, and the output of described Schmidt trigger is exported minimum ON time signal T
On.min
Concrete connected mode and the operation principle of other components and parts are same as the previously described embodiments in the present embodiment, repeat no more herein.
Another embodiment of the present invention also provides another switching power source control circuit, shown in Figure 13 dotted line frame, the described switching power source control circuit that links to each other with main power stage circuit 101 comprises: error signal generation circuit 102, peak current control circuit 103, frequency control circuit 104 and drive signal generation circuit 105.
With above-described embodiment difference be:
Operational transconductance amplifier GM, the inverting input of operational transconductance amplifier GM receive output voltage error signal V as frequency control circuit 104 inputs
e, the in-phase input end of operational transconductance amplifier GM receives minimum output voltage error signal TH;
One-way conduction circuit 1041, the input of one-way conduction circuit 1041 links to each other with operational transconductance amplifier GM output;
Concrete operation principle is:
Operational transconductance amplifier GM is with the minimum output voltage error signal TH of in-phase input end reception and the output voltage error signal V of inverting input reception
eCompare, according to the comparative result of the output of operational transconductance amplifier GM, one-way conduction circuit 1041 determines whether conducting, when the state of one-way conduction circuit 1041 is conducting, receive described comparative result, and generate and send frequency according to described comparative result and follow output voltage error signal V
eThe the second control signal V that changes
K2When one-way conduction circuit 1041 not conducting, the second control signal V that generates and sends
K2Frequency be the natural frequency f of oscillator 1042 inside
f
In concrete actual application environment, the way of realization of the internal structure of oscillator 1042 and one-way conduction circuit 1041 cooperatively interacts and selects, such as Figure 14 and shown in Figure 15.
Concrete connected mode and the operation principle of other components and parts are same as the previously described embodiments in the present embodiment, repeat no more herein.
Another embodiment of the present invention also provides another switching power source control circuit, shown in Figure 16 dotted line frame, the described switching power source control circuit that links to each other with main power stage circuit 101 comprises: error signal generation circuit 102, peak current control circuit 103, frequency control circuit 104 and drive signal generation circuit 105.
With the embodiment difference among Fig. 7 be:
Drive signal generation circuit 105 is: rest-set flip-flop;
The reset terminal R of described rest-set flip-flop is the first input end of drive signal generation circuit 105;
The set end S of described rest-set flip-flop is the second input of drive signal generation circuit 105;
The output Q of described rest-set flip-flop is the output of drive signal generation circuit 105.
Concrete operation principle is:
The first control signal V that described rest-set flip-flop receives according to reset terminal R
K1The second control signal V with set end S reception
K2Generate and send and drive signal V
qTo peak current control circuit 103 and main power stage circuit 101, drive main power stage circuit 101 and start according to different frequencies and turn-off.
As output voltage error signal V
eGreater than maximum output voltage error signal V
HThe time, switching frequency and ON time that described rest-set flip-flop is controlled the switching tube in the described main power circuit are fixed value, and control the inductance peak current I in the described main power circuit
PkBe stabilized in maximum induction peak current I
PkH
As output voltage error signal V
eLess than maximum output voltage error signal V
HAnd during greater than minimum output voltage error signal TH, the switching frequency that described rest-set flip-flop is controlled the switching tube in the described main power circuit is fixed value, but ON time is followed output voltage error signal V
eChange, and the inductance peak current Ipk that controls in the described main power circuit follows output voltage error signal V
eChange.
As output voltage error signal V
eDuring less than minimum output voltage error signal TH, the ON time that described rest-set flip-flop is controlled the switching tube in the described main power circuit is fixed value, but switching frequency is followed output voltage error signal V
eChange, and the inductance peak current Ipk that controls in the described main power circuit is stabilized in minimum inductance peak current I
PkL
As output voltage error signal V
eDuring less than certain value TS, described rest-set flip-flop is controlled described main power circuit and is entered sleep pattern.
In concrete actual application environment, drive signal generation circuit 105 is not defined as rest-set flip-flop, also can adopt various logic gates to interconnect to realize the function identical with described rest-set flip-flop according to actual needs, also may further include the driving intensifier circuit.
The concrete connected mode of other circuit modules and operation principle are identical with embodiment among Fig. 7 in the present embodiment, repeat no more herein.
Another embodiment of the present invention also provides another switching power source control circuit, shown in Figure 17 dotted line frame, the described switching power source control circuit that links to each other with main power stage circuit 101 comprises: error signal generation circuit 102, peak current control circuit 103, frequency control circuit 104 and drive signal generation circuit 105.
And error signal generation circuit 102 comprises:
Error amplifier, the inverting input of described error amplifier is as error signal generation circuit 102 inputs; The output of described error amplifier is the output of error signal generation circuit 102.
Peak current control circuit 103 comprises:
The first comparator A1, the inverting input of the first comparator A1 receive output voltage error signal V as peak current control circuit 103 inputs
e, the in-phase input end of the first comparator A1 receives instantaneous peak value voltage signal V
IPK
Time signal produces circuit 1032, and the input that time signal produces circuit 1032 receives driving signal V
q, time signal produces the output of circuit 1032 and exports minimum ON time signal T
On.min
With door, describedly link to each other with the output of the first comparator A1 and time signal generating circuit 1032 respectively with the input of door, described output with door is the output of peak current control circuit 103.
Operational transconductance amplifier GM, the inverting input of operational transconductance amplifier GM receive output voltage error signal V as frequency control circuit 104 inputs
e, the in-phase input end of operational transconductance amplifier GM receives minimum output voltage error signal TH;
One-way conduction circuit 1041, the input of one-way conduction circuit 1041 links to each other with operational transconductance amplifier GM output;
One-way conduction circuit 1041 describes Figure 8 shows that example with oscillator 1042.
Drive signal generation circuit 105 is: rest-set flip-flop;
The reset terminal R of described rest-set flip-flop is the first input end of drive signal generation circuit 105;
The set end S of described rest-set flip-flop is the second input of drive signal generation circuit 105;
The output Q of described rest-set flip-flop is the output of drive signal generation circuit 105.
Preferably, high clamp circuit 1031 is the first diode D1; The positive pole of the first diode D1 links to each other with the first comparator A1 inverting input; The negative pole of the first diode D1 receives maximum output voltage error signal V
H
Preferably, time signal generation circuit 1032 comprises:
Push-pull circuit, described push-pull circuit are connected between the current source of power supply and ground connection, and the input of described push-pull circuit receives and drives signal V
q
Capacitor C, an end of capacitor C links to each other with the output of described push-pull circuit, the other end ground connection of capacitor C;
Schmidt trigger, the input of described Schmidt trigger links to each other with the output of described push-pull circuit, and the output of described Schmidt trigger is exported minimum ON time signal T
On.min
Below in conjunction with Figure 18 and signal waveforms shown in Figure 19 and signal relation figure shown in Figure 6, concrete operation principle is described in detail:
(1) as output voltage error signal V
eBe higher than maximum output voltage error signal V
HThe time, also be system when being in the fully loaded situation of load, since the high clamping action of the first diode D1, the output voltage error signal V that the first comparator A1 inverting input receives
eEqual the maximum output voltage error signal V that the first diode D1 negative pole receives
HThe maximum output voltage error signal V that the first comparator A1 receives inverting input
HInstantaneous peak value voltage signal V with the in-phase input end reception
IPKCompare, wherein, instantaneous peak value voltage signal V
IPKCharacterize the instantaneous inductor current peak of main power stage circuit, can be obtained by prior art, do not repeat them here, and maximum output voltage error signal V
HCan be that the required maximum induction peak current IpkH of full load sets according to load; At this moment, the comparative result V of the first comparator A1 output
bBe low level; Therefore, no matter time signal produces the minimum ON time signal T that circuit 1032 produces
On.minWhether be high level, comparative result V
bWith minimum ON time signal T
On.minThrough described with behind the door, the described first control signal V of generation
K1Be low level.
The output voltage error signal V that this moment, operational transconductance amplifier GM inverting input received
eMinimum output voltage error signal TH greater than the in-phase input end reception, operational transconductance amplifier GM will extract electric current from the outside, but because the one-way conduction characteristic of one-way conduction circuit 1041, operational transconductance amplifier GM can not extract electric current, therefore, oscillator 1042 is not subjected to the impact of operational transconductance amplifier GM, and the frequency of the described second control signal Vk2 of its output is the fixed value f of internal preset
f, wherein, fixed value f
fCan set by capacitance in the oscillator 1042 and the value of current source are set.
The reset terminal R of described rest-set flip-flop receives the first control signal V
K1, set end S receives the second control signal V
K2As the second control signal V
K2During for high level, the driving signal V of the output Q of rest-set flip-flop output
qBe high level, control the switching tube conducting in the main power stage circuit 101, the inductance peak current Ipk in the main power stage circuit 101 continues to rise; Until inductance peak current Ipk when arriving maximum induction peak current IpkH, namely characterizes the instantaneous peak value voltage signal V of inductance peak current Ipk
IPKArrive maximum output voltage error signal V
HThe time, the comparative result V of the first comparator A1 output
bUpset, saltus step is high level; And this moment, owing to drive signal V
qRemain high level always, through after the minimum ON time, minimum ON time signal T
On.minSaltus step is high level; Therefore, comparative result Vb and minimum ON time signal T
On.minGenerate afterwards the first control signal V through described with door
K1Be high level also, the described rest-set flip-flop that resets, the driving signal V of the output Q output of rest-set flip-flop
qThe switching tube of controlling in the main power stage circuit 101 turn-offs; So system is in the situation that load is fully loaded, by described switching power source control circuit, according to the fixed frequency f of oscillator 1042 internal preset
fOpen the switching tube in the main power stage circuit 101, and when the value of inductance peak current Ipk reaches maximum induction peak current IpkH, i.e. instantaneous peak value voltage signal V
IPKArrive maximum output voltage error signal V
HThe time, turn-off the switching tube in the main power stage circuit 101.Circulate with this, guarantee that the value of inductance peak current Ipk is basicly stable at maximum induction peak current IpkH.
(2) as output voltage error signal V
eBe lower than maximum output voltage error signal V
H, when but being higher than minimum output voltage error signal TH, also be system when being in the situation of normal operation, the first diode D1 is to output voltage error signal V
eDo not play clamping action; Therefore, because the course of work and the above-mentioned situation of each components and parts are similar, as can be known, described switching power source control circuit is according to the fixed frequency f of oscillator 1042 internal preset
fOpen the switching tube in the main power stage circuit 101, as instantaneous peak value voltage signal V
IPKArrive output voltage error signal V
eThe time, turn-off the switching tube in the main power stage circuit 101.Circulate with this, realize that inductance peak current Ipk follows output voltage error signal V substantially
eChange.
(3) being signal waveforms in the underloading situation with reference to load shown in Figure 13, when output voltage error signal Ve is lower than minimum output voltage error signal TH, also is system when being in the underloading pattern, and same, the first diode D1 is to output voltage error signal V
eDo not play clamping action.As the second control signal V
K2During for high level, the switching tube in the main power stage circuit 101 is opened instantaneous peak value voltage signal V
IPKContinue to rise, as instantaneous peak value voltage signal V
IPKRise to output voltage error signal V
eThe time, the comparative result V of the first comparator A1 output
bSaltus step is high level; Because this moment, the ON time of switching tube did not also arrive minimum switching tube ON time T
On.min, instantaneous peak value voltage signal V
IPKContinue to rise until the ON time of switching tube is minimum switching tube ON time T
On.min, time signal T saltus step is high level, at this moment, and instantaneous peak value voltage signal V
IPKRise to minimum peak voltage signal V
IPKLTherefore, comparative result V
bWith time signal T process and the first control signal V that exports behind the door
K1Also saltus step is high level, controls the driving signal V of described rest-set flip-flop output
qBe low level, the switching tube of controlling in the main power stage circuit 101 turn-offs minimum voltage peak value V
IPKLBegin to descend until zero; As the second control signal V
K2When again being high level, repeat said process, guarantee that with this inductance peak current Ipk is basicly stable at minimum inductance peak current IpkL.
At this moment, the output voltage error signal V of operational transconductance amplifier GM inverting input reception
eMinimum output voltage error signal TH less than the in-phase input end reception, the outside output current of operational transconductance amplifier GM, through one-way conduction circuit 1041, so that the capacitor discharge speed in the oscillator 1042 slows down, so the second control signal V of oscillator 1042 outputs
K2Frequency reduce, and along with output voltage error signal V
eReduce and reduce;
This shows, the operating frequency of controlling the switching tube in the main power stage circuit 101 will opening and shutting off with lower frequency, and can not enter sleep state, and then also avoided system when the underloading pattern, the low problem of regulating power of 101 pairs of output voltages of main power stage circuit that the brownout on the output capacitance causes, and the frequency of having avoided system master's power stage circuit 101 to start can be reduced to the noise that scope that people's ear can hear produces.Simultaneously, can also guarantee that inductance peak current Ipk is basicly stable at minimum inductance peak current IpkL.
(4) as output voltage error signal V
eWhen continuing to be reduced to certain value, system just can enter sleep state.
Another embodiment of the present invention also provides another Switching Power Supply, comprises the described switching power source control circuit among main power stage circuit 101 and any one Fig. 7 to Figure 17.Described main power stage circuit 101 can for adopting the topological structure of peak current control program, comprise buck, boost, buck-boost etc.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can be in the situation that do not break away from the spirit or scope of the present invention, in other embodiments realization.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (14)
1. Switching Power Supply control method is used for the main power stage circuit of control switch power supply, it is characterized in that, may further comprise the steps:
Receive output voltage feedback signal and the output voltage reference signal of described main power stage circuit, and described output voltage feedback signal and described output voltage reference signal are compared and enlarged, generate and send the output voltage error signal;
Receive maximum output voltage error signal, instantaneous peak value voltage signal, drive signal and described output voltage error signal, when described output voltage error signal during greater than described maximum output voltage error signal, with described output voltage error signal clamper in described maximum output voltage error signal; And described output voltage error signal and instantaneous peak value voltage signal compared and generate comparative result, generate minimum ON time signal according to described driving signal, and generate and send the first control signal according to described comparative result and described minimum ON time signal;
Receive minimum output voltage error signal and described output voltage error signal, described output voltage error signal and minimum output voltage error signal are compared, and generate and send the second control signal according to comparative result;
Receive described the first control signal and the second control signal, according to described the first control signal and the second control signal, generate and send described driving signal to described main power stage circuit, drive described main power stage circuit and start according to different frequencies.
2. Switching Power Supply control method according to claim 1 is characterized in that, when described output voltage error signal during greater than the maximum output voltage error signal, with described output voltage error signal clamper in described maximum output voltage error signal; Making described the first control signal is effective status when described instantaneous peak value voltage signal reaches described maximum output voltage error signal, and the frequency of described the second control signal is fixed frequency; Take the switching frequency of controlling the switching tube in the described main power circuit and ON time as fixed value, and the inductance peak current of controlling in the described main power circuit is stabilized in the maximum induction peak current.
3. Switching Power Supply control method according to claim 1, it is characterized in that, when described output voltage error signal during less than described maximum output voltage error signal and greater than described minimum output voltage error signal, making described the first control signal is effective status when described peak voltage signal reaches described output voltage error signal, and the frequency of described the second control signal is fixed frequency; Take the switching frequency of controlling the switching tube in the described main power circuit as fixed value, but ON time is followed described output voltage error signal intensity, and the inductance peak current of controlling in the described main power circuit is followed described output voltage error signal intensity.
4. Switching Power Supply control method according to claim 1, it is characterized in that, when described output voltage error signal during less than described minimum output voltage error signal, making described the first control signal is effective status when the ON time of described switching tube reaches described minimum ON time, and the frequency of described the second control signal is followed described output voltage error signal intensity; Take the ON time of controlling the switching tube in the described main power circuit as fixed value, but switching frequency is followed described output voltage error signal intensity, and the inductance peak current of controlling in the described main power circuit is stabilized in the minimum inductance peak current.
5. Switching Power Supply control method according to claim 1 is characterized in that, when described output voltage error signal during less than certain value, controls described main power circuit and enters sleep pattern.
6. a switching power source control circuit links to each other with Switching Power Supply master power stage circuit, it is characterized in that, described switching power source control circuit comprises:
Error signal generation circuit, an input of described error signal generation circuit receive output voltage feedback signal as the input of described switching power source control circuit, link to each other with described main power stage circuit output; Described error signal generation circuit also receives the output voltage reference signal, and described output voltage feedback signal and described output voltage reference signal are compared and enlarged, and generates and sends the output voltage error signal;
The peak current control circuit, the input of described peak current control circuit links to each other with described error signal generation circuit output, receives described output voltage error signal; Described peak current control circuit also receives maximum output voltage error signal, instantaneous peak value voltage signal and drives signal, when described output voltage error signal during greater than described maximum output voltage error signal, with described output voltage error signal clamper in described maximum output voltage error signal; And described output voltage error signal and instantaneous peak value voltage signal compared and generate comparative result, generate minimum ON time signal according to described driving signal, and generate and send the first control signal according to described comparative result and described minimum ON time signal;
Frequency control circuit, the input of described frequency control circuit links to each other with described error signal generation circuit output, receives described output voltage error signal; Described frequency control circuit also receives the minimum output voltage error signal, described output voltage error signal and minimum output voltage error signal is compared, and generate and send the second control signal according to comparative result;
Drive signal generation circuit, the first input end of described drive signal generation circuit links to each other with described peak current control circuit output, receives described the first control signal; The second output of described drive signal generation circuit links to each other with described frequency control circuit output, receives described the second control signal; Described drive signal generation circuit is according to described the first control signal and the second control signal, generate and send and drive signal to described peak current control circuit and described main power stage circuit, drive described main power stage circuit and start according to different frequencies, the output of described drive signal generation circuit is the output of described switching power source control circuit.
7. switching power source control circuit according to claim 6 is characterized in that, described error signal generation circuit comprises:
Error amplifier, the inverting input of described error amplifier receives described output voltage feedback signal as described error signal generation circuit input; The in-phase input end of described error amplifier receives the output voltage reference signal; The output of described error amplifier is the output of described error signal generation circuit, produces described output voltage error signal.
8. switching power source control circuit according to claim 6 is characterized in that, described peak current control circuit comprises:
The first comparator, the inverting input of described the first comparator receives described output voltage error signal as described peak current control circuit input, and the in-phase input end of described the first comparator receives described instantaneous peak value voltage signal;
High clamp circuit, an end of described high clamp circuit links to each other with described the first comparator inverting input, receives described output voltage error signal, and the other end of described high clamp circuit receives described maximum output voltage error signal; When described output voltage error signal during greater than described maximum output voltage error signal, with described output voltage error signal clamper in described maximum output voltage error signal;
Time signal produces circuit, and the input that described time signal produces circuit receives described driving signal, and described time signal produces the output of circuit and exports described minimum ON time signal;
With door, the input of described and door links to each other with the output that described the first comparator and described time signal produce circuit respectively, described with output be the output of described peak current control circuit, generate described the first control signal; When described output voltage error signal greater than the maximum output voltage error signal, and the described peak voltage signal that receives of described the first comparator is when reaching described maximum output voltage error signal, described described the first control signal that becomes with the pupil is effective status; When described output voltage error signal less than the maximum output voltage error signal and greater than the minimum output voltage error signal, and when the described peak voltage signal that described the first comparator receives reached described output voltage error signal, described described the first control signal that becomes with the pupil was effective status; When described output voltage error signal less than the minimum output voltage error signal, and the described time signal minimum ON time that produces circuit evolving is when being high level, described described the first control signal that becomes with the pupil is effective status.
9. switching power source control circuit according to claim 8 is characterized in that, described high clamp circuit is the first diode; The positive pole of described the first diode links to each other with described the first comparator inverting input, receives described output voltage error signal; The negative pole of described the first diode receives described maximum output voltage error signal.
10. switching power source control circuit according to claim 8 is characterized in that, described high clamp circuit comprises: mirror current source and voltage follower;
One end of described mirror current source links to each other with described the first comparator inverting input, receives described output voltage error signal; The other end of described mirror current source links to each other with the output of described voltage follower;
The in-phase input end of described voltage follower receives described maximum output voltage error signal.
11. switching power source control circuit according to claim 8 is characterized in that, described time signal produces circuit and comprises:
Push-pull circuit, described push-pull circuit are connected between the current source of power supply and ground connection, and the input of described push-pull circuit receives described driving signal;
Electric capacity, an end of described electric capacity links to each other with the output of described push-pull circuit, the other end ground connection of described electric capacity;
Schmidt trigger, the input of described Schmidt trigger links to each other with the output of described push-pull circuit, and the output of described Schmidt trigger is exported described minimum ON time signal.
12. switching power source control circuit according to claim 6 is characterized in that, described frequency control circuit comprises:
Operational transconductance amplifier, the inverting input of described operational transconductance amplifier receive described output voltage error signal as described frequency control circuit input, and the in-phase input end of described operational transconductance amplifier receives described minimum output voltage error signal; Described output voltage error signal and minimum output voltage error signal are compared, and the output comparative result;
One-way conduction circuit, the input of described one-way conduction circuit links to each other with described operational transconductance amplifier output, described one-way conduction circuit determines whether conducting according to the described comparative result that receives, and when described one-way conduction circuit conducting, described comparative result is transmitted;
Oscillator, the input of described oscillator links to each other with the output of described one-way conduction circuit, when described one-way conduction circuit conducting, receive described comparative result, and generate and send the second control signal that frequency is followed described output voltage error signal intensity according to described comparative result; When described not conducting of one-way conduction circuit, the frequency of described the second control signal that generates and sends is the natural frequency of described oscillator inside; The output of described oscillator is the output of described frequency control circuit.
13. switching power source control circuit according to claim 6 is characterized in that, described drive signal generation circuit comprises: rest-set flip-flop;
The reset terminal R of described rest-set flip-flop is the first input end of described drive signal generation circuit;
The set end S of described rest-set flip-flop is the second input of described drive signal generation circuit;
The output Q of described rest-set flip-flop is the output of described drive signal generation circuit;
When described output voltage error signal during greater than the maximum output voltage error signal, switching frequency and ON time that described rest-set flip-flop is controlled the switching tube in the described main power circuit are fixed value, and the inductance peak current of controlling in the described main power circuit is stabilized in the maximum induction peak current;
When described output voltage error signal during less than the maximum output voltage error signal and greater than the minimum output voltage error signal, the switching frequency that described rest-set flip-flop is controlled the switching tube in the described main power circuit is fixed value, but ON time is followed described output voltage error signal intensity, and the inductance peak current of controlling in the described main power circuit is followed described output voltage error signal intensity;
When described output voltage error signal during less than the minimum output voltage error signal, the ON time that described rest-set flip-flop is controlled the switching tube in the described main power circuit is fixed value, but switching frequency is followed described output voltage error signal intensity, and the inductance peak current of controlling in the described main power circuit is stabilized in the minimum inductance peak current;
When described output voltage error signal during less than certain value, described rest-set flip-flop is controlled described main power circuit and is entered sleep pattern.
14. a Switching Power Supply is characterized in that, comprises the described switching power source control circuit of any one among main power stage circuit and the claim 6-13.
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