CN103365624A - Judgment system and method - Google Patents

Abstract

Judgment system and method. The system uses a common adder circuit to execute one of a horizontal minimum instruction and an error absolute value sum instruction, and includes multiple adders, a summing circuit, a comparison circuit and a path selection circuit. The path selection circuit transmits multiple digital codes to the adder according to the executed instruction. When executing the horizontal minimum instruction, these adders are classified into many adder pairs. Each adder pair provides a carry output and a transfer output. Each adder pair has a high adder and a low adder. The high adder compares the high part of a digital code pair of these digital codes. The low adder compares the low part of the digital code pair of these digital codes. According to these carry outputs and these transfer outputs, the minimum digital code is found.

Description

Judgment system and method

This application is a divisional application of an invention patent application with an application date of September 07, 2010, an application number of 201010277155.1, and an invention title of "judgment system and method".

technical field

The present invention relates to a microprocessor instruction, in particular to a system and method for judging the minimum code from a set of digital values, wherein the smallest digital code is used as a horizontal minimum value (horizontal minimum ).

Background technique

The current microprocessor (microprocessor) is often used to execute media instructions (MediaInstruction) to increase the efficiency of multimedia applications. For example, the microprocessor architecture may include one or more media instructions to identify a horizontal minimum value from a set of digital codes, and the horizontal minimum value in a bus (bus) or a register (register) Corresponding location. A specific example is the PHMINPOSUW instruction in Intel's SSE4 programming reference manual (SSE4programmingreference manual). The PHMINPOSUW instruction finds the minimum word and the corresponding position of the minimum word from 8 unsigned words (128 bits), wherein the minimum word has 16 bits. Certain known microprocessors require more processing procedures or more clock cycles when executing the PHMINPOSUW instruction. For example, in order to identify the smallest word pair among multiple word pairs, four 16-bit size comparators (magnitude comparators) are required to reduce the search range from 8 words to 4 words in a first cycle. words, and then feed back the found 4 words to 2 comparators to reduce the search range from 4 words to 2 words in a second cycle, and finally feed back the search results to 1 comparator to find the smallest word of 2 words in a third (ie final) cycle. In a known approach, the function of executing instructions in a single cycle is achieved by increasing the number of 16-bit comparators. Taking 7 16-bit comparators as an example, in a single cycle, use 4 comparators for the first comparison to reduce the search range from 8 words to 4 words, and then use 2 comparators, Reduce the search range from 4 words to 2 words, and finally use 1 comparator to find the smallest one from 2 words. However, each 16-bit comparator takes up a lot of space in the microprocessor, thus increasing the cost and reducing the processing performance.

Contents of the invention

The purpose of the present invention is to find out the minimum digital code and its corresponding position from the digital code set in a single cycle without increasing the circuit.

The invention provides a judging system for finding a minimum binary code from at least two binary codes. In an embodiment, the judging system includes a first adder, a second adder and a comparison circuit. The first adder adds up a plurality of first bits and a plurality of second bits to provide a first carry output and a first transfer output. These first bits are high bits of a first binary code. These second bits are inverted to the upper bits of a second binary code. The second adder adds up a plurality of third bits and a plurality of fourth bits to provide a second carry output. These third bits are the lower bits of the first binary code. These fourth bits are the inverse of the lower bits of the second binary code. The comparison circuit judges whether the first binary code is greater than the second binary code according to the first and second carry outputs and the first transfer output. Both the first and second binary codes are unsigned. The first and second adders perform unsigned binary addition. The first transfer output represents whether the first adder receives a carry input.

The present invention also provides a judging system for quickly finding a horizontal minimum value from multiple digital codes. The judging system of the present invention includes a plurality of difference circuits, a path selection circuit and a comparison circuit. Each difference circuit compares two digital codes. Routing circuitry assigns each of these digital codes to at least one difference circuit for comparing each digital code with other digital codes. Each difference circuit may include a high adder and a low adder. The high adder compares a high part of a first digital code with a high part of a second digital code to provide a first carry output and a transfer output. The low adder compares the low part of the first digital code with the low part of the second digital code to provide a second carry output. The comparison circuit compares the first and second carry outputs and compares the transfer outputs to obtain a minimum digital code among the digital codes.

Each transfer output indicates whether the high adder of one of these difference circuits receives a unary input. The comparison circuit includes a decoding circuit. The decoding circuit decodes the comparison bits to provide a plurality of minimum bits. Each minimum digit indicates whether the corresponding digital code is the minimum digital code. A location circuit informs the memory location of the minimum digital code. The judgment system may be integrated in a microprocessor chip to execute a fast horizontal minimum instruction.

The invention provides a judging method for finding a minimum digital code among multiple digital codes. In a possible embodiment, the judging method includes the following steps, comparing the high order of a first digital code and the high order of a second digital code to provide a first carry output and a transfer output; comparing the high order of the first digital code The low bit and the low bit of the second digital code are used to provide a second carry output; and according to the first and second carry output and the transfer output, it is judged that the first or second digital code is a smaller code. The judging method of the present invention may include sending each of these digital codes to at least one adder pair among a plurality of adder pairs, so as to compare each digital code with other digital codes to obtain a minimum digital code . The judging method of the present invention further includes decoding the comparison bit. The judging method of the present invention also includes knowing the location of the minimum digital code in a memory.

The present invention provides a system that utilizes a common adder circuit to execute one of a minimum level command and a sum of absolute error command. In one embodiment, the system includes a plurality of adders, a totalization circuit, a comparison circuit and a path selection circuit. Input operands include multiple numeric codes. For the error sum command, the digital codes include a first digital code set and a second digital code set. For horizontal minimal instructions, these codes consist of pairs of codes. Each code pair has a high code and a low code. Each adder compares a first digital code with a second digital code to provide an absolute error value and a carry output. The summing circuit sums up these absolute error values to provide a plurality of summed absolute error values. These adders form adder pairs and provide a transfer output. The comparison circuit combines the carry outputs and the transfer outputs to find a minimum digital code pair of the digital code pairs. When executing the horizontal minimum instruction, the path selection circuit transmits each digital code pair of these digital code pairs to at least one adder pair of these adder pairs, so as to compare each digital code pair with other digital code pairs . When executing the instruction of sum of absolute value of errors, the path selection circuit transmits the first and second digital code sets to these adder pairs, so as to obtain each digital code of the first digital code set and the second digital code The absolute value of the error between each digital code of the code set, the second digital code set has consecutive digital codes.

The present invention also provides a method for executing one of a minimum level command and a sum of absolute error command by using a shared adder circuit. In one embodiment, the method provided by the present invention includes: receiving a plurality of digital codes. These digital codes include a first set of digital codes and a second set of digital codes when executing the command of sum of absolute value of errors. These digital codes include a high digital code and a low digital code when executing the horizontal minimum command. The method provided by the present invention further includes providing multiple adders. Each adder compares a first digital code with a second digital code to provide an absolute error value and a carry output. The method provided by the present invention also includes summing up these absolute values of errors to provide a plurality of sums of absolute values of errors; classifying these adders into a plurality of adder pairs and providing a transfer output; combining these carry outputs and These transfer outputs are used to obtain a minimum digital code pair of these digital code pairs; and when the horizontal minimum instruction is executed, each digital code pair of these digital code pairs is sent to at least one adder of these adder pairs pairs, for comparing each pair of digital codes with other pairs of digital codes, and when executing the instruction of the sum of absolute value of errors, the first and second digital code sets are sent to these adder pairs to obtain the first The absolute value of the error between each digital code of a digital code set and each continuous digital code of the second digital code set.

Description of drawings

FIG. 1 shows an embodiment of a microprocessor 100 .

FIG. 2 is an embodiment of a comparison circuit.

FIG. 3 is an embodiment of the path selection circuit of the present invention.

FIG. 4 is an embodiment of the first adder circuit of the present invention.

FIG. 5 is an embodiment of the difference unit DIFF1 of the present invention.

FIG. 6 shows an embodiment of the summing unit S1 of the present invention.

FIG. 7 is an embodiment of the PMIN circuit 206 of the present invention.

FIG. 8 is an embodiment of the high-order/low-order comparison circuit 212 of the present invention.

[Description of main component symbols]

100: microprocessor;

102: scheduler;

104: complex integer execution unit;

106: simple integer execution unit;

108: floating point execution unit;

110: media unit;

114, 802: comparison circuit;

112: other units;

202: path selection circuit;

203: low-order adder circuit;

204: the first adder circuit;

206: the first PMIN circuit;

207: high-order adder circuit;

208: the second adder circuit;

210: the second PMIN circuit;

212: high-order/low-order comparator circuit;

302: buffer circuit;

304, 306, 308, 506, 510, 804, 806, 808: multiplexer;

402: difference circuit;

404: summing circuit;

410, 412: select a logic circuit;

502, 504, 602, 604, 606: adders;

514, 708, 716, 722, 726: AND gate;

516: OR gate;

508, 512, 702, 704, 706, 712, 714, 720, 710, 718, 724: inverters;

728: select circuit;

DIFF1～DIFF8: difference unit;

S1～S4: Sum unit.

Detailed ways

The following examples illustrate to enable those of ordinary skill in the art to make and use the present disclosure. Modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the general principles described herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments presented and described herein, but is to be given the widest scope consistent with the principles and novel features disclosed herein.

The present invention notes that known microprocessors use many cycles to execute horizontal minimum instructions. When the present invention executes the same instruction, only a single cycle is needed, and the circuit will not be greatly increased. The present invention provides a system and method for quickly obtaining the minimum level value. In order to make the features and advantages of the present invention more obvious and easy to understand, the preferred embodiments are specifically listed below, together with the accompanying drawings (Figs. 1-8 ), for details.

FIG. 1 is a structural diagram of a microprocessor 100 in an embodiment of the present invention. The processor 100 has a comparison circuit 114. The comparison circuit 114 can quickly find a horizontal minimum value from the digital code set, and obtain the sum of absolute differences between the first digital code set and the second digital code set. In this embodiment, FIG. 1 does not show other known systems and functions, such as instruction fetch, instruction queue, instruction decoding, and instruction reordering... wait. Although Fig. 1 does not show some known techniques, it does not affect the understanding of the present invention. The microprocessor 100 has a scheduler 102 . The scheduler 102 routes instructions or operations to select arithmetic logic units (ALUs) or execution units (EUs). As shown in Figure 1, the scheduler 102 is coupled to a complex integer execution unit (complex integer execution unit; IEU) 104, a simple integer execution unit (simple IEU) 106, a floating point execution unit (floating point execution unit; FPEU) 108, media A media unit 110 and other units 112, wherein the other units 112 are other similar or different processing units. The media unit 110 generally executes media-based instructions and operations, such as Streaming SIMD Extensions (SSE) or MultiMedia extension (MMX) and other similar instruction sets. SSE is a SIMD instruction set in Intel's x86 architecture, SIMD refers to single instruction multiple data (single instruction multiple data). The media unit 110 has a comparison circuit 114 for executing at least two independent media commands. In this embodiment, the two media instructions are called a horizontal minimum instruction (PMIN instruction) and a sum of absolute error instruction (PSAD instruction). The PSAD instruction represents the sum of the absolute values of errors of the first set of digital codes (or binary codes) and the second set of digital codes (or binary codes), wherein the second set of digital codes (or binary codes) follows the first set of digital codes. The first digital code set and the second digital code set will be described in detail later. By executing the PMIN command, a minimum digital code and its corresponding position can be obtained. In this embodiment, the above digital codes, binary codes and corresponding formats can be replaced with each other, and these codes represent digital codes of multiple bits or hexadecimal digits. The scheduler 102 has a memory 116 . The memory 116 is used for storing operands of the PSAD instruction and the PMIN instruction, and has a first bus ABUS and a second bus BBUS. In one embodiment, the first bus ABUS and the second bus BBUS can transmit 128 bits, but this is not intended to limit the invention. In other embodiments, the first bus ABUS and the second bus BBUS can transmit other numbers of bits. Although the media unit 110 is generally used to execute other media instructions well known to those skilled in the art, the comparison circuit 114 is used to execute PSAD and PMIN instructions.

In a possible embodiment, for the PSAD instruction, the first digital code set has 4 bytes (each byte has 8 bits), wherein the 4 bytes are unsigned bytes. For the PSAD instruction, the second set of digital codes has a set of bytes. This byte set has 11 consecutive bytes. At the same time, every 4 consecutive bytes will be classified into a group. For the second set of digital codes, each next group of 4 bytes starts with the next higher byte, which means that each next group will be shifted by 1 byte, therefore, the previous group will be overlapped The last 3 bytes of the . Assume that the second digital code set has 11 bytes B0-B10. First, B0-B3 are classified into the first group, and then, starting from the next higher byte (such as B1), they are further classified into the second group (B1-B4). Therefore, the second group ( B1 ˜ B4 ) overlaps the last 3 bytes ( B1 ˜ B3 ) of the first group ( B0 ˜ B3 ). The difference between each byte of the first set of digital codes and each byte of the second set of digital codes is called the absolute value of the error. The absolute values of the above errors are summed together. A specific example is the MPSADBW instruction in Intel's SSE4 program reference manual. For the PSAD instruction, the first bus ABUS transfers the first operand. The first operand consists of 4 unsigned bytes. The second bus BBUS transmits the second operand. The second operand has 11 unsigned bytes. The sum of the absolute value of the error is 8 10-bit binary codes without signs. The PSAD instruction may include one or more offsets (offsets) to find the above operands. The present invention does not limit the size of the offset. Any offset can be configured through the first bus ABUS and the second bus BBUS. Therefore, the corresponding operands will be configured on the first bus ABUS and the second bus BBUS The rightmost high bit position (right-most bit position). In this embodiment, the above offset is omitted. In one embodiment, the PMIN instruction provides the minimum value of 8 unsigned digital words in the first bus ABUS and the corresponding position of the minimum value, wherein each of the 8 unsigned digital words has 16 bits. A specific example is the PHMINPOSUW instruction in Intel's SSE4 program reference manual. For the PMIN instruction, the first bus ABUS transfers 8 words, each word has 16 bits. The bits transmitted by the second bus BBUS can be undefined or ignored, or the words transmitted by the second bus BBUS can be the same as those transmitted by the first bus ABUS. In this embodiment, the comparison circuit 114 uses the same adder circuit to execute two instructions (PMIN instruction and PSAD instruction) in a single cycle.

FIG. 2 is an embodiment of the comparison circuit 114 of the present invention. As shown in the figure, the comparison circuit 114 includes a routing circuit (routing circuit) 202, a low-order (low-order; LO) adder circuit 203, a high-order (high-order; HI) adder circuit 207, a high-order / Low order comparator circuit 212 . The path selection circuit 202 has two input terminals respectively coupled to the first bus ABUS and the second bus BBUS. The path selection circuit 202 has another input terminal for receiving the control code INSTR. The path selection circuit 202 rearranges or re-selects the bytes from the first bus ABUS and the second bus BBUS according to the control code INSTR received by the input terminal, so as to split the first bus ABUS and the second bus ABUS. Bytes of the bus BBUS. The control code INSTR has at least 1 bit. In this embodiment, when the control code INSTR is equal to 1, it means that the PMIN instruction is executed; when the control code INSTR is equal to 0, it means that the PSAD instruction is executed. The first bus ABUS is divided into a high part AH<31:0> and a low part AL<31:0>, wherein both the high part AH<31:0> and the low part AL<31:0> have 32 bits. The second bus BBUS is divided into a high part BH<55:0> and a low part BL<55:0>, wherein both the high part BH<55:0> and the low part BL<55:0> have 56 bits. How to rearrange the bytes of the first bus ABUS and the second bus BBUS or re-select paths will be described in detail later. The low-order adder circuit 203 has a first adder circuit 204 . The first adder circuit 204 is coupled to the first PMIN circuit 206 . The high-order adder circuit 207 has a second adder circuit 208 . The second adder circuit 208 is coupled to the second PMIN circuit 210 .

The first adder circuit 204 receives the control code INSTR, the low bits AL<31:0> and BL<55:0>, and outputs the sum of absolute error values PSAD<39:0> and the comparison bits C<5:0>. The sum of absolute error PSAD<39:0> has 40 bits. The compare bits C<5:0> have 6 bits. The compare bits C<5:0>, AL<15:0> and BL<47:0> are sent to the first PMIN circuit 206 . For the low part, the first PMIN circuit 206 outputs the minimum value PMINVAL<15:0> and the corresponding position PMINLOC<1:0>. The control code INSTR, the upper part AH<31:0> and BH<55:0> are sent to the second adder circuit 208 . The second adder circuit 208 outputs the sum of absolute error values PSAD<79:40> and compare bits C<11:6>. The sum of absolute error PSAD<79:40> has 40 bits. The compare bits C<11:6> have 6 bits. The comparison bits C<11:6>, AH<15:0> and BH<47:0> are sent to the second PMIN circuit 210 . For the high part, the second PMIN circuit 210 outputs the minimum value PMINVAL<31:16> and the corresponding position PMINLOC<3:2>. The minimum value PMINVAL<15:0> output by the first PMIN circuit 206 and the corresponding position PMINLOC<1:0> and the minimum value PMINVAL<31:16> output by the second PMIN circuit 210 and the corresponding position PMINLOC< 3:2> are combined to generate PMINVAL<31:0> and PMINLOC<3:0>. The high-order/low-order comparator circuit 212 receives PMINVAL<31:0> and PMINLOC<3:0>, and generates the final minimum digital code MINVAL<15:0> and its relative position MINLOC<2:0>.

The first adder circuit 204 and the second adder circuit 208 arrange the input bytes according to the instruction (ie, the control code INSTR), and perform comparison between the bytes. For the PSAD instruction, the combined PSAD<79:0> has eight 10-bit digital codes, where these digital codes have no sign. The eight 10-digit digital codes are the result of performing the operation of summing the absolute value of errors. For the PSAD instruction, the first PMIN circuit 206 , the second PMIN circuit 210 and the high-order/low-order comparator circuit 212 can be omitted. For the PMIN instruction, when each high-order part and low-order part are input, PSAD<79:0> can be omitted, and the comparison bits C<11:0> received by the first PMIN circuit 206 and the second PMIN circuit 210 can be The smallest digital code and relative position can be known. When the first bus ABUS provides 128-bit input data, the high-order/low-order comparator circuit 212 receives and compares the minimum digital code of the high-order part and the low-order part, and outputs the minimum value MINVAL<15:0> and the relative position MINLOC< 2:0>.

FIG. 3 is an embodiment of the path selection circuit 202 of the present invention. The path selection circuit 202 is used to arrange or re-select the digital codes provided by the first bus ABUS and the second bus BBUS according to specific instructions. The buffer circuit 302 receives ABUS<31:0>, and outputs corresponding AL<31:0> for the PSAD instruction and the PMIN instruction. In one embodiment, buffer circuit 302 may include a separate buffer for each bit such that ABUS<31:0> is effectively duplicated as AL<31:0>. In other words, AL<31>=ABUS<31>, AL<30>=ABUS<30>, ..., AL<0>=ABUS<0>. For the PSAD instruction and the PMIN instruction, AL<31:0> has 4 bytes A3˜A0. For the PMIN instruction, the bytes A3-A0 can be divided into two pairs, wherein A3 and A2 can form the word W1, and A1 and A0 can form the word W0. Words W1 and W0 each have 16 bits. Multiplexer 304 receives ABUS<95:64> and ABUS<31:0>. When the control signal of the multiplexer 304 is equal to logic 1 (or high level), the output AH<31:0> of the multiplexer 304 is equal to ABUS<95:64>. When the control signal of the multiplexer 304 is equal to logic 0 (or low level), the output AH<31:0> of the multiplexer 304 is equal to ABUS<31:0>. In one embodiment, a separate 1-bit wide multiplexer is provided for each of the 32-bit AH<31:0> bits, thus having a separate multiplexer for each input and output. MUX path. If the control code INSTR represents the PMIN instruction, then the multiplexer 304 regards ABUS<95:64> as AH<31:0>. These 32 bits form 4 bytes A11-A8. For PMIN, bytes A11-A8 can be divided into two words, wherein bytes A11 and A10 can form word W5, and bytes A9 and A8 can form word W4. If the control code INSTR represents PSAD, the multiplexer 304 uses ABUS<31:0> as AH<31:0>. These 32 bits form 4 bytes A3-A0. The byte is copied because the first operand of the PSAD instruction is the same for the high-order and low-order parts, which will be explained in detail later.

When the control signal of the multiplexer 306 is logic 1 (that is, the control code INSTR=1), the multiplexer 306 receives and outputs 8 high-order 0x8 and ABUS<63:16>, wherein the logic values of the 8 high-order 0x8 are all is 0. At this time, the output BL<55:0> of the multiplexer 306 is 8 high bits 0x8 and ABUS<63:16>. When the control signal of the multiplexer 306 is logic 0, the multiplexer 306 receives and outputs BBUS<55:0>. At this time, the output BL<55:0> of the multiplexer 306 is BBUS<55:0>. In one embodiment, for each byte of each bus, a multiplexer having a width of 1 bit may be used. If the control code INSTR represents the PMIN command, then ABUS<63:16> will be selected. ABUS<63:16> has 6 bytes A7-A2. The bytes A7-A2 can be divided into 3 pairs respectively. Bytes A7 and A6 may make up word W3. Bytes A5 and A4 may make up word W2. Bytes A3 and A2 may make up word W1. If the control code INSTR represents the PSAD instruction, BBUS<55:0> will be selected. BBUS<55:0> has the second operand of 7 low bytes B6~B0. When the control terminal of the multiplexer 308 is logic 1, the multiplexer 308 receives and outputs 8 high bits 0x8 and ABUS<127:79>, wherein the logic values of the 8 high bits 0x8 are all 0. At this time, the output BH<55:0> of the multiplexer 308 is a combination of 8 high bits 0x8 and ABUS<127:79>. When the control terminal of the multiplexer 308 is logic 0, the multiplexer 308 receives and outputs BBUS<87:32>. At this time, the output BH<55:0> of the multiplexer 308 is BBUS<87:32>. If the control code INSTR is PMIN instruction, ABUS<127:79> will be selected. ABUS<127:79> has 6 bytes A15-A10. There are 3 pairs of bytes A15～A10 respectively. Bytes A15 and A14 may make up word W7. Bytes A13 and A12 may make up word W6. Bytes A11 and A10 may make up word W5. If the control code INSTR is PSAD instruction, BBUS<87:32> will be selected. BBUS<87:32> has 7 high bytes B10~B4, and the 7 high bytes B10~B4 constitute the second operand of the PSAD instruction.

Please refer to FIG. 2, for the PMIN instruction, using the selection of the path selection circuit 202 shown in FIG. Adder circuit 204 . The first adder circuit 204 compares the word W0 with the words W1-W3 respectively, then compares the word W1 with the words W2-W3 respectively, then compares the word W2 with the word W3, and provides corresponding The compare bits C<5:0> of the The first PMIN circuit 206 receives the words W3˜W0, and takes the smallest word as PMINVAL<15:0>. The first PMIN circuit 206 indicates the minimum word of the low part of the first bus ABUS and its corresponding position PMINLOC<1:0>. For example, if the minimum word is at ABUS<15:0>, then PMINLOC=00; if the minimum word is at ABUS<32:16>, then PMINLOC=01. Similarly, for the PMIN instruction, the words W5 and W4 can be provided to the AH bus, and the words W7 ˜ W5 can be provided to the BH bus for transmission to the second adder circuit 208 . The second adder circuit 208 compares word W4 with words W5-W7, then compares word W5 with words W6-W7 respectively, then compares word W6 with word W7 respectively, and provides corresponding Compare bits C<11:6> of the The second PMIN circuit 210 receives the words W7-W4, and sets the corresponding bits of the smallest word in the words W7-W4 as PMINVAL<31:16>. The second PMIN circuit 210 also indicates the corresponding position PMINLOC<3:2> of the minimum word located in the upper part of the first bus ABUS. For example, if the minimum word is at ABUS<79:64>, then PMINLOC=00; if the minimum word is at ABUS<95:65>, then PMINLOC=01. The high-order/low-order comparator circuit 212 compares the words of PMINVAL<15:0> with the words of PMINVAL<31:16> to identify which is the minimum value in ABUS<127:0>. Through the comparison result of the high-order/low-order comparator circuit 212 , the relative position MINLOC<2:0> of the minimum value can also be known.

Please refer to FIG. 2, for the PSAD instruction, the path selection circuit 202 (as shown in FIG. 3 ) provides the bytes A3-A0 of the first operand from the first bus ABUS to AL<31 through selection of bytes. :0> and AH<31:0>, and provide AL<31:0> to the first adder circuit 204 and AH<31:0> to the second adder circuit 208, respectively. The path selection circuit 202 takes the bytes B6 ˜ B0 of the second operand from the second bus BBUS as BL<55:0>, and transmits the BL<55:0> to the first adder circuit 204 . The path selection circuit 202 takes the bytes B10 ˜ B4 of the second operand from the second bus BBUS as BH<55:0>, and transmits the BH<55:0> to the second adder circuit 208 . For the PSAD instruction, the first adder circuit 204 sums the difference between bytes A0 and B0, the difference between bytes A1 and B1, the difference between bytes A2 and B2, and the difference between bytes A3 and B3 together and provide the first 10 bits of the resulting PSAD<9:0>. The first adder circuit 204 sums together the difference between bytes A0 and B1, the difference between bytes A1 and B2, the difference between bytes A2 and B3, and the difference between bytes A3 and B4 and provides the first Two 10-bit results in PSAD<19:10>. The first adder circuit 204 sums together the difference between bytes A0 and B2, the difference between bytes A1 and B3, the difference between bytes A2 and B4, and the difference between bytes A3 and B5 and provides the first Three 10-bit results in PSAD<29:20>. The first adder circuit 204 sums together the difference between bytes A0 and B3, the difference between bytes A1 and B4, the difference between bytes A2 and B5, and the difference between bytes A3 and B6 and provides the first Three 10-bit results PSAD<39:30>. Similarly, the second adder circuit 208 sums the difference between bytes A0 and B4, the difference between bytes A1 and B5, the difference between bytes A2 and B6 and the difference between bytes A3 and B7, And provide the result PSAD<49:40> for the first 10 bits. The second adder circuit 208 sums the difference between bytes A0 and B5, the difference between bytes A1 and B6, the difference between bytes A2 and B7, and the difference between bytes A3 and B8 and provides the first Two 10-bit results PSAD<59:50>. The second adder circuit 208 adds together the difference between bytes A0 and B6, the difference between bytes A1 and B7, the difference between bytes A2 and B8, and the difference between bytes A3 and B9 and provides the first Three 10-bit results in PSAD<69:60>. The second adder circuit 208 adds together the difference between bytes A0 and B7, the difference between bytes A1 and B8, the difference between bytes A2 and B9, and the difference between bytes A3 and B10 and provides Four 10-bit results in PSAD<79:70>.

FIG. 4 is an embodiment of the first adder circuit 204 of the present invention. The first adder circuit 204 processes the bytes in AL<31:0> and BL<31:0> and provides PSAD<39:0> or C<5:0>. The first adder circuit 204 includes a difference circuit (difference circuit) 402 , a sum circuit (sum circuit) 404 , a selection logic circuit (selection logic) 410 and a selection logic circuit 412 . The difference circuit 402 has a plurality of difference units DIFF1˜DIFF8. The difference units DIFF1 to DIFF8 are independent of each other. The summing circuit 404 has summing units S1 to S4. The summing units S1-S4 are independent of each other. Each difference unit judges the difference (no sign) between 4 bytes (ie, 2 pairs of bytes). Each difference unit inverts one byte of each pair of bytes and then sums it with the other byte. The difference produced by each pair of bytes is the absolute value of the error. The byte data received by the difference unit is determined by the first executed instruction. The selection logic circuit 410 has a plurality of multiplexing circuits. Each multiplexing circuit is independent of each other. These multiplexing circuits select specific bytes for the difference unit DIFF3 according to the instruction executed at the beginning. As shown in the figure, for the PMIN instruction, when the control terminal of the selection logic circuit 410 is logic 1 (that is, the control code INSTR=1), the selection logic circuit 410 selects and outputs the bytes BL<47:40>, BL< 31:24>, BL<39:32> and BL<23:16> to the difference unit DIFF3. Bytes BL<47:40>, BL<31:24>, BL<39:32>, and BL<23:16> correspond to bytes A7˜A4, respectively. For the PSAD instruction, when the control terminal of the selection logic circuit 410 is logic 0 (that is, the control code INSTR=0), the selection logic circuit 410 selects and outputs bytes BL<23:16>, AL<15:8>, BL<15:8> and AL<7:0> are assigned to the difference unit DIFF3. Bytes BL<23:16>, AL<15:8>, BL<15:8>, and AL<7:0> correspond to bytes B2, A1, B1, and A0, respectively. Similarly, for the PMIN instruction, when the control terminal of the selection logic circuit 412 is logic 1, the selection logic circuit 412 selects and outputs bytes AL<15:8> and AL<7:0> to the difference unit DIFF8. Bytes AL<15:8> and AL<7:0> correspond to bytes A1 and A0, respectively. For the PSAD instruction, when the control terminal of the selection logic circuit 412 is logic 0, the selection logic circuit 412 selects and outputs bytes AL<23:16> and AL<15:8> to the difference unit DIFF3. Bytes AL<23:16> and AL<15:8> correspond to bytes A2 and A1, respectively.

For the PSAD instruction, the first inverting input of the difference unit DIFF1 receives the bytes BL<15:8>. Byte BL<15:8> corresponds to Byte B1. The second non-inverting input of difference unit DIFF1 receives bytes AL<15:8>. Byte AL<15:8> corresponds to Byte A1. The difference unit DIFF1 determines the absolute value of the error (|A1-B1 |) between the bytes A1 and B1. The difference unit DIFF1 takes the absolute value of the error (|A1-B1|) between the bytes A1 and B1 as the result AD1, and outputs it from the first output terminal. Likewise, the third inverting input of the difference unit DIFF1 receives the bytes BL<7:0>. Byte BL<7:0> corresponds to Byte B0. The fourth non-inverting input of difference unit DIFF1 receives bytes AL<7:0>. Byte AL<7:0> corresponds to byte A0. Difference unit DIFF1 determines the absolute value of the error (|A0-B0|) between bytes A0 and B0. The difference unit DIFF1 takes the absolute value of the error (|A0-B0|) between the bytes A0 and B0 as the result AD2, and outputs it from the second output terminal. Similarly, the difference unit DIFF2 determines the absolute value of the error between the bytes A3 and B3 (|A3-B3|), and takes the absolute value of the error between the bytes A3 and B3 as AD3, and outputs it from the first output terminal. The difference unit DIFF2 determines the absolute value of the error between the bytes A2 and B2 (|A2-B2|), and takes the absolute value of the error between the bytes A2 and B2 as AD4, and outputs it from the second output terminal. In a word, when the control code INSTR is a PSAD instruction, the difference circuit 402 determines the absolute value of the error between byte A0 and bytes B0-B3 respectively, the absolute value of error between byte A1 and byte B1-B4 respectively, the absolute value of error between byte A1 and byte B1-B4, The absolute values of the errors between the section A2 and the bytes B2-B5 respectively, and the absolute values of the errors between the byte A3 and the bytes B3-B6 respectively.

The sum unit S1 calculates the sum of 4 bytes AD1-AD4, and takes the calculated result as 10-bit PSAD<9:0>. The calculation result of the sum unit S1 corresponds to (|A0-B0|)+(|A1-B1|)+(|A2-B2|)+(|A3-B3|). For the PSAD instruction, the difference unit DIFF3 determines the absolute value of the error between A0 and B1, and takes the absolute value of the error between A0 and B1 as AD6. The difference unit DIFF3 determines the absolute value of the error between A1 and B2, and takes the absolute value of the error between A1 and B2 as AD5. The difference unit DIFF4 determines the absolute value of the error between A2 and B3, and takes the absolute value of the error between A2 and B3 as AD8. The difference unit DIFF4 determines the absolute value of the error between A3 and B4, and takes the absolute value of the error between A3 and B4 as AD7. The sum unit S2 calculates the sum of 4 bytes AD5-AD8, and takes the calculated result as 10-bit PSAD<19:10>. The calculation result of the sum unit S2 corresponds to (|A0-B1|)+(|A1-B2|)+(|A2-B3|)+(|A3-B4|). Similarly, for the PSAD instruction, the summing unit S3 calculates the sum of the 4 bytes AD9-AD12, and takes the calculated result as 10-bit PSAD<29:20>. The calculation result of the sum unit S3 corresponds to (|A0-B2|)+(|A1-B3|)+(|A2-B4|)+(|A3-B5|). Finally, for the PSAD instruction, the sum unit S4 calculates the sum of the 4 bytes AD13-AD16, and takes the calculated result as 10-bit PSAD<39:30>. The calculation result of the sum unit S3 corresponds to (|A0-B3|)+(|A1-B4|)+(|A2-B5|)+(|A3-B6|). Although FIG. 4 only shows an embodiment of the first adder circuit 204, the second adder circuit 208 is substantially similar to the first adder circuit 204, and is used to determine the difference between the byte A0 and the bytes B4-B7 respectively. The absolute value of error, the absolute value of error between byte A1 and byte B5~B8, the absolute value of error between byte A2 and byte B6~B9, and the error between byte A3 and byte B7~B10 The absolute value of the error between. In addition, the second adder circuit 208 sums up the four absolute error values, and provides four summed values according to the summed results. PSAD<79:40> contains these 4 summed values.

In summary, for the PSAD instruction, the difference circuit 402 is used to determine the difference between each byte (A3:A0) in the first digital code set and each byte (B10:B0) in the second digital code set The absolute value of the error. After the first group B3:B0 is processed, the comparison starts from the next higher bit, such as B1:B4, B2:B5, B3:B6...etc. Therefore, in the 8 groups, absolute error values AD1-AD4, AD5-AD8, . . . , AD29-AD32 will be generated. The summing circuit 404 sums the absolute error values of each group and provides a corresponding sum of absolute error values PSAD<79:0>.

When the control code INSTR is the PMIN instruction, except for the selected byte is different, the processing method of the difference circuit 402 is roughly the same. The sum of AD1~AD16 and PSAD<39:0> can be omitted, only compare bits C<5:0> are needed. Difference unit DIFF1 compares or otherwise determines the absolute value of the error between A1 and A3 and the absolute value of the error between A0 and A2. The first byte A3 is the high byte of word W1 and the second byte A1 is the high byte of word W0. The third byte A2 is the low byte of word W1 and the fourth byte A0 is the low byte of word W0. In this embodiment, the difference unit DIFF1 compares the high byte and low byte of the words W1 and W0 respectively. The difference unit DIFF1 determines the compare bit C<0>. Bit C<0> indicates which word (W1 or W0) is the smaller word. Similarly, difference unit DIFF2 compares high bytes A5 and A3 of words W2 and W1, and compares low bytes A4 and A2 of words W2 and W1 to determine which word (W2 or W1) is the smaller word, And provide compare bit C<3>. Likewise, difference unit DIFF3 compares high bytes A7 and A5 of words W3 and W2, and compares low bytes A6 and A4 of words W3 and W2 to determine which word (W3 or W2) is the smaller word, And provide compare bit C<5>. For the PMIN instruction, the difference unit DIFF4 can be omitted. The difference unit DIFF5 compares the high byte A5 and A1 of the word W2 and W0, and compares the low byte A4 and A0 of the word W2 and W0 to determine which word (W2 or W0) is the smaller word and provide a comparison Bit C<1>. The difference unit DIFF6 compares the high bytes A7 and A3 of the words W3 and W1, and compares the low bytes A6 and A2 of the words W3 and W1 to determine which word (W3 or W1) is the smaller word and provide a comparison Bit C<4>. For PMIN, the difference unit DIFF7 can be omitted. The difference unit DIFF8 compares the high byte A7 and A1 of the word W3 and W0, and compares the low byte A6 and A0 of the word W3 and W0 to determine which word (W3 or W0) is the smaller word and provide a comparison Bit C<2>.

In summary, for the PMIN instruction, the compare bit C<0> of the difference circuit 402 of the first adder circuit 204 represents the smaller of the words W0 and W1. Compare bit C<1> indicates the lesser between words W0 and W2. Compare bit C<2> indicates the lesser between words W0 and W3. Compare bit C<3> indicates the smaller of words W1 and W2. Compare bit C<4> indicates the smaller of words W1 and W3. Compare bit C<5> indicates the smaller of words W2 and W3. Although FIG. 4 does not show the detailed circuit of the second adder circuit 208, the second adder circuit 208 also has the same difference circuit as the first adder circuit 204, which is used for the words W4˜ W8 performs the same comparison and provides the corresponding compare bits C<11:6>. Thus, for PMIN, compare bit C<6> represents the lesser of words W4 and W5. Compare bit C<7> indicates the lesser of words W4 and W6. Compare bit C<8> indicates the lesser of words W4 and W7. Compare bit C<9> indicates the lesser of words W5 and W6. Compare bit C<10> indicates the lesser of words W5 and W7. Compare bit C<11> indicates the lesser of words W6 and W7. The first PMIN circuit 206 uses the comparison bits C<5:0> to identify the minimum of the words W0 - W3 . The second PMIN circuit 210 uses the comparison bits C<11:6> to identify the minimum of the words W4˜W7.

FIG. 5 is an embodiment of the difference unit DIFF1 of the present invention. As shown, the difference unit DIFF1 has a pair of adders. The pair of adders has a high (or first) adder 502 and a low (or second) adder 504 . Both the adders 502 and 504 have an inverting input terminal B and a non-inverting input terminal A. Therefore, both adder 502 and adder 504 can perform a subtraction operation to determine the signal difference between the inverting input terminal B and the non-inverting input terminal A. For the PSAD instruction, the inverting input B of adder 502 receives byte B1. For the PMIN instruction, the inverting input B of adder 502 receives byte A3. For the PSAD and PMIN instructions, the non-inverting input A of adder 502 receives byte A1. The adder 502 performs an inversion operation on each bit of the byte received by the inversion input terminal B to obtain an inversion value ~B, where ~ represents an inversion in binary. The adder 502 sums the inverted result (~B) and the byte received by the input terminal A without a sign (that is, A+～B=A-B), and then sends the summed result to the output terminal A SUM output. The adder 502 has a carry out (CO) terminal CO for providing a carry out signal CO1. When the summing result obtained by the adder 502 overflows, the carry output signal CO1 is logic 1. The adder 502 also increments the summed result, and outputs the incremented result from the output terminal INCSUM. The adder 502 has a propagate output terminal CP. If the adder outputs a carry input (not provided), the transfer output signal CP1 of the transfer output terminal CP is logic 1. In FIG. 5 , although there is no carry input, if the adder 502 receives and transmits the carry input, the output signal CP1 is logic 1. In one embodiment, each bit of the byte received at the input terminal A and each bit of the byte received at the input terminal B are ORed one-to-one. After the OR operation, 8 operation results can be obtained. After these 8 operation results, an AND operation is performed. According to the OR operation result and the AND operation result, the logic level of the transfer output signal CP1 of the transfer output terminal CP can be determined. The output terminal SUM is coupled to the input terminal of the inverter 508 . Inverter 508 has a separate inverter for each bit of the byte. The output terminal of the inverter 508 is coupled to the input terminal 0 of the multiplexer 506 . The output terminal INCSUM is coupled to the input terminal 1 of the multiplexer 506 . The select input terminal of the multiplexer 506 receives the carry out signal CO1. The output signal AD1 of the multiplexer 506 is the absolute value of the error between the bytes received by the input terminals A and B of the multiplexer 502 .

Likewise, for the PSAD instruction, the inverting input B of adder 504 receives byte B0. For the PMIN instruction, the inverting input B of adder 504 receives byte A2. For the PSAD and PMIN instructions, input A of adder 504 receives byte A0. The adder 504 performs an inversion operation on each bit of the byte received by the inversion input terminal B to generate an opposite logic value, such as ~B. The adder 504 performs an unsigned sum of the inverted result (˜B) and the byte received at the input terminal A, and provides output signals to the output terminals INCSUM, SUM and CO. Since the output terminals INCSUM, SUM and CO of the adder 504 are similar to those of the adder 502 , details are omitted here. The output terminal CO of the adder 504 provides a carry out signal CO2. If the adder 504 has a transfer output CP, the transfer output CP may not be used or omitted. The CP output terminal of the adder 504 may not output a signal. The output terminal INCSUM of the adder 504 is coupled to the input terminal 1 of the multiplexer 510 . The multiplexer 510 is used to provide AD2. The output terminal SUM of the adder 504 is coupled to the input terminal of the inverter 512 . The output terminal of the inverter 512 is coupled to the input terminal 0 of the multiplexer 510 . The select input terminal of the multiplexer 510 receives the carry out signal CO2. One of the two input terminals of the AND gate 514 receives the carry out signal CO2. The OR gate 516 is used to generate the comparison bit C<0>, and one of the two input terminals of the OR gate 516 receives the carry output signal CO1. The output terminal CP of the adder 502 is coupled to an input terminal of the AND gate 514 . The other input terminal of the AND gate 514 receives the carry output signal CO2 from the output terminal CO of the adder 504 . An output terminal of the AND gate 514 is coupled to an OR gate 516 .

For the adders 502 and 504, if the byte of the input terminal A is greater than the byte of the input terminal B, the output terminal CO is logic 1, and the output terminal INCSUM represents the absolute value of the error between the input terminals A and B, That is |A-B|. When the adder 502 sets the carry output signal CO1 to logic 1, the comparison bit C<0>=1 output by the OR gate 516 . When the carry output signal CO1 is logic 1, the logic values of the input terminals A and B can determine the transfer output signal CP1 of the adder 502 to be logic 0 or 1. When the carry output signal CO1 is logic 1, the OR gate 516 can set the comparison bit C<0> to logic 1. Therefore, for the comparison bit C<0>, the value of the output signal CP1 is not important. For example, if the binary code received by input A is 00000100 (4 in decimal), and the binary code received by input B is 00000010 (2 in decimal), then the The difference A-B=00000010 (decimal code is 2). The binary code received by the input terminal B will be inverted first, so the result after the inversion ~B=11111101. When the binary code received by the input terminal A and ~B are summed without a sign, the summed result A+~B (or A-B) is 00000001, and the carry output signal CO1 is logic 1 (passing the output signal CP1=0). Therefore, the summed result (ie, the value of the output SUM) is not the correct value. The output terminal of the inverter (508 or 512) is ~SUM (that is, the inverted value of the binary code of the output terminal SUM)=11111110. The value of the output terminal of the inverter is also not the correct value. The value of the output INCSUM is 00000001+1=00000010, which is the correct value. Therefore, for the adders 502 and 504, when the byte of the input terminal A is greater than the byte of the input terminal B, the output terminal CO=1, therefore, the corresponding multiplexer (506 or 510) will input the terminal 1 The value of (ie INCSUM) is considered the correct output (absolute value between inputs A and B).

If the value of the input terminal A is less than or equal to the value of the input terminal B, the output terminal CO=0, and the corresponding multiplexer will regard the output signal ~B of the corresponding inverter (508 or 512) as correct output. When the value at input A is equal to the value at input B, the correct output is 00000000. Although the correct output will be reflected in the output terminals INCSUM and ~SUM, but because the output terminal CO=0, the corresponding multiplexer will select ~SUM. When the value at input A is equal to the value at input B, the value at output CP = 1. For example, when the values of input terminals A and B are both equal to 00001111, then the value of input terminal A plus the inverse value of input terminal B~B is equal to 00001111+11110000=11111111=SUM, and the value of output terminal CP= 1. The inverted value of the output SUM (ie ~SUM) is 00000000, which is the correct value. The value of the output INCSUM is 1+11111111, which results in 00000000, which is also the correct value (although it will not be selected by the multiplexer). When the value at input A is less than the value at input B, output CO=0, and the multiplexer sees ~SUM as the correct value. For example, if input A has a value of 00000010 and input B has a value of 00000100, then |A-B|=00000010. In this example, A+～B=00000010+11111011=11111101=SUM. Since the output terminal CO=0, ~SUM=00000010 will be regarded as the correct value. In this example, the value of the output INCSUM is equal to 1+11111101=11111111, which is not the correct value.

When the control code INSTR is a PSAD instruction, according to the PSAD operation, the adder 502 can obtain the absolute value of the error AD1=|A1-B1|, and the adder 504 can obtain the absolute value of the error AD2=|A0-B0|, and the comparison can be omitted Bit C<0>. When the control code INSTR is the PMIN instruction, if A1>A3, then the high byte of word W0 is greater than the high byte of word W1, so W0>W1. In this example, when W0>W1, since CO1=1, C<0>=1. When A3>A1, both CO1 and CP1 of the adder 502 are logic 0, so C<0>=0, which represents the word W0<W1. If A1=A3, the output of adder 502 CO1=1 and CP1=0. In this example, the comparison result of the low byte of the relative word of the adder 504 is used to determine the relative value of the words W0 and W1. When the high bytes are all equal, then CP1=1, if A0>A2, then the low byte of word W0 is greater than the low byte of word W1, so W0>W1. In this example, both CP1 and CO2 are logic 1, so C<0>=1. If the high bytes are all equal, then CP1=1, then A0 is less than or equal to A2, so CO2 is logic 0, making C<0>=0. In this example, word W0 is less than or equal to W1, and in other examples, word W0 is taken as the minimum value. The structures and operations of other difference circuits (DIFF2-DIFF8) are the same, and are used to judge AD3-AD16. The difference units DIFF4 and DIFF7 can be simplified. In particular, a logic device for receiving CO and CP to determine the corresponding comparison bit C<x> is not necessary. The transfer logic used by each individual adder can also be omitted if necessary.

Please refer to FIG. 4 and FIG. 5 , in the PMIN instruction and the PSAD instruction, the same adder circuit is used, especially each adder pair in each difference unit can be applied in the PMIN instruction and the PSAD instruction. For the PSAD instruction, each independent adder circuit is used to obtain the absolute value of the error between the input byte pairs. For the PMIN instruction, although the sum of the absolute values of the errors obtained by the PSAD instruction is not necessary, each adder pair uses a comparison between bytes to determine which word has the minimum value. In the PSAD instruction, the path selection circuit makes maximum use of the adder to help the PMIN instruction. As mentioned above, for the PMIN instruction, the multiple adders are divided into a number of adder pairs. The high part (such as the high byte) of a pair of digital codes (such as two words) is provided to the corresponding input terminal of the first adder, and the low part (such as the low byte) of the pair of digital codes is provided to the second The corresponding input of the adder. By modifying the two adders, it gets the carry output. Pass the high adder in the adder pair so that it has a pass-through output. The carry out and transfer out of each adder pair are used to determine the minimum value of each digital code pair. For the PSAD instruction, the result processed by the adder is used to obtain the absolute value of the error between the first operand and the second operand, and for the PMIN instruction, the result processed by the adder can obtain 8 word sets The smallest of , where the first operand has 4 bytes and the second operand has 11 bytes.

Fig. 6 shows a possible embodiment of the summing unit S1 of the present invention. The summing unit S1 has an adder 602 , an adder 604 and an adder 606 for providing a 10-bit result PSAD<9:0>. Both adder 602 and adder 604 have 8 bits, and adder 606 has 9 bits. The adder 602 and the adder 604 are similar to the adder 502, the difference is that the adder 602 and the adder 604 do not have an inverting input terminal, and the INCSUM circuit is not necessary, so it can be omitted. In addition, the transfer output circuit is not necessary, so it can be omitted. The adder 602 performs unsigned summation on the binary values AD1 and AD2, and provides a first sum value SUM1 (=AD1+AD2) and a corresponding carry output C1. The adder 604 performs an unsigned sum of the binary values AD3 and AD4, and provides a second sum value SUM2 (=AD3+AD4) and a corresponding carry output C2. The carry out C1 acts as the most significant bit (MSB) of SUM1. The carry out C2 acts as the most significant bit (MSB) of SUM2. The first input terminal of the adder 606 receives the combination result of the carry output C1 and the first sum SUM1 . The second input terminal of the adder 606 receives the combination result of the carry output C2 and the second sum value SUM2 . Adder 606 receives 9 bits at both inputs. The adder 606 performs unsigned summation on the received data ( C1 , SUM1 + C2 , SUM2 ) at the two input terminals, and provides a 10-bit output result PSAD<9:0>. The smallest 9 bits PSAD<8:0> represent the result of unsigned binary addition, while the most significant bit MSB PSAD<9> represents the result of carry-out summation. In this embodiment, the summing unit S1 sums the first error absolute value group ( AD1 ˜ AD4 ) to obtain a first error absolute value total PSAD<9:0>. The structures of the other summing units S2-S4 are the same, respectively summing up the error absolute value groups AD5-AD8, AD9-AD12, and AD13-AD16 to provide the total error absolute value PSAD<19:10>, PSAD<29 :20> and PSAD<39:30>.

FIG. 7 is an embodiment of the PMIN circuit 206 of the present invention. The PMIN circuit 206 has a decoding logic circuit 701 , a selection logic circuit 728 and a location logic circuit (location logic) 703 . The decoding logic circuit 701 has an inverter 702, an inverter 704, an inverter 706, an inverter 712, an inverter 714, an inverter 720, an inverter 710, an inverter 718, and an inverter 724 and AND gate 708 , AND gate 716 , AND gate 722 and AND gate 726 . Each of the AND gate 708 , the AND gate 716 , the AND gate 722 and the AND gate 726 has three input terminals. The position logic circuit 703 has an OR gate 730 and an OR gate 732 . Both the OR gate 730 and the OR gate 732 have two input terminals. The comparison bits C<2:0> are respectively provided to the inverter 702 , the inverter 704 and the inverter 706 . The AND gate 708 receives the outputs of the inverter 702 , the inverter 704 and the inverter 706 . The AND gate 708 outputs a signal W0_MIN. Signal W0_MIN is logic 1 when word W0 is the minimum word. The comparison bits C<3:4> are provided to the inverter 712 and the inverter 714 respectively. The three input terminals of the AND gate 716 respectively receive the outputs of the inverter 712 and the inverter 714 and the comparison bit C<0>. The AND gate 716 outputs a signal W1_MIN. Signal W1_MIN is logic 1 when word W1 is the minimum word. The input of inverter 720 receives C<5>. The AND gate 722 receives the output of the inverter 720 , C<1> and C<3> respectively. The AND gate 722 outputs a signal W2_MIN. Signal W2_MIN is logic 1 when word W2 is the minimum word. The inverters 710 , 718 and the inverter 724 respectively receive the signals W0_MIN, W1_MIN and W2_MIN to generate the signals ~W0_MIN, ~W1_MIN and ~W2_MIN respectively. The signals ~W0_MIN, ~W1_MIN and ~W2_MIN respectively indicate that the corresponding word is not the minimum value. The AND gate 726 receives the signals ~W0_MIN, ~W1_MIN and ~W2_MIN, and outputs the signal W3_MIN. Signal W3_MIN is logic 1 when word W3 is the minimum word.

AL<15:0>, BL<15:0>, BL<31:16> and BL<47:32> respectively represent words W0-W3. The selection circuit 728 receives AL<15:0>, BL<15:0>, BL<31:16>, BL<47:32>, signals W0_MIN˜W3_MIN. At the same time, only one of the signals W0_MIN˜W3_MIN is logic 1, which means that within this period, the corresponding word of W0_MIN˜W3_MIN is the minimum value. Therefore, the selection circuit 728 selects one of the words W0 to W3 as the minimum word, and outputs the minimum word as PMINVAL<15:0>. OR gate 730 receives signals W3_MIN and W2_MIN. The OR gate 730 has an output terminal for outputting a corresponding bit PMINCLOC<1>. The OR gate 732 receives the signals W3_MIN and W1_MIN. The OR gate 732 has an output terminal for outputting the corresponding bit PMINCLOC<0>. In this embodiment, through PMINVAL<15:0>, the minimum of words W0~W3 can be known, and PMINLOC<1:0> represents the second half of the first bus ABUS received by the low-order adder circuit 203 The relative position of the smallest word in the partial word. The structure of the PMIN circuit 210 is similar to that of the PMIN circuit 206 for providing PMINVAL<31:16> and PMINLOC<3:2> representing the smallest of the words W4˜W7. PMINLOC<3:2> represents the corresponding position of the minimum among the first half words of the first bus ABUS received by the high-order adding circuit 207 .

FIG. 8 is an embodiment of the high-order/low-order comparison circuit 212 of the present invention. The inverting input terminal of the 16-bit comparison circuit 802 receives PMINVAL<31:16> provided by the high-order adder 207 . The non-inverting input terminal of the comparison circuit 802 receives PMINVAL<15:0> provided by the low-order adder circuit 203 . The comparison circuit 802 has a carry output terminal CO for providing the signal MINLOC<2>. The comparison circuit 802 compares the minimum word of high order and low order, and outputs the carry as MINLOC<2>. The carry output terminal CO of the comparison circuit 802 is the same as the output terminal CO of the above-mentioned adder. If the word of PMINVAL<15:0> is larger than the word of PMINVAL<31:16>, MINLOC<2> of the carry output terminal CO of the comparison circuit 802 is logic 1, otherwise MINLOC<2> is logic 0. MINLOC<2> is the Most Significant Bit (MSB) of the position value MINLOC<2:0>. Since MINLOC<2> is logic 1, the minimum value is in the first half word of the first bus ABUS. Conversely, if MINLOC<2> is logic 0, it indicates that the minimum value is located in the second half word of the first bus ABUS. MINLOC<2> is used as the selection input terminal of the multiplexer 804, the multiplexer 806 and the multiplexer 808, and the multiplexer 804 selects the byte value PMINVAL<23:16> or PMINVAL<7:0> as the low byte MINVAL<7:0>. The byte value PMINVAL<23:16> or PMINVAL<7:0> represents the low byte of the smallest word found from the high-order and low-order parts. Multiplexer 806 selects the byte value PMINVAL<31:24> or PMINVAL<15:8> as the upper byte MINVAL<15:8>. PMINVAL<31:24> or PMINVAL<15:8> indicate the upper byte of the smallest word found from the high-order and low-order parts. Multiplexer 808 selects bits to set PMINLOC<3:2> or PMINLOC<1:0> as MINLOC<1:0>. Bit bits PMINLOC<3:2> or PMINLOC<1:0> indicate the least significant location bits of the high-order or low-order part. As mentioned above, the comparison circuit 802 can determine whether MINLOC or the most significant bit of MINLOC<2>. Therefore, MINLOC<2:0> indicates the location of the minimum word of the first bus ABUS.

While the invention has been described in detail for a number of preferred embodiments, other possible variations have also been considered. For example, all of the circuits described above may be implemented using any logic device or logic circuit. The functions of the above-mentioned logic circuit can also be implemented by software or firmware in an integrated device. The above circuit may have many inverting devices to provide positive logic or negative logic for any signal. The circuits disclosed in the present invention use digital codes or binary bytes or words, but the number of bits in digital codes or binary codes is not limited. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the appended claims.

Claims (19)

1. A system for executing one of a minimum level command and a sum of absolute error command utilizing a shared adder circuit, the system comprising: A plurality of digital codes. For the instruction of sum of absolute values of errors, these digital codes include a first set of digital codes and a second set of digital codes. For the horizontal minimum instruction, these digital codes include a plurality of pairs of digital codes , each digital code pair has a high digital code and a low digital code; A plurality of adders, each adder compares a first digital code with a second digital code to provide an absolute error value, a carry output and a transfer output; A summation circuit, summing up these absolute values of errors to provide a plurality of summed absolute values of errors; a comparison circuit, combining the carry outputs and the transfer outputs, to find a minimum digital code pair of the digital code pairs; and A path selection circuit, when executing the horizontal minimum instruction, the path selection circuit transmits each digital code pair of these digital code pairs to at least one adder pair of these adder pairs, so as to combine each digital code pair with Compared with other digital code pairs, when executing the error absolute value sum instruction, the path selection circuit sends the first digital code set and the second digital code set to these adder pairs to obtain the first digital code The absolute value of the error between each digital code of the set and each digital code of the second digital code set, the second digital code set has continuous digital codes. 2. The system according to claim 1, wherein the path selection circuit connects the first digital code set and the second digital code set to a first bus and a second bus when executing the absolute error sum command, They are respectively sent to a third bus and a fourth bus. When executing the horizontal minimum instruction, the path selection circuit sends these digital code pairs from the first bus to the third bus and the fourth bus. 3. The system as claimed in claim 1, wherein when executing the absolute sum of errors instruction, the routing circuit sends each digital code of the first digital code set to a first adder pair of the adders and sending each digital code of the second set of digital codes to a second adder of the first adder pair of the adders. 4. The system of claim 3, wherein the first adder of the first adder pair provides an absolute error value. 5. The system of claim 1, wherein the summing circuit comprises: a first adder for summing up a first error absolute value pair provided by a first adder pair of the adder pairs to provide a first total value; a second adder for summing up a second error absolute value pair provided by a second adder pair of the adder pairs to provide a second total value; A third adder, summing up the first total value and the second total value to provide a total error absolute value. 6. The system of claim 1, wherein each adder pair comprises: a high adder that compares a high digital code of a first digital code pair with a high digital code of a second digital code pair, the high adder providing these transfer outputs; and A low adder compares a low code of the first digital code pair with a low code of the second digital code pair. 7. The system as claimed in claim 1, wherein each digital code in the digital codes comprises an unsigned byte when executing the sum-of-absolute-errors instruction, and these digital codes include an unsigned byte when executing the horizontal minimum instruction. Each numeric code in the code includes an unsigned word. 8. The system of claim 1, wherein each of the transfer outputs indicates whether a carry input is incremented by a high adder of a pair of adders. 9. The system of claim 1, wherein the comparison circuit comprises: a first comparison circuit that combines the carry output and the transfer output of each of the adder pairs to generate a compare bit; and A second comparison circuit determines a minimum digital code pair of the digital code pairs according to the comparison bits. 10. The system of claim 9, wherein the first comparison circuit of each of the adder pairs has an AND gate and an OR gate, the AND gate combines a transfer output of a high adder with a A transfer output of the low adder is combined to generate a first bit, and the OR gate combines the first bit with a carry output of the high adder to provide a compare bit. 11. The system as claimed in claim 9, wherein the second comparison circuit decodes the comparison bits to provide a plurality of minimum bits, and each minimum bit represents whether each digital code pair of the digital code pairs is a minimum number Code pair. 12. The system of claim 9, further comprising: A memory for storing these digital code pairs, the second comparison circuit includes a decoding circuit, and the decoding circuit decodes these comparison bits to provide a plurality of minimum bits; A selection circuit, selects a digital code pair of these digital code pairs, and uses the selected digital code pair as a minimum digital code pair according to the minimum bits, and stores the minimum digital code pair in the memory; and A position circuit provides a position value according to the minimum bits, and the position value indicates the position of the minimum digital code pair in the memory. 13. A method of executing one of a minimum level command and a sum of absolute error command using a shared adder circuit, the method comprising: Receive a plurality of digital codes, these digital codes include a first digital code set and a second digital code set when executing the error sum absolute value instruction, these digital codes include a high digital code when executing the horizontal minimum instruction and a low-digit code; Provide a plurality of adders, each adder compares a first digital code with a second digital code to provide an absolute error value and a carry output; Aggregate these absolute values of errors to provide a sum of multiple absolute values of errors; sorting the adders into pairs of adders and providing a transfer output; Combining the carry outputs and the transfer outputs to obtain a minimum digital code pair of the digital code pairs; and When executing the horizontal minimum instruction, each digital code pair of these digital code pairs is sent to at least one adder pair of these adder pairs, in order to compare each digital code pair with other digital code pairs. During the error absolute value sum instruction, the first digital code set and the second digital code set are sent to these adder pairs, so as to obtain the difference between each digital code of the first digital code set and the second digital code set The absolute value of the error between each consecutive digital code. 14. The method according to claim 13, wherein when executing the instruction of the sum of absolute values of errors, further comprising: sending each digital code of the first digital code set to a first adder of a first adder pair of the adders; Each digital code of the second digital code set is sent to a second adder of the first adder pair of the adders. 15. The method of claim 13, wherein the summing step comprises: summing up a first error absolute value pair provided by a first adder pair of the adder pairs to generate a first summed value; summing a second pair of absolute values of errors provided by a second pair of adders of the pair of adders to generate a second summed value; and Summing up the first total value and the second total value to provide a total error absolute value. 16. The method of claim 13, wherein when executing the horizontal minimum instruction, the step of providing and sorting the adders comprises: Comparing a high digital code of a first digital code pair and a high digital code of a second digital code pair through a high adder of each adder pair to provide a first carry output and the transfer outputs; Through a low adder of each adder pair, a low digital code of the first digital code pair is compared with a low digital code of the second digital code pair to provide a second carry output. 17. The method of claim 13, wherein the combining step comprises: combining a first carry output and a second carry output of each of the adder pairs with one of the transfer outputs to provide a compare bit; and According to these comparison bits, a minimum digital code pair of these digital code pairs is obtained. 18. The method as claimed in claim 17, wherein the step of knowing the minimum digital code pair of these digital code pairs comprises: The comparison bits are decoded to provide a plurality of minimum bits, and each minimum bit represents whether the corresponding digital code pair is the minimum digital code pair. 19. The method of claim 18, further comprising: storing the digital code pairs in a memory; and According to these minimum bits, find out the position of the minimum digital code pair of these digital code pairs in the memory.

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