CN103346156B - Eeprom - Google Patents
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- CN103346156B CN103346156B CN201310270867.4A CN201310270867A CN103346156B CN 103346156 B CN103346156 B CN 103346156B CN 201310270867 A CN201310270867 A CN 201310270867A CN 103346156 B CN103346156 B CN 103346156B
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Abstract
The present invention discloses a kind of EEPROM, at least includes：Semiconductor substrate；The heavily doped source region of interval setting N-type and drain region and the channel region channel region are Wei Yu the source region and the drain region between in the Semiconductor substrate；First bit line and the second bit line, are connected to the source region and the drain region；First floating boom, is arranged above the channel region and the source region, the second floating boom, is arranged above the channel region and the drain region, and first floating boom and second floating boom respectively constitute the first storage bit unit and the second storage bit unit；First control gate and the second control gate, are respectively arranged above first floating boom and second floating boom；And wordline, above the channel region and Wei Yu the first floating boom and second floating boom between, by the present invention, it is to avoid a large amount of use word line voltage selecting switch, reduce the area of chip.
Description
Technical field
The present invention is with regard to a kind of semiconductor storage unit, more particularly to a kind of EEPROM
(EEPROM).
Background technology
In semiconductor storage, EEPROM (EEPROM) is a kind of volatile memory,
And belong to Erasable Programmable Read Only Memory EPROM (Erasable Programmable Read-Only Memory, EPROM).Electricity
The advantage of EPROM (EEPROM) is which can be wiped for whole memory block, and erasing speed
Hurry up, about need one to two second.Therefore, in recent years, EEPROM (EEPROM) has applied to various consumer
In electronic product, for example：Digital camera, digital code camera, mobile phone or notebook computer etc..
In general, EEPROM (EEPROM) point grid dividing structure or stacking gate structure or two kinds of knots
The combination of structure.Sub-gate EEPROM (EEPROM), due to its special structure, comparing stacking gate electricity can
EPROM (EEPROM) all embodies its unique performance advantage when programmed and erased, therefore divides grid
Formula structure is due to, the advantages of with high programming efficiency, the structure of wordline can avoid " cross and wipe ", applying particularly extensive.But
As sub-gate EEPROM (EEPROM) is with respect to stacking gate EEPROM
(EEPROM) how a wordline so that the area of chip can also increase, enters one while therefore how improving chip performance
It is problem demanding prompt solution that step reduces the size of chip.
The common practice for reducing chip size in prior art is to make two memory cell share a wordline.Fig. 1 is existing
There is the structural representation of a kind of EEPROM of shared word line (EEPROM) in technology.As shown in figure 1, existing
The EEPROM (EEPROM) for having technology includes：Semiconductor substrate 100, has on a semiconductor substrate 100
There are spaced source region 110 and drain region 120 and channel region 130, channel region 130 is located at source region 110 and leakage
Between polar region domain 120；First bit line BL0 and the second bit line BL1, is connected to source region 110 and drain region 120；The
One floating boom 310, is arranged at channel region 130 and 110 top of source region；Second floating boom 320, is arranged at channel region 130 and drain electrode
120 top of region, the first floating boom 310 and the second floating boom 320 respectively constitute the first storage bit unit and the second storage bit unit；The
One control gate CG0 and the second control gate CG1, is respectively arranged at the first floating boom 310 and 320 top of the second floating boom；Wordline WL, is located at
Above channel region 130 and Wei Yu the first floating boom 310 and the second floating boom 320 between.
During erasing, to selected cell Cell a, wordline WL of corresponding blocks connect high pressure 8V, control gate CG0/CG1 connect negative high voltage-
7V, so between wordline WL and the control gate, high pressure reaches 15V, and the high pressure between wordline WL and CG0, CG1 forms highfield, on floating boom
Electronics be pulled to WL, so as to remove the electronics on corresponding floating boom totally so as to form erasing, for unselected cells, wordline
WL=0V, without high pressure, will not occur floating boom electron transfer to wipe.During because wiping when wordline WL voltage and reading and programming not
With, therefore word line control voltage conversion needs high-voltage switch gear, and number of word lines is numerous and controls complexity, its high-voltage switch gear quantity is relatively
Greatly, shared area is also larger, is unfavorable for the design of chip.
Content of the invention
For overcoming the problem for causing chip area increase of above-mentioned prior art presence, present invention is primarily targeted at carrying
For a kind of EEPROM (EEPROM), which can avoid increasing a large amount of high-voltage switch gears in wordline WL, real
The purpose for saving chip area is showed.
For reaching above and other purpose, the invention provides a kind of EEPROM, at least includes：
Semiconductor substrate；
The heavily doped source region of interval setting N-type and drain region and the channel region channel region in the Semiconductor substrate
Between the source region and the drain region；
First bit line and the second bit line, are connected to the source region and the drain region；
First floating boom, is arranged above the channel region and the source region, the second floating boom, is arranged at the channel region and the leakage
Pole overlying regions, first floating boom and second floating boom respectively constitute the first storage bit unit and the second storage bit unit；
First control gate and the second control gate, are respectively arranged above first floating boom and second floating boom；And wordline,
Above the channel region and Wei Yu the first floating boom and second floating boom between.
Further, the Semiconductor substrate is N-type substrate.
Further, when erasing operation is carried out to the EEPROM, to selected cell, to the word
The voltage range that line applies is -1～-3V, and the voltage range applied by first bit line is 5～8V, and first control gate is applied
Plus voltage range be -5～-8V, second bit line and second control-grid voltage are 0.
Further, when erasing operation is carried out to the EEPROM, to unselected list of mutually going together
Unit, the voltage range applied by the wordline is -1～-3V, is -5～-8V to the voltage range that first control gate applies, and this
One bit line, second bit line and second control-grid voltage are 0.
Further, when erasing operation is carried out to the EEPROM, to same column different rows not
Selected cell, is 5～8V to the voltage range that first bit line applies, the word line voltage, second bit line, first control gate
And second control-grid voltage is 0.
Further, when operation is programmed to the EEPROM, to selected cell, to this
One control gate applied voltage scope is 5～9V, is 3～5V to the second control gate applied voltage scope, first bit line is applied
Making alive scope is 5～7V, and it is 1～5uA that second bit line applies current range, be 1 to the voltage range that the wordline applies～
2V.
Further, when operation is programmed to the EEPROM, to unselected cells of going together,
First control gate connects 5～9V voltage, and second control gate connects 3～5V voltage, and wordline WL connects 1～2V voltage, this first
Line and the second bit-line voltage are 0V.
Further, when operation is programmed to the EEPROM, unselected to same column different rows
Middle unit, the control gate, second control gate and the wordline all connect 0V voltage, the unselected cells to different rows different lines, should
First control gate, second control gate, the wordline, first bit line and second bit line all connect 0V voltage.
Further, when read operation is carried out to the EEPROM, to selected cell, first control
Grid processed connect 0V voltage, are 3～5V to the second control gate applied voltage scope, are 0.5 to the second bit line applied voltage scope
～2V, first bit line connect 0V voltage, and the voltage range applied by the wordline is 3～5V.
Further, when read operation is carried out to the EEPROM, to unselected cells of going together, should
First control gate meets 0V, and the second control gate applied voltage scope is 3～5V, and the voltage range applied by the wordline is 3～5V,
First bit line and second bit line hanging.
Further, when read operation is carried out to the EEPROM, unselected to same column different rows
Unit, first control gate, second control gate and the wordline connect 0V voltage, the unselected cells to different rows different lines, should
First control gate, the second control gate, the wordline, first bit line and second bit line all connect 0V voltage.
Compared with prior art, a kind of EEPROM of the present invention (EEPROM) is by partly leading in N-type
EEPROM is realized on body substrate, erasing operation is realized by applying applying negative high voltage on positive high voltage and CG0 in BL0, it is to avoid in word
Increase a large amount of high-voltage switch gears on line WL, it is achieved thereby that saving the purpose of chip area.
Description of the drawings
Fig. 1 is the structural representation of a kind of EEPROM of shared word line (EEPROM) in prior art
Figure；
Fig. 2 illustrates for a kind of EEPROM (EEPROM) cellular construction of present pre-ferred embodiments
Figure；
Fig. 3 is the group battle array circuit diagram of the EEPROM (EEPROM) of Fig. 2.
Specific embodiment
Below by way of specific instantiation and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understood further advantage and effect of the present invention by content disclosed in the present specification easily.The present invention also can be different by other
Instantiation implemented or applied, the every details in this specification also can based on different viewpoints and application, without departing substantially from
Various modifications and change is carried out under the spirit of the present invention.
Fig. 2 illustrates for a kind of EEPROM (EEPROM) cellular construction of present pre-ferred embodiments
Figure.As shown in Fig. 2 a kind of present invention EEPROM (EEPROM) unit, including：Semiconductor substrate 10,
In present pre-ferred embodiments, Semiconductor substrate 10 is N-type substrate, has spaced N-type heavy doping (N+) thereon
Source region 210 and drain region 220 and channel region 230；Channel region 230, positioned at source region 210 and drain region 220 it
Between；First bit line BL0 and the second bit line BL1, is connected to source region 210 and drain region 220；First floating boom 310, if
It is placed in channel region 230 and 210 top of source region；Second floating boom 320, is arranged at channel region 230 and 220 top of drain region,
First floating boom 310 and the second floating boom 320 respectively constitute the first storage bit unit and the second storage bit unit；First control gate CG0
With the second control gate CG1, the first floating boom 310 and 320 top of the second floating boom is respectively arranged at；Wordline WL, on channel region 230
Just and Wei Yu the first floating boom 310 and the second floating boom 320 between.
During erasing, it is -1～-3V to selected cell Cell a, word line voltage WL scope, in present pre-ferred embodiments
It is 5～8V that WL is -2V, bit line BL0 voltage range, and in present pre-ferred embodiments, BL0 meets high pressure 5.5V, control gate CG0 and connects
Negative high voltage, in the range from -5～-8V, in present pre-ferred embodiments, CG0 meets -6.5V, bit line BL1 and meets 0V, control gate CG1 and connects
Between 0V, so cell bit line BL0 and control gate CG0, high pressure reaches 12V, and this can form highfield, by the electricity on corresponding floating boom
Son is removed totally so as to form erasing；To unselected cells of mutually going together, wordline WL voltage is -2V, and control gate CG0 is -6.5V,
It is that 0V, bit line BL1 voltage keeps 0V that control gate CG1 is 0V, bit line BL0 voltage, and between control gate and wordline or bit line, high pressure is not
Foot causes generation electron transfer on floating boom not wipe；Unselected cells to same column different rows, word line voltage WL is
0V, bit line BL0 voltage is that 5.5V, bit line BL1 voltage keeps 0V, and control gate CG0/CG1 is 0V, bit line BL or wordline WL and control
Between grid CG0/CG1 processed, high pressure deficiency migrates electronics on floating boom, will not be wiped free of so as to its information；Different to different rows
The unselected cells of row, bit line BL0/BL1, wordline WL, control gate CG0/CG1 are 0V, corresponding floating boom Information invariability.Because of erasing
When bit line BL voltage different from when reading and programming, therefore the conversion of bit line BL control voltage is also required to high-voltage switch gear, but because bit line electricity
Pressure is accomplished by switching to switch originally, meets erasing demand, therefore bit line connects high pressure increase relatively in wordline its parameter is adjusted by
On-off ratio relatively saves area, so as to reduce EEPROM area.
When operation is programmed to the EEPROM, to selected cell, control gate CG0 applies electricity
Pressure scope is 5～9V, and in present pre-ferred embodiments, CG0 connects 8V, CG1 applied voltage scope for 3～5V, preferable in the present invention
In embodiment, CG1 connects 5V, BL0 applied voltage scope for 5～7V, and in present pre-ferred embodiments, BL0 meets 5.5V, and BL1 is applied
Plus current range is 1～5uA, the voltage range applied by wordline WL is [1～2V], and in present pre-ferred embodiments, WL connects
1.5V, the high pressure for now having electric current flowing, CG0 in channel region 230 allow part thermoelectron be injected into floating boom, so as to realize writing
Enter；To unselected cells of going together, control gate CG0 meets 8V, control gate CG1 and meets 5V, and wordline WL meets 1.5V, but bit line BL0/BL1
For 0V, therefore no current is flowed in channel region 230, is not had electron transfer phenomenon and will not be write；Different to same column
Row unselected cells, control gate CG0/CG1 and wordline WL meet 0V, will not form raceway groove in channel region 230, even if bit line
The information that BL0 has voltage, this unit will not produce impact to electric current on this bit line；Unselected cells to different rows different lines,
Control gate CG0/CG1, wordline WL, bit line BL0/BL1 all meet 0V, and selected cell is not affected.
When read operation is carried out to the EEPROM, to selected cell, control gate CG0 meets 0V, CG1
Applied voltage scope is 3～5V, and in present pre-ferred embodiments, CG1 connects 4.5V, BL1 applied voltage scope for 0.5～2V,
In present pre-ferred embodiments, BL1 meets 0.8V, and BL0 meets 0V, and the voltage range applied by wordline WL is [3～5V], at this
In bright preferred embodiment, WL meets 4.5V, now has electric current flowing in channel region 230, under the high pressure effect of CG1 and WL,
Formed by the electronically controlled raceway groove on floating boom 310 in channel region 230, and corresponding current is formed on bit line BL1, through reading
Amplifier and subsequent conditioning circuit obtain previously written information after processing；To unselected cells of going together, control gate CG0 meets 0V, control
Grid CG1 meets 4.5V, and wordline WL meets 4.5V, but bit line BL0/BL1 is hanging, therefore no current is flowed in channel region 230, will not
Reading on selected cell produces impact；To same column different rows unselected cells, control gate CG0/CG1 and wordline WL meet 0V,
Raceway groove will not be formed in channel region 230, even if bit line BL0/BL1 has voltage, the information of this unit will not be to selecting on this bit line
The current generated generation impact of middle unit；Unselected cells to different rows different lines, control gate CG0/CG1, wordline WL, position
Line BL0/BL1 all meets 0V, and selected cell is read not to be affected.
Fig. 3 is the group battle array circuit diagram of the EEPROM (EEPROM) of Fig. 2.As shown in figure 3, per
The control gate CG0 of the memory cell of a line links together, and the control gate CG1 of the memory cell per a line links together, per
Wordline WL of the memory cell of a line links together, and the bit line BL0 of each row links together, and the BL1 per a line is connected to
Together, select each unit to carry out reading by ranks decoding circuit (in figure is not drawn into), programming and erasing operation, bit line output connects reading
Go out amplifier (in figure is not drawn into).
In sum, a kind of EEPROM of the present invention (EEPROM) passes through in N-type semiconductor substrate
On realize EEPROM, by applying to apply negative high voltage on positive high voltage and CG0 to realize erasing operation in BL0, it is to avoid in wordline WL
Increase a large amount of high-voltage switch gears, it is achieved thereby that saving the purpose of chip area.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any
Skilled person all can be modified to above-described embodiment and is changed without prejudice under the spirit and the scope of the present invention.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (9)
1. a kind of EEPROM, at least includes：
Semiconductor substrate；The Semiconductor substrate is N-type substrate；
The heavily doped source region of interval setting N-type and drain region and channel region in the Semiconductor substrate, the raceway groove position
Between the source region and the drain region；
First bit line and the second bit line, are connected to the source region and the drain region；
First floating boom, is arranged above the channel region and the source region, the second floating boom, is arranged at the channel region and the drain region
Above domain, first floating boom and second floating boom respectively constitute the first storage bit unit and the second storage bit unit；
First control gate and the second control gate, are respectively arranged above first floating boom and second floating boom；And wordline, it is located at
Above the channel region and Wei Yu the first floating boom and second floating boom between；
Apply positive high voltage and apply negative high voltage in first control gate to realize to electrically erasable by the first bit line in N-type substrate
The operation wiped by programmable read only memory；When erasing operation is carried out to the EEPROM, right
Selected cell, the voltage range applied by the wordline is -1～-3V, and the voltage range applied by first bit line is 5～8V, right
The voltage range that first control gate applies is -5～-8V, and second bit line is 0 with second control-grid voltage.
2. a kind of EEPROM as claimed in claim 1, it is characterised in that：To the electric erasable and programmable
When journey read-only storage carries out erasing operation, to unselected cells of mutually going together, be -1 to the voltage range that the wordline applies～-
3V, is -5～-8V to the voltage range that first control gate applies, first bit line, second bit line and second control gate
Voltage is 0.
3. a kind of EEPROM as claimed in claim 1, it is characterised in that：To the electric erasable and programmable
When journey read-only storage carries out erasing operation, unselected cells to same column different rows, the voltage model applied by first bit line
Enclose for 5～8V, the word line voltage, second bit line, first control gate and second control-grid voltage are 0.
4. a kind of EEPROM as claimed in claim 1, it is characterised in that：Can to the electrically erasable
When program read-only memory is programmed operation, to selected cell, it is 5～9V to the first control gate applied voltage scope, right
The second control gate applied voltage scope is 3～5V, is 5～7V to the first bit line applied voltage scope, and second bit line is applied
Plus current range is 1～5uA, it is 1～2V to the voltage range that the wordline applies.
5. a kind of EEPROM as claimed in claim 1, it is characterised in that：To the electric erasable and programmable
When journey read-only storage is programmed operation, to unselected cells of going together, first control gate connects 5～9V voltage, second control
Grid processed connect 3～5V voltage, and wordline WL connects 1～2V voltage, and first bit line and the second bit-line voltage are 0V.
6. a kind of EEPROM as claimed in claim 1, it is characterised in that：To the electric erasable and programmable
When journey read-only storage is programmed operation, to same column different rows unselected cells, the control gate, second control gate and the word
Line all connects 0V voltage, the unselected cells to different rows different lines, first control gate, second control gate, the wordline, this
One bit line and second bit line all connect 0V voltage.
7. a kind of EEPROM as claimed in claim 1, it is characterised in that：To the electric erasable and programmable
When journey read-only storage carries out read operation, to selected cell, first control gate connects 0V voltage, applies electricity to second control gate
Pressure scope is 3～5V, is 0.5～2V to the second bit line applied voltage scope, and first bit line connects 0V voltage, the wordline is applied
Plus voltage range be 3～5V.
8. a kind of EEPROM as claimed in claim 1, it is characterised in that：To the electric erasable and programmable
When journey read-only storage carries out read operation, to unselected cells of going together, first control gate meets 0V, and second control gate applies electricity
Pressure scope is 3～5V, and the voltage range applied by the wordline is 3～5V, and first bit line and second bit line are hanging.
9. a kind of EEPROM as claimed in claim 1, it is characterised in that：To the electric erasable and programmable
When journey read-only storage carries out read operation, to same column different rows unselected cells, first control gate, second control gate and should
Wordline connects 0V voltage, the unselected cells to different rows different lines, first control gate, the second control gate, the wordline, this first
Bit line and second bit line all connect 0V voltage.
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| CN201310270867.4A CN103346156B (en) | 2013-06-28 | 2013-06-28 | Eeprom |
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| CN103346156B true CN103346156B (en) | 2017-03-08 |
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Families Citing this family (2)
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| CN103839587A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Electric erasable programmable read-only memory and operating method |
| CN112185965B (en) * | 2020-11-12 | 2023-11-10 | 上海华虹宏力半导体制造有限公司 | Mask read-only memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1373517A (en) * | 2001-03-06 | 2002-10-09 | 力旺电子股份有限公司 | Embedded flash memory and its operating method |
| US6605840B1 (en) * | 2002-02-07 | 2003-08-12 | Ching-Yuan Wu | Scalable multi-bit flash memory cell and its memory array |
| CN101859775A (en) * | 2009-04-07 | 2010-10-13 | 北京芯技佳易微电子科技有限公司 | Non-volatile memorizer and manufacturing, programming and reading method thereof |
-
2013
- 2013-06-28 CN CN201310270867.4A patent/CN103346156B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1373517A (en) * | 2001-03-06 | 2002-10-09 | 力旺电子股份有限公司 | Embedded flash memory and its operating method |
| US6605840B1 (en) * | 2002-02-07 | 2003-08-12 | Ching-Yuan Wu | Scalable multi-bit flash memory cell and its memory array |
| CN101859775A (en) * | 2009-04-07 | 2010-10-13 | 北京芯技佳易微电子科技有限公司 | Non-volatile memorizer and manufacturing, programming and reading method thereof |
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