CN103337257B - NAND flash memory equipment and operation method thereof - Google Patents
NAND flash memory equipment and operation method thereof Download PDFInfo
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- CN103337257B CN103337257B CN201310247465.2A CN201310247465A CN103337257B CN 103337257 B CN103337257 B CN 103337257B CN 201310247465 A CN201310247465 A CN 201310247465A CN 103337257 B CN103337257 B CN 103337257B
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- 230000015654 memory Effects 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 7
- 238000004364 calculation method Methods 0.000 claims description 21
- 230000005540 biological transmission Effects 0.000 claims description 9
- 238000012937 correction Methods 0.000 claims description 9
- 238000001514 detection method Methods 0.000 claims description 9
- 238000011017 operating method Methods 0.000 claims description 8
- 230000005611 electricity Effects 0.000 claims description 3
- 238000013461 design Methods 0.000 abstract description 2
- 238000013500 data storage Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 2
- 210000003205 muscle Anatomy 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
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- 238000012546 transfer Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
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- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention belongs to the field of a structural design of an NAND flash memory and provides NAND flash memory equipment and an operation method thereof. The NAND flash memory equipment and the operation method thereof dynamically adjust actual working voltage of an NAND flash memory chip according to erasing times of the NAND flash memory chip to enable the actual working voltage of the corresponding NAND flash memory chip to have a high value in an allowed range, so as to guarantee the reliable work of the NAND flash memory chip and improve execution speeds of erasing operation and writing-in operation; and therefore, the NAND flash memory chip has the high performance in the process of executing the erasing operation and the writing-in operation and the use experience of a user is improved.
Description
Technical field
The invention belongs to the field of structural design of nand flash memory, more particularly to a kind of NAND flash memory equipment and its operation side
Method.
Background technology
With the progress of semiconductor technology, the price of NAND flash memory equipment declines steadily, and its application field is also opened up
Exhibition.
Well known, each memory cell in nand flash memory chip uses floating transistor in structure, to nand flash memory core
The operation of piece can be erasing operation, write operation or read operation, by the charge/discharge to floating grid, realize depositing for data
Storage/release, and then realize the write/erase of data in nand flash memory chip.In detail, each nand flash memory chip includes certain
The block of number, each block is divided into the page of certain amount again, and the erasing to data in nand flash memory chip is carried out in units of block
, write-in and reading to data in nand flash memory chip are carried out in units of page, and necessary before write operation is performed
First carry out erasing operation.
Conventionally, as the write operation and erasing operation to nand flash memory chip are related to floating transistor
Charge/discharge, and nand flash memory chip is operated under rated operational voltage, therefore it is remote to perform the speed of write operation and erasing operation
It is slower than performing read operation, so as to have impact on the performance of nand flash memory chip, reduce the experience property that user uses.For example,
It is the multi-level cell memory of 4K bytes for a kind of typical, every page data size（Multi-level Cell,MLC）, its wiping
The execution time of division operation is 3000 microseconds, and the execution time of its write operation is 1300 microseconds, and during the execution of read operation
Between be only 25 microseconds.Especially for write operation, can only be gone here and there because write-in, erasing and the operation read are unable to executed in parallel
Row is performed, therefore the execution speed of write operation turns into the bottleneck for restricting nand flash memory chip storage performance.
The content of the invention
It is an object of the invention to provide a kind of NAND flash memory equipment, it is intended to solve existing nand flash memory chip due to writing
Enter operation and erasing operation is related to the charge/discharge of floating transistor, and nand flash memory chip to be operated under rated operational voltage, because
The speed of this write operation and erasing operation is slow, influences the performance of nand flash memory chip and reduces asking for the experience property that user uses
Topic.
The present invention is achieved in that a kind of NAND flash memory equipment, and the NAND flash memory equipment includes at least one by extremely
The flash memory set that a few nand flash memory chip is constituted, the nand flash memory controller being connected with the flash memory set, and to described
Nand flash memory chip exports the voltage regulator circuit of real work voltage, and the nand flash memory controller includes：
Governor circuit, for the erasing instruction to the nand flash memory chip transmission block；
At least one counter, for after the erasing instruction of the governor circuit transmission block, according to the governor circuit
Counting instruction the erasing times of relevant block are counted, the average of erasing times is obtained according to count results statistics afterwards
Value；
At least one voltage dynamic calculation unit, for the erasing time obtained according to the corresponding counters count
Several average value, lookup obtain the erasing times the corresponding nand flash memory chip of average value real work voltage, and to
The voltage regulator circuit exports corresponding control signal, the voltage regulator circuit to the output of corresponding nand flash memory chip with
The corresponding real work voltage of the control signal.
Another object of the present invention is to provide a kind of operating method of NAND flash memory equipment as described above, methods described
Including：
Erasing instruction from governor circuit to the nand flash memory chip transmission block in flash memory set；
After the erasing instruction that the governor circuit sends described piece, counter is instructed according to the counting of the governor circuit
Erasing times to relevant block are counted, and obtain the average value of erasing times according to count results statistics afterwards；
The average value of the erasing times that voltage dynamic calculation unit is obtained according to the corresponding counters count, looks into
The real work voltage of the corresponding nand flash memory chip of average value of the erasing times is found, and it is defeated to voltage regulator circuit
Go out corresponding control signal；
The voltage regulator circuit exports corresponding actual work according to the control signal to corresponding nand flash memory chip
Make voltage.
NAND flash memory equipment proposed by the present invention and its operating method are dynamic according to nand flash memory chip erasing times
The real work voltage of nand flash memory chip is adjusted, may be such that the real work voltage of corresponding nand flash memory chip in the model for allowing
There is high value, so as to while nand flash memory chip reliably working is ensured, improve erasing operation and write operation in enclosing
Perform speed so that nand flash memory chip, with performance higher, improves user when erasing operation and write operation is performed
The experience property for using.
Brief description of the drawings
Fig. 1 is the structure chart of the NAND flash memory equipment that first embodiment of the invention is provided；
Fig. 2 is the structure chart of the NAND flash memory equipment that second embodiment of the invention is provided；
Fig. 3 is the flow chart of the NAND flash memory equipment that third embodiment of the invention is provided；
During Fig. 4 is third embodiment of the invention, voltage dynamic calculation unit is searched and obtains real work voltage and export control
The flow chart of signal processed.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
It is slow in order to solve the problems, such as existing NAND flash memory equipment execution write/erase service speed, from semiconductor technology angle
Degree sees, can improve charge/discharge speed by improving the real work voltage of floating transistor, therefore, it is proposed by the present invention
NAND flash memory equipment is the real work voltage that dynamic adjusts nand flash memory chip according to nand flash memory chip erasing times.
Fig. 1 shows the structure of the NAND flash memory equipment that first embodiment of the invention is provided, and for convenience of description, only shows
The part related to first embodiment of the invention.
In detail, the NAND flash memory equipment that first embodiment of the invention is provided includes that at least one is dodged by least one NAND
Deposit the flash memory set 2 of chip composition, the nand flash memory controller 1 being connected with flash memory set 2, and to each nand flash memory in flash memory set 2
Chip exports the voltage regulator circuit 3 of real work voltage.Wherein, nand flash memory controller 1 includes：Governor circuit 11, is used for
To the erasing instruction of the nand flash memory chip transmission block in flash memory set 2；At least one counter 12, for being sent out in governor circuit 11
After sending the erasing instruction of block, the counting instruction according to governor circuit 11 is counted to the erasing times of relevant block, afterwards basis
Count results statistics obtains the average value of erasing times；At least one voltage connected one to one respectively with each counter 12
Dynamic calculation unit 13, the average value for counting the erasing times for obtaining according to corresponding counter 12, lookup obtains the wiping
Except the real work voltage of the corresponding nand flash memory chip of the average value of number of times, and corresponding control is exported to voltage regulator circuit 3
Signal processed, voltage regulator circuit 3 exports real work voltage corresponding with the control signal to corresponding nand flash memory chip.
In first embodiment of the invention, voltage regulator circuit 3 can include at least one voltage control chip；At least one
Counter 12 can be respectively at least one counter corresponding with each nand flash memory chip, or respectively with each sudden strain of a muscle
2 corresponding at least one counters of group are deposited, be can also be and 2 corresponding counters of whole flash memory sets.If at least one meter
Number devices 12 are at least one counters corresponding with each nand flash memory chip respectively, then counter 12 counts the erasing time for obtaining
Several average value is the average value of each piece in corresponding nand flash memory chip of erasing times, and corresponding voltage dynamic calculation unit
The control signal of 13 outputs is the real work voltage for adjusting corresponding nand flash memory chip；At least one counter 12 is point
At least one counter not corresponding with each flash memory set 2, then the average value that counter 12 counts the erasing times for obtaining is phase
Answering the average value of each piece in flash memory set 2 of erasing times, and the control signal of corresponding voltage dynamic calculation unit 13 output is
It is used to adjust the real work voltage of each nand flash memory chip in corresponding flash memory set 2；If at least one counter 12 is and whole
2 corresponding counters of flash memory set, then it is each in whole flash memory sets 2 that counter 12 counts the average value of erasing times for obtaining
The average value of the erasing times of block, and the control signal of corresponding voltage dynamic calculation unit 13 output is to adjust whole sudden strains of a muscle
Deposit the real work voltage of each nand flash memory chip in group 2.
Assuming that the difference of the real work voltage of nand flash memory chip and rated operational voltage is Δ Vpp, erasing times it is flat
Average is N, then have：ΔVpp=μ*λN, wherein, μ and λ is constant and λ ＜ 1.Requirement according to nand flash memory chip is, it is necessary to Δ
Vpp is no more than the 10% of rated operational voltage, for example, being the nand flash memory chip of 3.3v, its Δ Vpp for rated operational voltage
It is the nand flash memory chip of 1.8v for rated operational voltage no more than 0.3v, its Δ Vpp is no more than 0.15v.Accordingly, this hair
In bright first embodiment, voltage dynamic calculation unit 13 is previously stored with a contingency table, and the contingency table is characterized when μ and λ are certain
When, the corresponding relation between the value range of erasing times and the real work voltage of nand flash memory chip, voltage dynamic calculation list
First 13 in the case of the average value of known erasing times, by searching the contingency table, you can obtains corresponding real work electricity
Pressure.If being the nand flash memory core of 3.3v for rated operational voltage for example, the average value of erasing times is to the maximum 3000 times
Piece, can be by editor's contingency table in advance so that：When the value range of erasing times is 0-500 times, corresponding real work voltage
It is 3.6v, when the value range of erasing times is 500-1000 times, corresponding real work voltage is 3.45v or 3.5v, erasing time
When several value ranges is 1000-1500 times, corresponding real work voltage is 3.4v, and the value range of erasing times is 1500-
At 2500 times, corresponding real work voltage is 3.35v, when the value range of erasing times is 2500 times and the above, corresponding reality
Border operating voltage is 3.3v.
The NAND flash memory equipment that first embodiment of the invention is proposed is that dynamic is adjusted according to nand flash memory chip erasing times
The real work voltage of whole nand flash memory chip, may be such that the real work voltage of corresponding nand flash memory chip in the scope for allowing
It is interior with high value, so as to while nand flash memory chip reliably working is ensured, improve holding for erasing operation and write operation
Scanning frequency degree so that when erasing operation and write operation is performed with performance higher, improve user makes nand flash memory chip
Experience property.
Due in practice, with the raising of the real work voltage of nand flash memory chip, nand flash memory chip is being performed
During write operation, the error rate of data storage is also improved therewith, therefore, second embodiment of the invention proposes a kind of nand flash memory
Equipment, as shown in Fig. 2 for convenience of description, illustrate only the part related to second embodiment of the invention.
Different from first embodiment, in a second embodiment, nand flash memory controller 1 also includes：At least one mistake inspection
Unit 14 is surveyed and corrects, for using a certain algorithm（Such as ECC algorithm etc.）, to performing the corresponding of write operation and read operation
Nand flash memory chip carries out data detection and correction, so as to ensure that the integrality of data transfer.
In second embodiment of the invention, according to data throughput and error detection and correction ability, at least one mistake inspection
It can be at least one error detection and correction unit 14 corresponding with each flash memory set 2 respectively to survey and correct unit 14, it is also possible to
It is at least one error detection and correction unit 14 corresponding with multiple flash memory sets 2 respectively.
The NAND flash memory equipment that second embodiment of the invention is proposed utilizes error detection and correction unit 14, it is to avoid NAND
Flash chip causes the raising of the error rate of data storage due to the raising of real work voltage, so as to improve nand flash memory
While the execution speed of chip erasing operation, data when data perform read operation and write operation are also further ensured
Integrality, the experience property that the performance and user for further improving nand flash memory chip are used.
Fig. 3 shows the operating method stream of the NAND flash memory equipment shown in Fig. 1 or Fig. 2 of third embodiment of the invention offer
Journey.
In detail, the operating method bag of the NAND flash memory equipment shown in Fig. 1 or Fig. 2 of third embodiment of the invention offer
Include：
Step S1：Erasing instruction from governor circuit to the nand flash memory chip transmission block in flash memory set.
Step S2：After the erasing instruction of governor circuit transmission block, counter is instructed to phase according to the counting of governor circuit
Answer the erasing times of block to be counted, obtain the average value of erasing times according to count results statistics afterwards.
Step S3：The average value of the erasing times that voltage dynamic calculation unit is obtained according to corresponding counters count, looks into
The real work voltage of the corresponding nand flash memory chip of average value of the erasing times is found, and is exported to voltage regulator circuit
Corresponding control signal.
Further, as shown in figure 4, step S3 may include：
Step S31：Voltage dynamic calculation unit searches the contingency table that prestores, obtains being obtained with corresponding counters count
The corresponding real work voltage of average value of erasing times.
In third embodiment of the invention, contingency table characterizes the value range of erasing times and the actual work of nand flash memory chip
Make the corresponding relation between voltage.
Step S32：Voltage dynamic calculation unit exports phase according to the real work voltage for finding to voltage regulator circuit
The control signal answered.
Step S4：Voltage regulator circuit exports corresponding actual work according to control signal to corresponding nand flash memory chip
Make voltage.
In sum, NAND flash memory equipment proposed by the present invention and its operating method are according to nand flash memory chip erasing time
Count and the dynamic real work voltage for adjusting nand flash memory chip, may be such that the real work voltage of corresponding nand flash memory chip exists
There is high value, so as to while nand flash memory chip reliably working is ensured, improve erasing operation and write in the range of permission
Enter the execution speed of operation so that nand flash memory chip, with performance higher, is carried when erasing operation and write operation is performed
The experience property that user uses is risen.In addition, in NAND flash memory equipment proposed by the present invention, can also be set in nand flash memory controller
Error detection and correction unit is put, with the data integrity during ensureing write operation and read operation, is reduced due to reality
The error rate that operating voltage is improved and caused.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Any modification, equivalent and improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of NAND flash memory equipment, it is characterised in that the NAND flash memory equipment includes at least one by least one NAND
The flash memory set that flash chip is constituted, the nand flash memory controller being connected with the flash memory set, and to the nand flash memory chip
The voltage regulator circuit of real work voltage is exported, the nand flash memory controller includes：
Governor circuit, for the erasing instruction to the nand flash memory chip transmission block；
At least one counter, for after the erasing instruction of the governor circuit transmission block, according to the meter of the governor circuit
Number instruction is counted to the erasing times of relevant block, obtains the average value of erasing times according to count results statistics afterwards；
At least one voltage dynamic calculation unit, for the erasing times that are obtained according to the corresponding counters count
Average value, lookup obtains the real work voltage of the corresponding nand flash memory chip of average value of the erasing times, and to described
Voltage regulator circuit exports corresponding control signal, the voltage regulator circuit to corresponding nand flash memory chip export with it is described
The corresponding real work voltage of control signal；
, with the increase of the average value of erasing times, its value is from higher than rated operational voltage to being reduced to for the real work voltage
Equal to rated operational voltage.
2. NAND flash memory equipment as claimed in claim 1, it is characterised in that at least one counter be respectively with it is each
Corresponding at least one counter of the nand flash memory chip, the average value of the erasing times that the counters count is obtained
It is the average value of each piece in corresponding nand flash memory chip of erasing times, and the corresponding voltage dynamic calculation unit output
The control signal is the real work voltage for adjusting the corresponding nand flash memory chip.
3. NAND flash memory equipment as claimed in claim 1, it is characterised in that at least one counter be respectively with it is each
Corresponding at least one counter of the flash memory set, the average value of the erasing times that the counters count is obtained is corresponding
The average value of each piece of erasing times in flash memory set, and the control signal that the corresponding voltage dynamic calculation unit is exported
It is the real work voltage for adjusting each nand flash memory chip in the corresponding flash memory set.
4. NAND flash memory equipment as claimed in claim 1, it is characterised in that at least one counter is and whole flash memories
The corresponding counter of group, during the average value of the erasing times that the counters count is obtained is whole flash memory sets
The average value of each piece of erasing times, and the control signal of the corresponding voltage dynamic calculation unit output is to adjust
The real work voltage of each nand flash memory chip in whole whole flash memory sets.
5. NAND flash memory equipment as claimed in claim 1, it is characterised in that the voltage regulator circuit includes at least one electricity
Pressure control chip.
6. NAND flash memory equipment as claimed in claim 1, it is characterised in that at least one voltage dynamic calculation unit point
Do not connected one to one with each counter.
7. NAND flash memory equipment as claimed in claim 1, it is characterised in that the nand flash memory controller also includes：
At least one error detection and correction unit, for using a certain algorithm, the phase to performing write operation and read operation
Answering nand flash memory chip carries out data detection and correction.
8. NAND flash memory equipment as claimed in claim 7, it is characterised in that at least one error detection and correction unit
It is corresponding with each flash memory set respectively or corresponding with multiple flash memory sets respectively.
9. a kind of operating method of NAND flash memory equipment as described in any one of claim 1 to 8, it is characterised in that the side
Method includes：
Erasing instruction from governor circuit to the nand flash memory chip transmission block in flash memory set；
After the erasing instruction that the governor circuit sends described piece, counter is instructed to phase according to the counting of the governor circuit
Answer the erasing times of block to be counted, obtain the average value of erasing times according to count results statistics afterwards；
The average value of the erasing times that voltage dynamic calculation unit is obtained according to the corresponding counters count, searches
To the real work voltage of the corresponding nand flash memory chip of average value of the erasing times, and phase is exported to voltage regulator circuit
The control signal answered；
The voltage regulator circuit exports corresponding real work electricity according to the control signal to corresponding nand flash memory chip
Pressure.
10. the operating method of NAND flash memory equipment as claimed in claim 9, it is characterised in that the voltage dynamic calculation list
The average value of the erasing times that unit obtains according to the corresponding counters count, lookup obtains the flat of the erasing times
The real work voltage of the corresponding nand flash memory chip of average, and to voltage regulator circuit export corresponding control signal the step of
Including：
Voltage dynamic calculation unit searches the contingency table for prestoring, and obtains the erasing obtained with the corresponding counters count
The corresponding real work voltage of average value of number of times, the contingency table characterizes the value range and nand flash memory chip of erasing times
Real work voltage between corresponding relation；
Voltage dynamic calculation unit is controlled according to the real work voltage for finding to voltage regulator circuit output is corresponding
Signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310247465.2A CN103337257B (en) | 2013-06-20 | 2013-06-20 | NAND flash memory equipment and operation method thereof |
| PCT/CN2014/070544 WO2014201864A1 (en) | 2013-06-20 | 2014-01-13 | Nand flash memory device and operation method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310247465.2A CN103337257B (en) | 2013-06-20 | 2013-06-20 | NAND flash memory equipment and operation method thereof |
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| CN103337257B true CN103337257B (en) | 2017-05-24 |
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| CN103337257B (en) * | 2013-06-20 | 2017-05-24 | 深圳市瑞耐斯技术有限公司 | NAND flash memory equipment and operation method thereof |
| CN105242871B (en) * | 2014-06-06 | 2018-06-05 | 华为技术有限公司 | A kind of method for writing data and device |
| CN105302474B (en) * | 2014-07-31 | 2018-03-16 | 华为技术有限公司 | Control the method for write operation and the controller of flash memory of flash memory |
| KR20160112450A (en) * | 2015-03-19 | 2016-09-28 | 에스케이하이닉스 주식회사 | Non-volatile memory device, operating method thereof, and test system having non-volatile memory device |
| CN105788637A (en) * | 2015-12-24 | 2016-07-20 | 北京兆易创新科技股份有限公司 | Erasing and writing recession compensation method and device for NAND FLASH |
| CN106205714A (en) * | 2016-06-29 | 2016-12-07 | 联想(北京)有限公司 | A kind of data processing method, storage device, electronic equipment |
| US10229740B2 (en) * | 2016-10-17 | 2019-03-12 | SK Hynix Inc. | Memory system of 3D NAND flash and operating method thereof |
| CN109308161B (en) * | 2017-07-26 | 2022-04-01 | 北京兆易创新科技股份有限公司 | Parameter adjusting device, method and equipment for flash memory |
| CN108647111B (en) * | 2018-05-14 | 2021-06-11 | 联芸科技（杭州）有限公司 | Read control device and read control method for memory and memory controller |
| CN111273864B (en) * | 2020-01-17 | 2023-08-08 | 山东浪潮科学研究院有限公司 | Method and system for reducing NAND FLASH erasing times |
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| CN102937935A (en) * | 2012-09-04 | 2013-02-20 | 邹粤林 | Solid state storage system, controller and method for prolonging service life of flash memory chips |
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| WO2014201864A1 (en) | 2014-12-24 |
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