CN103325773A - Package structure of integrated circuit - Google Patents

Abstract

The present invention relates to an integrated circuit packaging structure, comprising: a first chip unit; a second chip unit, which is tightly combined with the first chip unit, the second chip unit having at least one semiconductor layer and at least one metal layer, and the second chip unit having a plurality of apertures penetrating the semiconductor layer and the metal layer; wherein each aperture penetrates the second chip unit respectively, and the first chip unit is electrically connected to an input-output junction element. The integrated circuit packaging structure provided by the present invention tests the first chip unit via the input-output junction element, and the first chip unit can be directly cut into a plurality of crystal grains without going through a general packaging procedure, thereby effectively reducing the packaging test cost and reducing the area size of the chip after packaging.

Description

Package structure of integrated circuit

technical field

The invention relates to a packaging structure of an integrated circuit, in particular to a packaging structure of an integrated circuit with a chip unit as a substrate.

Background technique

The current method of chip packaging is roughly described as follows: after cutting according to the arrangement positions of multiple dies on a wafer (Wafer), each die is mounted on a corresponding lead frame (Lead frame) or It is on a substrate (Substrate), so that a plurality of conductive pins (Pin) in the die are electrically connected to the lead frame or the substrate, and receive a set of test voltage signals for chip testing.

In addition, based on the further observation of the bonding method between the die and the substrate in today's packaging technology, it can be roughly divided into wire bond (WB), automatic pressure bonding (Tape automatic bonding, TAB), flip-chip ( Flip chip, FC) packaging methods, if viewed from the substrate pin type, can be roughly divided into pin-through-hole (PTH), surface mount technology (SMT), peripheral type ( Peripheral package) and array type (Array area), etc. However, as electronic products continue to evolve toward lighter, thinner, shorter, and smaller trends, chip packaging technology has gradually changed from the early wire bonding type to the flip chip type. Mainly, and the pin type of the substrate is also changed from pin insertion type to array type (such as: ball grid array package (Ball Grid Array, BGA).

For example, a flip-chip ball grid array package (FC BGA) is shown in Figure 1, a die 910 is connected to a substrate 920 by a plurality of solder balls 991, and the solder balls 991 are connected to the tin-lead alloy material The substrate pin 992 is effectively electrically connected, and FIG. 2 shows a wire bond BGA package (Wire bond BGA), wherein the die 810 is connected to the substrate 820 by a metal wire 892 .

From the above-mentioned chip packaging technologies, no matter which one must use a substrate (or a lead frame) as a device for carrying the die, and the die and the substrate must be connected by solder balls or metal wires. One of the mainstream methods of chip packaging technology at present.

Contents of the invention

In view of this, the object of the present invention is to provide a packaging structure for integrated circuits.

In order to achieve the above object, the present invention provides a package structure of an integrated circuit, the package structure of the integrated circuit includes:

a first chip unit; and

A second chip unit, which is electrically connected to the first chip unit, the second chip unit has at least one semiconductor layer and at least one metal layer, and the second chip unit has a plurality of Apertures of the layer; wherein, each aperture respectively penetrates the second chip unit, and the first chip unit is electrically connected to an input-output joint element.

As a preferred solution, the second chip unit further has a bonding metal layer, and the bonding metal layer is fabricated into a plurality of input and output bonding elements according to a semiconductor process.

As a preferred solution, the packaging structure of the integrated circuit further includes a bonding layer unit, and the bonding layer unit is fabricated into a plurality of input and output bonding elements according to semiconductor technology.

As a preferred solution, wherein the first chip unit, the second chip unit and the bonding layer unit are packaged into an integrated circuit module.

As a preferred solution, the area of the second chip unit is larger than the area of the first chip unit.

As a preferred solution, the area of the second chip unit is equal to the area of the first chip unit.

As a preferred solution, the first chip unit and the second chip unit are packaged into an integrated circuit module.

As a preferred solution, the material of the semiconductor layer is silicon.

As a preferred solution, the material of the semiconductor layer is gallium arsenide.

In the packaging structure of the integrated circuit provided by the present invention, the first chip unit is tested through the I/O bonding element, and the first chip unit can be directly cut into a plurality of crystal grains without going through a general packaging procedure. Therefore, It can effectively reduce the packaging and testing cost and reduce the size of the packaged chip area.

Description of drawings

FIG. 1 is a schematic side view of a flip-chip solder ball array package in the prior art;

FIG. 2 is a schematic side view of a wire-bonded ball grid array package in the prior art;

Fig. 3 is a schematic side view of the first preferred embodiment of the present invention;

Fig. 4 is a schematic side view of the first preferred embodiment of the present invention after obtaining most circuit elements and input-input bonding elements through semiconductor technology;

Fig. 5 is a schematic top view of the first preferred embodiment of the present invention after obtaining most circuit elements and output and input bonding elements through the semiconductor process;

Fig. 6 is the side view schematic diagram of the second preferred embodiment in the present invention;

FIG. 7 is a schematic top view of a third preferred embodiment of the present invention.

[Description of main component symbols]

Wafer-10; First Chip Unit-11; Conductive Pins-110; Semiconductor Layer-111; Metal Layer-112; Second Chip Unit-12; Aperture-121; Bonding Layer Unit-13; -131;

Die-810; Substrate-820; Metal wire-892;

Die-910; Substrate-920; Solder Ball-991; Substrate Pin-992;

Circuit elements - CKT1~CKTn;

Grain-D1~Dm. the

Detailed ways

Regarding the features and technical contents of the present invention, three preferred embodiments are described in detail below with reference to the accompanying drawings.

Since the present invention has several preferred embodiments, similar elements in the following preferred embodiments are denoted by the same numerals before detailed description.

1. The first preferred embodiment of the packaging structure of the integrated circuit

Referring to FIG. 3 , a preferred embodiment of the present invention includes: a first chip unit 11 , a second chip unit 12 and a bonding layer unit 13 . The first chip unit 11 and the second chip unit 12 respectively include at least one semiconductor layer 111 and at least one metal layer 112, and the material of the semiconductor layer 111 is a semiconductor material (such as: silicon (Si), gallium arsenide (GaAs), etc. ), and the bonding layer unit 13 is a metal layer.

It is worth noting that the first chip unit 11, the second chip unit 12, and the bonding layer unit 13 are sequentially bonded with the second chip unit 12 interposed between the first chip unit 11 and the bonding layer unit 13, and the second chip unit The area of 12 is greater than or equal to the area of the first chip unit 11 . In addition, since the bonding layer unit 13 is a metal layer, it can also be implemented by utilizing the lowest layer in the second chip unit 12 .

The first chip unit 11 and the second chip unit 12 are made in the way of semiconductor technology (such as: exposure, oxide layer deposition, etching, development, etc.), and relevant circuit elements are made in them. Because a circuit element manufacturing method using semiconductor technology is not For the main features of the present invention, please refer to the description of the relevant content in the book "Principles of CMOS VLSI Design" written by Neil H. E. Weste and Kamran Eshraghian, etc., and will not repeat them here.

Then, a plurality of apertures 121 are provided in the second chip unit 12 , wherein each aperture 121 penetrates through the second chip unit 12 respectively.

Finally, in the bonding layer unit 13, a plurality of input/output bonding elements 131 (I/O Pad) are manufactured by means of a semiconductor process.

Referring to Figures 4 and 5 together, it is assumed that the first chip unit 11 has n circuit elements CKT1~CKTn manufactured by semiconductor technology, and each circuit element CKT1~CKTn has its corresponding conductive pin 110, each conductive The pins 110 are respectively electrically connected to a corresponding output-input junction element 131 via a corresponding aperture 121, so that each circuit element CKT1~CKTn can receive a set of reference voltages (not shown in the figure) via its corresponding output-input junction element 131 ).

After the circuit elements in the first chip unit 11 receive the set of reference voltages and complete the test, each circuit element CKT1~CKTn in the first chip unit 11 can be obtained through wafer dicing, because the circuit element CKT1 ~CKTn is supported by the second chip unit 12, and can transmit or receive signals through the corresponding input and output bonding elements 131. Therefore, it does not need to go through traditional packaging processes such as wire bonding and glue filling, so it can reduce the Production costs of circuit components.

2. The second preferred embodiment of the packaging structure of the integrated circuit

Referring to FIG. 6, the biggest difference between the second preferred embodiment and the first preferred embodiment is: when the bottom layer of the second chip unit 12 is a metal layer, the metal layer can be regarded as the bonding layer unit 13, And make a plurality of input and output bonding elements on the metal layer, that is to say, the bonding layer unit 13 and the second chip 12 can also be made in an integrated manner, not limited to the way of making them separately in the first preferred embodiment And implement.

3. The third preferred embodiment of the packaging structure of the integrated circuit

Referring to FIG. 7, since the first chip units 11 including the circuit elements CKT1~CKTn do not need to be respectively arranged on a lead frame or a substrate as in the prior art, in this preferred embodiment, A plurality of first chip units 1 are arranged in a wafer 10 (Wafer) at the same time, and a corresponding second chip unit 12 is arranged, and each first chip unit 1 is separated through the aperture of the second chip unit 12 The conductive pin (Pin) is electrically connected to a bonding layer unit 13 having a plurality of output and input bonding elements 131, so if packaging is required, each first chip unit 11 is connected to the corresponding second chip unit 12, and bonded The layer units 13 can be directly packaged together, and then through the wafer dicing process, a plurality of dies D1~Dm respectively having the circuit elements CKT1~CKTn can be obtained. In other words, this preferred embodiment can effectively The area of each die having the circuit elements CKT1 - CKTn is reduced.

The biggest difference between the present invention and the prior art is that, after bonding the first chip unit and the second chip unit in the present invention, the first chip unit can receive a set of references through the apertures in the second chip units. Therefore, it is not as in the prior art that the wafer is cut into a plurality of dies, and then the dies are placed on a lead frame or a substrate for packaging and testing. Therefore, compared with the prior art In other words, the present invention integrates the first chip unit, the second chip unit, and the bonding layer unit in the integrated circuit, so that the first and second chip units can be tested and used through the input-input bonding element without After general packaging procedures (such as: setting surface mount type (SMT) pins, or wire bonding (WB) chip packaging), the first chip unit can be directly cut into multiple dies. Therefore, Compared with the prior art, the packaging and testing cost can be effectively reduced and the size of the packaged chip area can be reduced, so the purpose of the present invention can indeed be achieved.

The above is only a preferred embodiment of the present invention, and is not used to limit the scope of the patent of the present invention. All equivalent changes and modifications made according to the spirit of the patent of the present invention belong to the scope of protection of the patent of the present invention. Inside.

Claims (9)

1. A packaging structure for an integrated circuit, characterized in that the packaging structure for an integrated circuit comprises: a first chip unit; and A second chip unit, which is electrically connected to the first chip unit, the second chip unit has at least one semiconductor layer and at least one metal layer, and the second chip unit has a plurality of Apertures of the layer; wherein, each aperture respectively penetrates the second chip unit, and the first chip unit is electrically connected to an input-output joint element. 2 . The packaging structure of the integrated circuit according to claim 1 , wherein the second chip unit further has a bonding metal layer, and the bonding metal layer is fabricated into a plurality of input and output bonding elements according to a semiconductor process. 3. The packaging structure of the integrated circuit according to claim 1, characterized in that, the packaging structure of the integrated circuit further comprises a bonding layer unit, and the bonding layer unit is made into a plurality of output and input bonding elements according to the semiconductor process . 4. The packaging structure of an integrated circuit according to claim 3, wherein the first chip unit, the second chip unit and the bonding layer unit are packaged into an integrated circuit module. 5. The packaging structure of an integrated circuit according to claim 1, wherein the area of the second chip unit is larger than the area of the first chip unit. 6. The packaging structure of the integrated circuit according to claim 1, wherein the area of the second chip unit is equal to the area of the first chip unit. 7. The packaging structure of an integrated circuit according to claim 1, wherein the first chip unit and the second chip unit are packaged into an integrated circuit module. 8. The packaging structure of an integrated circuit according to claim 1, wherein the semiconductor layer is made of silicon. 9 . The packaging structure of the integrated circuit according to claim 1 , wherein the material of the semiconductor layer is gallium arsenide.

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