CN103324461A - Four-addend binary parallel synchronous adder - Google Patents
Four-addend binary parallel synchronous adder Download PDFInfo
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Abstract
The invention discloses a four-addend binary parallel synchronous adder which is mainly used for numerical calculation in the field digital arithmetic calculation and comprises an identical-weight digit add circuit, a bit carrying synthetic circuit and a final local sum generating circuit. The identical-weight digit add circuit is used for counting the quantities of high levels or low levels in original addends in each weight bit and displays continuous high levels at output ends, and one of two switch groups is selectively conducted according to the parity of the high levels, so that two power sources are provided for the final local sum generating circuit; first-order bit carrying lines, second-order bit carrying lines and 3-carrying lines are introduced into the bit carrying synthetic circuit, low-order bit carrying lines are selected by switches, so that the first-order bit carrying lines, second-order bit carrying lines and 3-carrying lines can be generated; the power sources from the identical-weight digit add circuit are selectively turned on or turned off by the bit carrying lines, so that final local sums can be generated by the final local sum generating circuit. The four-addend binary parallel synchronous adder has the advantages that the circuits are simple in structure, the design is neat, the four-addend binary parallel synchronous adder is low in hardware overhead, digit extension can be implemented easily, and only used time of the three basic gate circuits is required.
Description
Technical field
The invention belongs to electronic technology field and field of computer architecture, be realize four all bit parallel additions of scale-of-two addend, synchronously produce each weights position carry and final one's own department or unit and adding circuit, can be widely used in the arithmetic and logic unit of all kinds of microprocessors, digital signal processor and some special-purposes.
Background technology
In adder circuit family, two addend totalizers are little because of operand, circuit is simple, be easier to realize etc. former thereby paid close attention to, further investigation and widespread use.Aspect disclosed scientific paper and patent, two addend totalizers are mainly realized by the transistor logic door.Because this gate circuit adopts the transistor series structure, thereby cause adding circuit concurrent operation weak effect, synchronism is not strong, and along with the addend figure place increases, its hardware spending and operation time all may rise according to nonlinear relationship, thereby the current two addend binary adders that generally use accomplish at most 64, more the totalizer of seniority, such as 128 totalizers, on cost performance, lost practicality.
The present patent application people has disclosed a kind of " general multioperand adder " in Chinese patent 201210373908.8,2 given addend totalizers can address the above problem.It can finish the computing that surpasses 128 figure places by on-off circuit, and its hardware spending is linear with the addend figure place, and its operation use time only needs 3 basic gate circuit times fixing, has nothing to do with the addend figure place.This circuit really accomplished parallel addition each, produce synchronously each carry and final one's own department or unit and.
Although 2 addend totalizers have lot of advantages, comprise the 2 addend totalizers that patent 201210373908.8 proposes, to calculate 4 addends with it cumulative, that just needs repetitive operation 3 times, needs to surpass altogether the time of 9 basic gate circuits.This runs counter to current research high-speed computer trend.Consider if a kind of 4 addend totalizers are arranged, it can walk abreast all positions of four scale-of-two addends of addition, synchronously produce each weights position carry and final one's own department or unit and, within the time that is no more than 3 basic gate circuits, finish the computing that surpasses 128 figure places, and the hardware spending of this totalizer and addend figure place are linear, this totalizer has more advantage than current 2 addend totalizers so, and such totalizer has also just had researching value and using value naturally.
Present Domestic is the achievement in research of rare 4 addend totalizers outward, does not more satisfy the totalizer of this requirement.Although " the general multioperand adder " that disclose in Chinese patent 201210373908.8 by the present patent application people can extract 4 addend totalizers, can satisfy all positions of parallel four scale-of-two addends of addition, synchronously produce each weights position carry and final one's own department or unit and, and hardware spending and addend figure place are linear, but this totalizer is calculated time spent and needed time of 6 above basic gate circuits.Obviously, this 4 addend adder designs schemes are unsatisfactory.
Summary of the invention
In order to overcome defects, the invention discloses a kind of four addend scale-of-two parallel synchronous totalizers, be to solve the cumulative scheme of four multidigit binary number parallel synchronous.This totalizer is mainly by identical weights figure place adder circuit, carry synthetic circuit and final one's own department or unit and generation the electric circuit constitute.Wherein, identical weights figure place adder circuit is the circuit of realizing 4 one digit number additions.It is by two parts the electric circuit constitute, and some is statistical circuit, and another partly is that the power supply complementation initially adds and circuit.Statistical circuit mainly is the number of high level (such as " 1 ") or low level (such as " 0 ") in each original addend in weights position of statistics, adopted the selector switch array, and shown with continuous high level (such as " 1 ") and continuous low level (such as " 0 ") array configuration at output terminal.This course of work needs the time of 1 basic gate circuit.The power supply complementation initially adds with circuit controls 2 groups of switches by the output level of statistical circuit, one's own department or unit and parity according to these 4 original addends in weights position are selected wherein one group of switch conduction, so that for finally one's own department or unit and generation circuit provide two-way power supply (or being called high level).The output port of this two-way power supply is named as respectively strange power end and even power end.When one's own department or unit with when being odd number, one group of switch conduction, strange power end externally provides power supply, and another group switch disconnects, and even power end externally is high-impedance state; Otherwise when one's own department or unit with when being even number, even power end externally provides power supply, and strange power end externally is high-impedance state.This circuit working process also only needs the time of 1 basic gate circuit.
The carry synthetic circuit produces single order carry and second order carry according to the result of statistical circuit with from the information of low level, and it is as follows that its carry produces constraint condition:
Suppose that 4 n bits all are " 1 " of n position (n for greater than 1 natural number), namely maximum number can be write as 2n-1, then these 4 n figure places and be 4* (2
n-1)=(2
N+2-1)-2-1=
B(1).
Formula (1) illustrates: the addition of 4 multidigit binary numbers can only be advanced " 11B " at most to a high position, namely produce 2 rank carries, in other words, certain 4 the number sums add the low level carry, itself and be no more than 7.
Corresponding with " second order carry " and " single order carry ", the present invention has introduced " second order carry line " and " single order carry line ", wherein the high-low level of second order carry line represents corresponding position and whether has produced the second order carry, the single order carry line is determined more than or equal to " 2 " by original input number and the low level carry value sum of corresponding position, shows that this has produced second order carry or single order carry.Like this, when the second order carry line was high level, the high level of single order carry line only illustrated that this has produced carry, did not show necessarily to have the single order carry, and when the second order carry line was low level, the high level of single order carry line showed that just this has produced the single order carry.
By top definition as can be known, when the second order carry line was high level, the single order carry line also one was decided to be high level.Consider when the summation of certain 4 number sums and additions of low level carry more than or equal to 6 the time, namely this position not only produces the second order carry and has also produced the single order carry, for judge when the second order carry line during as high level the high level of single order carry line whether represent this and produced the single order carry, the present invention also introduces a mark line, be named " advancing 3 lines ", show in fact whether this position enters " 3 " to a high position.Like this, when second order carry line and single order carry line all are high level, be low level if advance 3 lines, then this position only produces the second order carry, and if to advance 3 lines be high level, then this position not only produces the second order carry and has also produced the single order carry.
The principle of design of carry synthetic circuit of the present invention is as follows: be directed to a certain position, 1. when 4 number sums are " 0 ", put that 3 lines are advanced in this position and the second order carry line is low level, the while transmits with single order carry form the possible second order carry of low level to a high position; 2. when 4 number sums are " 1 ", putting this position, to advance 3 lines be low level, and low level is advanced 3 line states be transferred to this second order carry line, and simultaneously the possible carry of low level, namely the single order carry line state of low level is transferred on this single order carry line; 3. when 4 number sums are " 2 ", putting this position, to advance 3 lines be low level, and to set the single order carry line be high level, selects simultaneously the second order carry line of low level to generate this second order carry; 4. when 4 number sums were " 3 ", putting the single order carry line was high level, selected simultaneously the single order carry line of low level to generate this second order carry, advanced 3 lines by low level again and decided this position to advance 3 line states; 5. when 4 number sums were " 4 ", putting single order carry line and second order carry line was high level, and the second order carry line by low level decides this position to advance 3 line states simultaneously.
" single order carry line ", " the second order carry line " and " advancing 3 lines " introduced according to the present invention, adopt form list certain " single order carry line ", " second order carry line ", " advancing 3 lines " and finally one's own department or unit and and the low level related data between relation.If: alphabetical A represent certain 4 original input numbers and, Y represents its parity, Si represent these 4 original input numbers and the addition of low level carry final one's own department or unit and, Ci_2 and Ci_1 represent respectively this second order carry line and single order carry line state, Ci_3 represents that this position advances 3 line states, letter b represents may adding of low level and (is its 4 original input numbers and the summation of its low level carry, maximum is no more than 7) rather than final one's own department or unit and, Ci-1_3, Ci-1_2 and Ci-1_1 represent respectively 3 lines that advance of low level, second order carry line and single order carry line state the results are shown in Table 1.
Table 1 operation relation table
Explain the principle of design of carry synthetic circuit according to table 1: 1. when 4 number sums are " 0 ", Ci_3=0, Ci_2=0, Ci_1=Ci-1_2 that is to say, on the one hand, no matter whether low level produces carry, this position all can not produce the second order carry, also can not affect into 3 line states, and namely 3 lines are advanced and the second order carry line is low level in this position; On the other hand, the second order carry of only having low level is the single order carry line state that high level just can affect this, thus to select to transmit the second order carry of low level, rather than the single order carry of low level.2. when 4 number sums are " 1 ", Ci_3=0, Ci_2=Ci-1_3, Ci_1=Ci-1_1 that is to say, on the one hand, no matter whether low level produces carry, it all is low level that 3 line states are advanced in this position, and this second order carry is subject to low level and advances the control of 3 line states; On the other hand, no matter whether the second order carry line of low level is high level, as long as the single order carry line of low level is high level, this position all can produce the single order carry so, thereby selects the single order carry line state of transmission low level.The single order carry line also must be the situation of high level when having considered here that the second order carry line is high level.3. when 4 number sums are " 2 ", Ci_3=0, Ci_2=Ci-1_2, Ci_1=1, this just explanation, this position is advanced 3 lines and not affected by the low level carry, keep low level, and if low level second order carry line is high level, then the second order carry line of this position is high level, otherwise be low level, thereby will select to transmit the second order carry of low level.Why this single order carry line is set is high level, is not only in order to illustrate that these position 4 number sums have produced carry, still in order to guarantee that these position 4 number sums are not masked because of the low level no-carry more than or equal to the situation of " 2 ".4. when 4 number sums when being " 3 ", Ci_3=Ci-1_3, Ci_2=Ci-1_1, Ci_1=1, that is to say, on the one hand advance 3 lines by low level and determine that this position advances 3 line states, and the single order carry line is set is high level, on the other hand, no matter whether the second order carry of low level is high level, as long as the single order carry line of low level is high level, namely low level has produced carry, this position all can produce the second order carry so, thereby selects the single order carry line of low level to generate this second order carry.5. when 4 number sums when be " 4 ", Ci_3=Ci-1_2, Ci_2=1, Ci_1=1 that is to say, the single order carry line directly is set one side and the second order carry line is high level, on the other hand, decides this position to advance 3 line states by the second order carry of low level.
The design of this carry synthetic circuit has three large characteristics: one, adopt on-off circuit fully, huge because switch has when disconnecting resistance, via resistance is very little and conduct electricity the characteristics such as rapid during conducting; Two, between low level and high-order " advancing 3 lines ", " second order carry line " and " single order carry line " this three line, a low bit line neither can appear and simultaneously conducting of high bit line more than 2, a high bit line can not appear yet and simultaneously conducting of low bit line more than two, and lead in formation on the switch passage of high-order " advancing 3 lines ", " second order carry line " and " single order carry line ", each passage only has at most a way switch conducting, and this has just guaranteed between the high-low-position carry of circuit without feedback and has crosstalked; Three, the carry synthetic circuit only takies the time of a basic gate circuit.
Final one's own department or unit and generation circuit are comprised of two groups of on-off circuits and a pull down resistor.These two groups of on-off circuits are defined as respectively even control circuit and post control circuit, its output terminal merged final one's own department or unit and output as this, and provide low level by the pull down resistor that connects.Final one's own department or unit of each and produce circuit and all controlled by advance 3 lines, second order carry line and single order carry line from low level carry synthetic circuit is in order to select the out-put supply complementation initially to add strange power supply output signal or even power supply output signal with circuit.This circuit also only takies the time of a basic gate circuit.
Provide the design concept of final one's own department or unit and generation circuit according to table 1.When Y=1, the strange power end that the power supply complementation initially adds with circuit provides power supply, and even control circuit work is posted control circuit and is high-impedance state, if this moment Ci-1_3, three's high level number sum of Ci-1_2 and Ci-1_1 is even number, and a way switch path conducting is then arranged in the even control circuit, has selected the power supply complementation initially to add with the power supply of posting of circuit and has exported, Si exports high level, otherwise without any way switch path conducting, Si is defined as low level by pull down resistor in the even control circuit; When Y=0, the even power end that the power supply complementation initially adds with circuit provides power supply, posts control circuit work, and even control circuit is high-impedance state, if this moment Ci-1_3, three's high level number sum of Ci-1_2 and Ci-1_1 is for posting number, and then posting has a way switch path conducting in the control circuit, has selected the power supply complementation initially to add with the even power supply of circuit and has exported, Si exports high level, otherwise, posting in the control circuit without any way switch path conducting, Si is defined as low level by pull down resistor.
In the present invention, statistical circuit takies a basic gate circuit time, and the power supply complementation initially adds with circuit and carry synthetic circuit and starts simultaneously, takies altogether a basic gate circuit time, final one's own department or unit and produce circuit and also only take a basic gate circuit time.Consider that the present invention uses on-off circuit, communication time is short more than the Time Created of switch conduction on it, like this, in case related switch is opened simultaneously in the carry synthetic circuit of all, the communication time from the lowest order to the most significant digit can be ignored, therefore, totalizer of the present invention only needs the time spent of 3 basic gate circuits, and is irrelevant with the addend figure place in limited range.
Based on foregoing invention description of contents and the illustrative examples that provides of accompanying drawing subsequently, compared with prior art, circuit structure of the present invention is regular, and is low in energy consumption, and the time spent is few, only need 3 basic gate circuit times fixing, irrelevant with the addend figure place, hardware spending is low, and is linear with the addend figure place, be easy to expansion, satisfying the adding circuit that to accomplish under the cost performance requirement more than 128.
By read content of the present invention, in conjunction with innovation pointed in following the description of the drawings and the claims etc., the those skilled in the art can have clearer understanding and understanding to the above-mentioned content relevant with other and target of the present invention, may exist some advantages of the present invention and new application not to provide at this, but still wish to be included in the limited range of the claims of enclosing.
In order more comprehensively, systematically to understand content of the present invention, be described in further detail below in conjunction with accompanying drawing.
Description of drawings:
Fig. 1 is theory diagram of the present invention;
Fig. 2 is the illustrative examples schematic diagram of expanding four addend scale-of-two parallel synchronous totalizers of the present invention;
Fig. 3 present invention is directed at a certain position to be input to the illustrative circuitry embodiment schematic diagram that adds with result's output from addend;
Fig. 4 is the illustrative examples schematic diagram of non-expansion four addend scale-of-two parallel synchronous totalizers of the present invention.
Embodiment:
Below in conjunction with accompanying drawing illustrative examples of the present invention is described in detail.Note that hereinafter described is illustrative examples of the present invention, and should not be limited to these embodiment and following description when of the present invention understanding.
Fig. 1 is theory diagram of the present invention, and it mainly is comprised of a plurality of unit 110,120 and 130.Wherein unit 110 is exactly identical weights figure place adder circuit, can add up the number of " 1 " in the original input number, and determine the on off operating mode of two-way power supply according to parity as a result; Unit 120 is exactly the carry synthetic circuit, can select conducting to the information from low level by the statistics of unit 110, in order to produce single order carry, second order carry and advance 3 line information; Unit 130 is exactly final one's own department or unit and produces circuit, can select the two-way power supply that unit 110 provides according to the carry information from low level, thereby produce final one's own department or unit and.
Fig. 2 has provided the schematic diagram of Fig. 1, with 4 16 figure place totalizers as illustrative examples of the present invention.For unit 110 among more clear description Fig. 2,120 and 130 the course of work, we choose the unit 110,120 and 130 of any weights position, and are labeled among Fig. 3 in detail.Can find out, unit 110 is comprised of unit 111 and unit 112 again.
(1) when Yi_2, Mi_1, Yi_1 and Mi_0 are low level (illustrating that it is 0 that sum is counted in original input), low level single order carry on this carry without impact, and low level second order carry line is as long as be high level, this position will produce the single order carry, but can not produce the second order carry, thereby Mi_0 gauge tap K20-conducting, this single order carry line and the conducting of low level second order carry line, Simultaneous Switching K9+, K10+, K12+, K14+, K17+, K18+, K19+ and K21+ disconnect, this second order carry line and advance 3 lines and be defined as low level by pull down resistor.
(2) when Yi_2, Mi_1 and Yi_1 be low level, when Mi_0 is high level (illustrating that it is 1 that sum is counted in original input), as long as low level produces carry, no matter be low level second order carry, or low level single order carry, all will be transmitted to a high position with the single order carry value by this position, thereby Yi_1 and Mi_0 control respectively K22-and K21+ conducting, low level single order carry line and this single order carry line conducting.In addition, if low level advances 3, namely advancing 3 lines is high level, and then this position also can produce the second order carry, so the controlled conducting processed of K16-, K15-, K13-and K12+ is advanced the state that 3 lines determine the second order carry line by low level.Cut-off switch K9+, K10+, K14+, K17+, K18+, K19+ and K20-advance 3 lines and are defined as low level by pull down resistor simultaneously.
(3) when Yi_2 and Mi_1 be low level, when Yi_1 and Mi_0 are high level (illustrating that it is 2 that sum is counted in original input), if low level second order carry line is high level, will be transmitted to a high position with the second order carry by this position, otherwise, this second order carry line will be low level, thereby by Yi_2, Mi_1 and respectively gauge tap K16-, K15-and K14+ conducting of Yi_1, in order to select the second order carry line.In addition, Yi_1 gauge tap K19+ conducting is high level in order to force the single order carry line.Simultaneously, K switch 9+, K10+, K13-, K17+, K18+, K20-and K22-disconnect, and advance 3 lines and are defined as low level by pull down resistor.
(4) when Yi_2 be low level, Mi_1 is that (this moment, Yi_1 and Mi_0 also were high level to high level, illustrate that it is 3 that sum is counted in original input) time, no matter whether low level second order carry line is high level, as long as the single order carry line is high level, namely necessarily there is carry in low level, and this position all can produce the second order carry so, thereby by Yi_2 and respectively gauge tap K16-and K17+ conducting of Mi_1, in order to select the single order carry line.In addition, Yi_1 gauge tap K19+ conducting is high level in order to force the single order carry line.Simultaneously, Yi_2 and Mi_1 gauge tap K11-and K10+ conducting are advanced 3 lines by low level and are determined that this advances the state of 3 lines.
(5) when Yi_2 be that (this moment, Mi_1, Yi_1 and Mi_0 also were high level to high level, illustrate that it is 4 that sum is counted in original input) time, no matter whether low level produces carry, this second order carry line and single order carry line all are high level, thereby by Yi_2 and respectively gauge tap K18+ and K19+ conducting of Yi_1.In addition, no matter how low level advances 3 line states, as long as low level second order carry line is high level, this position is advanced 3 lines and just is high level, thus Yi_2 gauge tap K9+ conducting, so that transmission low level second order carry line state.
Above-mentioned analytic explanation, no matter any in five kinds of situations, at single order carry line, the second order carry line of low level with advance 3 lines and this single order carry line, second order carry line and the situation of advancing neither to exist between 3 lines a low bit line to communicate with a plurality of high bit lines simultaneously, the situation that does not also exist a high bit line to communicate with a plurality of low bit lines simultaneously, and lead on the high-order switch passage that advances 3 lines, second order carry line and single order carry line in formation, each passage only has at most a way switch conducting.This has just cut off single order carry line, the second order carry line of coordination and has advanced 3 lines and has produced mutually mutual interference by on-off circuit, has guaranteed the circuit normal operation.
By Fig. 2 and Fig. 3 as can be known, when 4 addend A0_0～A15_0, A0_1～A15_1, A0_2～A15_2 and A0_3～A15_3 are applied to each weights bit location 111 simultaneously, all unit 111 concurrent workings, and through a basic gate circuit after the time, synchronously Output rusults.These output signals are applied to the unit 112 and 120 of corresponding positions synchronously.Their concurrent workings, through a basic gate circuit after the time, export synchronously corresponding result, wherein all unit 120 are at single order carry line, second order carry line with advance the corresponding carry value of 3 lines output, and all unit 112 are exported high level or presented high-impedance state at its Yi_0 end and backward end/Yi_0.At last, all unit 112 and 120 output signal are applied to corresponding positions unit 130 synchronously, then all unit 131 and 132 beginning concurrent workings, also through a basic gate circuit after the time, export synchronously corresponding positions final one's own department or unit and.As seen, 4 16 figure places of the present invention are cumulative only to need 3 basic gate circuit times, same, for more 4 addend additions of seniority, also only needs 3 basic gate circuit times.In addition, the present invention approximately needs 48n switch (wherein 1 selector switch is equivalent to 2 switches in the unit 111) for 4 n figure place adder circuits.
The illustrative examples that Fig. 2 is four addend scale-of-two parallel synchronous totalizers of the present invention under can the expansion state.This totalizer has identical unit 110,120 and 130 owing to each, thereby is easy to expand the addition number figure place, implements not 4 addend adder designs of isotopic number, also can not increase a plurality of so identical totalizers of series connection use in the situation consuming time.When carrying out the low level expansion, input end C-1_1, the C-1_2 of low level and C-1_3 can be used for respectively being connected to high-order single order carry line, the second order carry line of another four addends totalizer and advancing 3 lines; When not needing to carry out the low level expansion, C-1_1, C-1_2 and C-1_3 connect low level; When carrying out high position expansion, control end CTR1 and CTR2 connect low level, S17 and S16 are exactly high-order second order carry line and single order carry line, can be used for connecting second order carry line, the single order carry line of another four addends totalizer lowest order and advancing 3 lines with C15_3; When not needing to carry out high position expansion, control end CTR1 is connected to S17, and CTR2 is connected to C15_3.At this moment, S17 and S16 are respectively high-order second order carry and the single order carry output terminals of 4 16 figure place totalizers.Here need explanation, the switch that CTR1 and CTR2 control enabling time point with consuming time aspect consistent with unit 130, also, this part can't additionally increase the consuming time of four addend scale-of-two parallel synchronous totalizers.In addition, the spirit according to the present invention, the switch of CTR1 control guarantees that when the second order carry was high level, the single order carry can not be forced high level, and the switch of CTR2 control is then guaranteed both to have produced in a high position and can be demonstrated the single order carry value when second order carry also produces the single order carry.
Fig. 4 is the illustrative examples of four addend scale-of-two parallel synchronous totalizers of the present invention under non-expansion condition.This also is 16 binary adders of 4 addends, and the part different from Fig. 2 is at lowest order, inferior low level circuit, and the carry of most significant digit forms circuit.Do not expand because do not need, so Fig. 4 circuit lowest order does not have input end C-1_1, C-1_2 and C-1_3, reduce backward end/Y0_0 and formed circuit, and unit 130, only obtain this single order carry line state by switch of Y0_1 control, obtain this second order carry value by switch of Y0_2 control, and directly form final one's own department or unit, this position and S0 by port Y0_0; Inferior low level is compared with its high position because of its low level and has been deleted all and advance the switch that 3 lines are associated with low level without advancing 3 lines; Form in the circuit in the carry of most significant digit, directly with the second order carry line with advance 3 lines and respectively control a switch, so that single order carry value and the second order carry value of acquisition most significant digit.
In Fig. 2, Fig. 3 and Fig. 4, in the unit 111 in selector switch and other unit switch can make with different materials, as long as resistance is huge when satisfy disconnecting, via resistance is very little and conduct electricity the characteristics such as rapid during conducting, and applied environment etc., such switch namely can be used in the present invention, such as atom switch, quantum switch, photon switch, transistor switch and electric switch etc.
Although the present invention describes four addend multidigit scale-of-two parallel synchronous totalizers, but it also be applicable to four the number subtract each other, with, the phase or, and two number multiply each other etc. in a variety of computing circuits, as long as bill of lading unit of institute of the present invention with switch carries out reasonable combination and modification just can realize the function that a lot of the present invention had not mentioned.
Although introduced the present invention by describing illustrative examples of the present invention, should be understood that, the people who is proficient in this area still can carry out various modifications on pro forma and the details to the present invention, and does not break away from the spirit and scope of the present invention.
Claims (10)
1. an addend scale-of-two parallel synchronous totalizer is characterized in that, described totalizer is mainly by identical weights figure place adder circuit, carry synthetic circuit, final one's own department or unit and generation the electric circuit constitute;
Identical weights figure place adder circuit is the circuit of realizing 4 one digit number additions, and it is by two parts the electric circuit constitute, and some is statistical circuit, and another partly is that the power supply complementation initially adds and circuit;
Statistical circuit mainly is the number of high level " 1 " or low level " 0 " in each original addend in weights position of statistics, and at output terminal with continuous high level " 1 " and continuously low level " 0 " array configuration demonstration;
The power supply complementation initially adds with circuit controls 2 groups of switches by the output level of statistical circuit, one's own department or unit and parity according to these 4 original addends in weights position are selected wherein one group of switch conduction, so that for finally one's own department or unit and generation circuit provide two-way power supply (or being called high level);
The principle of design of carry synthetic circuit is: be directed to a certain position, 1. when 4 number sums are " 0 ", put that 3 lines are advanced in this position and the second order carry line is low level, the while transmits with single order carry form the possible second order carry of low level to a high position; 2. when 4 number sums are " 1 ", putting this position, to advance 3 lines be low level, and low level is advanced 3 line states be transferred to this second order carry line, and simultaneously the possible carry of low level, namely the single order carry line state of low level is transferred on this single order carry line; 3. when 4 number sums are " 2 ", putting this position, to advance 3 lines be low level, and to set the single order carry line be high level, selects simultaneously the second order carry line of low level to generate this second order carry; 4. when 4 number sums were " 3 ", putting the single order carry line was high level, selected simultaneously the single order carry line of low level to generate this second order carry, advanced 3 lines by low level again and decided this position to advance 3 line states; 5. when 4 number sums were " 4 ", putting single order carry line and second order carry line was high level, and the second order carry line by low level decides this position to advance 3 line states simultaneously;
Final one's own department or unit and produce circuit by even control circuit, post control circuit and a pull down resistor forms; Final one's own department or unit of each and produce circuit and all controlled by advance 3 lines, second order carry line and single order carry line from low level carry synthetic circuit is in order to select the out-put supply complementation initially to add strange power supply output signal or even power supply output signal with circuit.
2. four addend scale-of-two parallel synchronous totalizers according to claim 1, it is characterized in that: described statistical circuit has adopted the selector switch array, shows the number of " 1 " or " 0 " in the input data with the form of continuous high level at output terminal.
3. four addend scale-of-two parallel synchronous totalizers according to claim 1 is characterized in that: described power supply complementation initially add with circuit according to one's own department or unit and parity, utilize on-off circuit externally to select to provide one road power supply and one tunnel high-impedance state; When one's own department or unit with when being odd number, one group of switch conduction, strange power end externally provides power supply, and another group switch disconnects, and even power end externally is high-impedance state; Otherwise when one's own department or unit with when being even number, even power end externally provides power supply, and strange power end externally is high-impedance state.
4. four addend scale-of-two parallel synchronous totalizers according to claim 1, it is characterized in that: described carry synthetic circuit has been introduced the single order carry line, second order carry line and advance 3 lines, wherein the high-low level of second order carry line represents corresponding position and whether has produced the second order carry, the single order carry line is determined more than or equal to " 2 " by original input number and the low level carry value sum of corresponding position, show that this has produced second order carry or single order carry, advancing 3 lines and be to show whether corresponding position advances 3 to a high position, also is to distinguish when the second order carry line is high level the single order carry line whether to represent this and produced the single order carry.
5. according to claim 1 or 4 described four addend scale-of-two parallel synchronous totalizers, it is characterized in that: between carry synthetic circuit low level and high-order " advancing 3 lines ", " second order carry line " and " single order carry line " this three line, a low bit line neither can appear and simultaneously conducting of high bit line more than 2, a high bit line can not appear yet and simultaneously conducting of low bit line more than two, and lead in formation on the switch passage of high-order " advancing 3 lines ", " second order carry line " and " single order carry line ", each passage only has at most a way switch conducting.
6. four addend scale-of-two parallel synchronous totalizers according to claim 1, it is characterized in that: described final one's own department or unit and the output terminal merged final one's own department or unit and the output as corresponding position that produce the even control circuit of circuit and post control circuit, and provide low level by the pull down resistor that connects; When one's own department or unit with when being odd number, the strange power end that the power supply complementation initially adds with circuit provides power supply, the work of idol control circuit, post control circuit and be high-impedance state, if low level " advances 3 lines " at this moment, three's high level number sum of " second order carry line " and " single order carry line " is even number, a way switch path conducting is arranged in the even control circuit then, final one's own department or unit and be high level, otherwise, in the even control circuit without any way switch path conducting, final one's own department or unit and be defined as low level by pull down resistor; When one's own department or unit with when being even number, the even power end that the power supply complementation initially adds with circuit provides power supply, post control circuit work, the idol control circuit is high-impedance state, if low level " advances 3 lines " at this moment, three's high level number sum of " second order carry line " and " single order carry line " is odd number, then posting has a way switch path conducting in the control circuit, final one's own department or unit and be high level, otherwise, post in the control circuit without any way switch path conducting final one's own department or unit and be defined as low level by pull down resistor.
7. four addend scale-of-two parallel synchronous totalizers according to claim 1, it is characterized in that: described totalizer has adopted on-off circuit fully, resistance was huge when switch had disconnection, the very little and conduction of via resistance rapidly during conducting, as long as switch designs of the present invention requires and applied environment just can be implemented the present invention no matter the switch of selecting which kind of material to make satisfies, all belong to category of the present invention.
8. four addend scale-of-two parallel synchronous totalizers according to claim 1, it is characterized in that: described statistical circuit takies a basic gate circuit time, the power supply complementation initially adds with circuit and carry synthetic circuit and starts simultaneously, take altogether a basic gate circuit time, final one's own department or unit and generation circuit also only take a basic gate circuit time.
9. four addend scale-of-two parallel synchronous totalizers according to claim 1, it is characterized in that: the described totalizer time spent is the time of 3 basic gate circuits, and hardware spending is low, and is linear with the addend figure place.
10. four addend scale-of-two parallel synchronous totalizers according to claim 1 is characterized in that: described totalizer also be applicable to four numbers subtract each other, with, mutually or, and in two several a variety of computing circuits such as multiply each other.
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| CN103324461B (en) | 2015-12-23 |
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