CN103311107A - Method for making metal silicide and semiconductor structure using same - Google Patents

Abstract

The invention discloses a method for manufacturing metal silicide and a semiconductor structure using the same. The method for manufacturing the metal silicide comprises the following steps: providing a substrate, wherein the substrate is provided with a first area and a second area; forming a silicon layer on the substrate; performing a planarization process to make the silicon layer have a flat surface; removing part of the silicon layer to form a plurality of first gates in the first region and a plurality of second gates in the second region, wherein the heights of the first gates are greater than those of the second gates, and the first gates and the second gates have upper surfaces with the same height in the horizontal plane; forming a dielectric layer on the substrate, wherein the dielectric layer covers the first gates and the second gates and exposes the upper surfaces of the first gates and the second gates; and forming a metal silicide on the upper surfaces of the first gates and the second gates.

Description

Method for making metal silicide and semiconductor structure using same

technical field

The present invention relates to a semiconductor process and structure, and in particular to a method for making metal silicide and a semiconductor structure using the same.

Background technique

With the increase in the integration of semiconductor components, the pattern and line width in the component are gradually reduced, which leads to an increase in the contact resistance between the gate and the wire in the component, resulting in a large resistance-capacitance delay (RC Delay), which affects the component. operating speed. Since the resistance of metal silicide is lower than polysilicon (Polysilicon), and its thermal stability is higher than that of general interconnection materials, metal silicide is formed on the gate in order to reduce the resistance between the gate and the metal interconnection. .

In the traditional process of forming metal silicide, when the gate (such as a polysilicon layer) is formed on the semiconductor wafer, the silicidation process of the gate includes forming a metal layer on the polysilicon layer, followed by an annealing process to form a metal silicide on the grid.

In current gate fabrication in the peripheral circuit area, metal silicide is also required to reduce the resistance between the wire and the gate. However, in the traditional self-aligned metal silicide process, if metal silicide is to be formed on part of the medium, it must go through quite complicated procedures to form metal silicide on the required area, especially when the memory cell array area When the height of the horizontal plane is different from that of the peripheral circuit area, the difficulty of process execution is further increased. In the current era of high efficiency, it is necessary to improve the traditional method to improve the efficiency of the semiconductor process.

Contents of the invention

The present invention relates to a method for making metal silicide and a semiconductor structure using the same. It is to form gates with the same horizontal plane height on the memory cell array area and the peripheral circuit area, so as to prevent the gate located in the lower area from being caused by interference. The electrical layer is shielded and the metal silicide cannot be formed smoothly.

According to one aspect of the present invention, a method for fabricating a metal silicide is proposed, including the following steps. A substrate is provided, and the substrate has a first region and a second region. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer have a flat surface. removing part of the silicon layer to form a plurality of first gates in the first region and a plurality of second gates in the second region, the height of the plurality of first gates being greater than the height of the plurality of second gates , and the plurality of first gates and the plurality of second gates have upper surfaces with the same level height. forming a dielectric layer on the substrate, the dielectric layer covers the plurality of first gates and the plurality of second gates, and exposes the upper surfaces of the plurality of first gates and the plurality of second gates surface. A metal silicide is formed on the upper surfaces of the plurality of first gates and the plurality of second gates.

According to another aspect of the present invention, a semiconductor structure is provided, including a substrate, a silicon layer, a dielectric layer, and a metal silicide. The substrate has a first area and a second area. The silicon layer has a plurality of first gates located in the first region and a plurality of second gates located in the second region, wherein the heights of the plurality of first gates are greater than the heights of the plurality of second gates, and the heights of the plurality of second gates are The plurality of first grids and the plurality of second grids have upper surfaces with the same level height. The dielectric layer is formed on the substrate, and the dielectric layer exposes the upper surfaces of the plurality of first gates and the plurality of second gates. Metal silicides are respectively formed on the upper surfaces of the plurality of first gates and the plurality of second gates.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples, together with the accompanying drawings, are described in detail as follows:

Description of drawings

1A-1F are schematic diagrams illustrating a method for fabricating a metal silicide and a semiconductor structure using the same according to an embodiment of the present invention.

2A-2F are schematic diagrams illustrating a method for fabricating a metal silicide and a semiconductor structure using the method according to an embodiment of the present invention.

[Description of main component symbols]

100, 200: Substrate

101, 201: the first area

102, 202: the second area

103, 203: local inner connection area

104: sloped surface

110, 110a, 210, 210a: silicon layer

111, 211: flat surface

120, 220: upper surface

121, 221: the first grid

122, 222: second grid

123, 223: the third gate

130, 230: dielectric layer

140, 240: metal silicide

W, X, X1, Y: Height

212: polysilicon layer

214, 214a: amorphous silicon layer

Detailed ways

The method for making metal silicide and the semiconductor structure using the same of the present invention are to deposit a silicon layer with increased thickness on the substrate, and then use a planarization process to thin it, so that the silicon layer has a flat surface with uniform horizontal plane height. After the silicon layer is patterned, a first gate and a second gate with the same horizontal plane height are formed. Therefore, metal silicide can be smoothly formed on the gates on the memory cell array area and the peripheral circuit area in the subsequent thermal process, so as to reduce the sheet resistance of the gates.

Various embodiments are presented below for detailed description, and the embodiments are only used as examples for illustration, and are not intended to limit the scope of protection of the present invention.

first embodiment

Please refer to FIG. 1A to FIG. 1F , which are diagrams illustrating a method for fabricating a metal silicide and a semiconductor structure using the method according to an embodiment of the present invention. This method at least includes the following steps. A substrate 100 is provided, and the substrate 100 has a first region 101 and a second region 102 . A silicon layer 110 is formed on the substrate 100 . A planarization process is performed so that the silicon layer 110 has a flat surface 111 . Part of the silicon layer 110 is removed to form a plurality of first gates 121 in the first region 101 and a plurality of second gates 122 in the second region 102 . The height X+Y of the first gate 121 is greater than the height Y of the second gate 122 , and the first gate 121 and the second gate 122 have an upper surface 120 with the same level. Forming a dielectric layer 130 on the substrate 100, the dielectric layer 130 covers the plurality of first gates 121 and the second gates 122, and exposes the plurality of first gates 121 and the second gates 122 120 on the upper surface. A metal silicide 140 is formed on the upper surfaces 120 of the plurality of first gates 121 and the second gates 122 .

In FIG. 1A , the substrate 100 has a first region 101 and a second region 102 . The silicon layer 110 is formed on the substrate 100 and covers the first region 101 and the second region 102 with equal thickness. The first region 101 and the second region 102 of the substrate 100 have different heights relative to the bottom surface of the substrate 100 , so that there is obviously a height difference X between the first region 101 and the second region 102 . In addition, the substrate 100 has, for example, an inclined surface 104 located in a local interconnection region 103 such that the local interconnection region 103 is inclined between the first region 101 and the second region 102 .

In this embodiment, the substrate 100 is a silicon-rich semiconductor substrate, and the silicon layer 110 is, for example, a polysilicon layer formed by chemical vapor deposition, which has a height W greater than a predetermined deposition height X+Y, where X is The height difference between the first region 101 and the second region 102 , Y is the ideal height of the second gate 122 . The first area 101 is, for example, a memory cell array area, and the second area 102 is, for example, a peripheral circuit area. In another embodiment, the first area 101 is, for example, a peripheral circuit area, and the second area 102 is, for example, a memory cell array area. In the area of the memory cell array, there are active elements (such as memory cells) for storing data. There are logic units (such as transistor switches) in the peripheral circuit area to read and calculate the data stored in the memory storage unit. In the subsequent process, the silicon layer 110 after the planarization process and the patterning process can serve as the gate of the memory storage unit and the gate of the logic unit respectively.

Referring to FIG. 1B , a planarization process such as chemical mechanical polishing is performed so that the silicon layer 110 a has a planar surface 111 . At this time, the height of the thinned silicon layer 110 a relative to the first region 101 is X+Y, and the height relative to the second region 102 is Y. Next, referring to FIG. 1C , part of the silicon layer 110a is removed by photolithography and anisotropic etching to form a plurality of first gates 121 in the first region 101 and a plurality of first gates 121 in the second region 102. Two gates 122 . The height of the first grid 121 is X+Y, and the height of the second grid 122 is Y, so the height of the first grid 121 is greater than the height of the second grid 122, and the first grid 121 and the second grid The pole 122 has an upper surface 120 with a uniform level. In the process of FIG. 1C, a third gate 123 can be formed on the local interconnection region 103, and the first gate 121, the second gate 122, and the third gate 123 have the upper surface 120 with the same level height. . In this embodiment, the first gate 121, the second gate 122 and the third gate 123 are, for example, the gates of transistors (such as N-type metal-oxide-semiconductor transistors) with the same polarity, or gates connected to N-type metal oxide semiconductor transistors. The oxide semiconductor transistor is the gate of the P-type metal oxide semiconductor transistor with the opposite polarity. In one embodiment, the third gate 123 can also be replaced by a local interconnection line between the first gate 121 and the second gate 122 , not limited to the gate of the transistor.

Please refer to FIG. 1D and FIG. 1E, forming a dielectric layer 130 on the substrate 100, so that the dielectric layer 130 is filled in the gap between the adjacent two grids, and covers the first grid 121, the second grid electrode 122 and the upper surface 120 of the third grid 123 . In FIG. 1E, the dielectric layer 130 can be thinned by a planarization process such as chemical mechanical polishing, so that the dielectric layer 130 is consistent with the level of the gates 121-123, and the first gate 121, the second gate 121, and the second gate are exposed. electrode 122 and the upper surface 120 of the third grid 123 .

Next, referring to FIG. 1F , a metal silicide 140 is respectively formed on the upper surfaces 120 of the first gate 121 , the second gate 122 and the third gate 123 . The metal silicide 140 is formed by thermally melting the metal layer and the adjacent thinned silicon layer 110a during a thermal process, such as 960 degrees Celsius, so that the metal particles and silicon crystals are rearranged. The steps of forming salicide 140 in FIG. 1F are as follows. First, a metal layer (not shown) is formed on the thinned silicon layer 110 a and the dielectric layer 130 by chemical vapor deposition or physical vapor deposition. A thermal process, such as an annealing process, is performed to make the metal layer interact with the silicon layer 110 a to form the metal silicide 140 . Next, a portion of the metal layer that has not reacted with the silicon layer 110 a is removed. The metal silicide 140 is, for example, tungsten silicide, molybdenum silicide, cobalt silicide, titanium silicide, nickel silicide or other refractory metal silicides. ) to reduce the sheet resistance values of the first gate 121 , the second gate 122 and the third gate 123 .

second embodiment

Please refer to FIG. 2A to FIG. 2F , which are diagrams illustrating a method for fabricating a metal silicide and a semiconductor structure using the method according to an embodiment of the present invention. The difference between this embodiment and the first embodiment lies in the steps of forming the silicon layer 210 in FIG. 2A and planarizing the silicon layer 210 in FIG. 2B . As for the processes of patterning the silicon layer 210a, forming the dielectric layer 230 and planarizing the dielectric layer 230, and forming the metal silicide 240 in FIGS. repeat.

2A, the silicon layer 210 includes a polysilicon layer 212 with a first height Y and an amorphous silicon layer 214 with a second height X1 formed by chemical vapor deposition, wherein the second height X1 is greater than (or equal to) the first region 201 and The height difference X of the second region 202, and the first height Y is the ideal height of the second gate 222, so the silicon layer 210 has a total height W greater than the predetermined deposition height X+Y.

Referring to FIG. 2B , a planarization process such as chemical mechanical polishing is performed so that the silicon layer 210 has a planar surface 211 . At this time, the height of the thinned silicon layer 210 a relative to the first region 201 is X+Y, and the height relative to the second region 202 is Y. In this embodiment, the amorphous silicon layer 214 located in the second region 202 is removed to expose the underlying polysilicon layer 212, so that the non-removed amorphous silicon layer 214a in FIG. 2B is aligned with the polysilicon layer 212, and The flat surface 211 has the same level as the polysilicon layer 212 . Since the polysilicon layer 212 under the amorphous silicon layer 214 can be used as a stop layer for etching or chemical mechanical polishing of the silicon layer 210 , the etching depth of the silicon layer 210 can be precisely controlled.

In subsequent FIG. 2B , before forming the metal silicide 240 , the amorphous silicon layer 214 a can be converted into another polysilicon layer by heating, for example, about 600 degrees Celsius to recrystallize it. Since the polysilicon layer has better electron mobility than the amorphous silicon layer 214a, the switching capability of the memory storage unit and the driving capability of the logic unit can be improved.

In this embodiment, after the silicon layer 210a is patterned (refer to FIG. 2C ), the first gate 221 , the second gate 222 and the third gate 223 form the upper surface 220 with the same horizontal plane height. Therefore, metal silicide can be formed smoothly in the subsequent thermal process on the gates on the first region 201 (such as the memory cell array region), the second region 202 (such as the peripheral circuit region) and the local internal connection region 203. 240 to reduce the sheet resistance value of the gate.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (10)

1. A method for making metal silicide, comprising: providing a substrate having a first region and a second region; forming a silicon layer on the substrate; performing a planarization process so that the silicon layer has a planar surface; removing part of the silicon layer to form a plurality of first gates in the first region and a plurality of second gates in the second region, the height of the plurality of first gates is greater than that of the plurality of second gates The height of the electrode, and the plurality of first grids and the plurality of second grids have upper surfaces with the same level height; forming a dielectric layer on the substrate, the dielectric layer covering the plurality of first gates and the plurality of second gates, and exposing the plurality of first gates and the plurality of second gates the upper surface of the A metal silicide is formed on the upper surfaces of the plurality of first gates and the plurality of second gates. 2. The method for manufacturing metal silicide according to claim 1, wherein the first region and the second region are respectively a memory cell array region and a peripheral circuit region. 3. The method for fabricating metal silicide according to claim 1, wherein the substrate has an inclined surface located in a local interconnection region, the local interconnection region is located between the first region and the second region, The first region of the substrate has a height difference relative to the second region, and the plurality of first gates are formed on the first region with a lower height, and the plurality of second gates are formed on the lower height high on this second region. 4. The method for making metal silicide according to claim 1, wherein the steps of forming the silicon layer and planarizing the silicon layer comprise: forming a polysilicon layer on the substrate; forming an amorphous silicon layer on the polysilicon layer; and The amorphous silicon layer is planarized so that the amorphous silicon layer is aligned with the polysilicon layer and has a flat surface with the polysilicon layer. 5. The method for fabricating a metal silicide as claimed in claim 4, further comprising heating the amorphous silicon layer to a recrystallization temperature to form another polysilicon layer after planarizing the amorphous silicon layer. 6. The method for fabricating a metal silicide as claimed in claim 1, further comprising planarizing the dielectric layer after forming the dielectric layer. 7. The method for making a metal silicide according to claim 1, wherein the step of forming the metal silicide comprises: forming a metal layer on the silicon layer and the dielectric layer; performing a thermal process to react the metal layer with the silicon layer to form the metal silicide; and The portion of the metal layer that has not reacted with the silicon layer is removed. 8. A semiconductor structure comprising: a substrate having a first region and a second region; A silicon layer having a plurality of first gates located in the first region and a plurality of second gates located in the second region, wherein the height of the plurality of first gates is greater than that of the plurality of second gates height, and the plurality of first gates and the plurality of second gates have an upper surface with the same horizontal plane height; a dielectric layer is formed on the substrate, and the dielectric layer exposes the upper surfaces of the plurality of first gates and the plurality of second gates; and A metal silicide is respectively formed on the upper surfaces of the plurality of first gates and the plurality of second gates. 9. The semiconductor structure according to claim 8, wherein the first region and the second region are respectively a memory cell array region and a peripheral circuit region, and the silicon layer is at least one polysilicon layer or consists of a polysilicon layer and an amorphous The silicon layers are combined, and the plurality of first gates and the plurality of second gates are gates of memory storage units and logic units respectively. 10. The semiconductor structure according to claim 8, wherein the substrate has an inclined surface located in a local interconnection region, the local interconnection region is located between the first region and the second region, and the silicon layer is further Including a third gate located in the local interconnection region, the first region of the substrate has a height difference relative to the second region, and the plurality of first gates are formed on the first region with a lower height On a region, the plurality of second gates are formed on the second region with a higher height.

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