CN103310851A - Self-repairing SRAM (Static Random Access Memory) controller design for DTMB (Digital Terrestrial Multimedia Broadcasting) demodulation chip - Google Patents
Self-repairing SRAM (Static Random Access Memory) controller design for DTMB (Digital Terrestrial Multimedia Broadcasting) demodulation chip Download PDFInfo
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Abstract
The invention discloses a self-repairing SRAM (Static Random Access Memory) controller design for a DTMB (Digital Terrestrial Multimedia Broadcasting) demodulation chip. The controller comprises an error-address storage register group, an error detection circuit, a repairing circuit, an error reporting circuit and a reading-writing control circuit, wherein the self-repairing SRAM controller design is used for storing an error conventional SRAM address; the error detection circuit is used for carrying out error detection on the conventional SRAM, and storing the detected and error address into the error-address storage register group; the repairing circuit is used for mapping the error address into a redundant SRAM when a central module accesses the error address stored in the error-address storage register group and accessing the central module to the redundant SRAM; the error reporting circuit is used for carrying out error detection on the conventional SRAM after the repairing circuit maps the error address to the redundant SRAM, and reporting errors when detecting the error address; the reading-writing control circuit is used for finishing read-writing operation of the central module to the conventional SRAM and the redundant SRAM.
Description
Technical field
The invention belongs to the DTMB digital TV field, relate in particular to a kind of selfreparing SRAM controller design for the DTMB demodulation chip.
Background technology
The main international standard of ground digital television broadcast has ATSC, the DVB-T in Europe, the ISDB-T of Japan and the DTMB standard of China of the U.S..China set up Digital Television research and development and industrialization and set up national digital TV leading group in 1999, clearly declared the autonomous technical standard of formulating.Released China digital TV ground standard DTMB (Digital Television Terrestrial Multimedia Broadcasting) in 2006.
Ground digital television receiver is finished the conversion that is input to the output of terminal audio frequency signal, vision signal demonstration from radiofrequency signal.The input radio frequency signal demand could be delivered to demultiplexing module with the transmission stream of output and carry out demultiplexing and other subsequent treatment through demodulation, channel-decoding.The DTMB demodulation chip is mainly finished demodulation, channel-decoding function.In decode procedure, need a large amount of intermediate data of storage.The storage that how to realize these intermediate data is one of design focal point of DTMB demodulation chip.In the prior art, the DTMB demodulation chip all is to adopt outside DRAM to realize the storage of these intermediate data.
There are some shortcomings in the mode of the DRAM storage intermediate data of above-mentioned employing outside: at first, chip production cost height, it needs two not costs of encapsulated naked wafers, and corresponding packaging cost is also high; Secondly, the chip encapsulation technology complexity needs pre-designed pin positions, so that mate with third-party DRAM; In addition, big capacity SRAM is easy to produce manufacturing defect in manufacture process, makes that the production yield is lower.
In view of the foregoing, need a kind of selfreparing SRAM memory storage that embeds chip internal, both can avoid the defective that manufacturing is expensive, encapsulation technology is complicated that the outside DRAM of use brings in the prior art, and can provide self-repair function again simultaneously, improve chip reliability.
Summary of the invention
The object of the present invention is to provide a kind of selfreparing SRAM controller for the DTMB demodulation chip, shortcoming such as be used for to solve that prior art adopts some production costs of outside DRAM storage intermediate data higher, encapsulation technology is complicated and chip reliability is lower.
The invention provides a kind of selfreparing SRAM controller for the DTMB demodulation chip, comprising:
Fault address storage register group is for the conventional SRAM address of memory error;
The error detector circuit is used for conventional SRAM is carried out error detector, and the fault address that detects is stored in the described fault address storage register group;
Repair circuit, be used for when center module has access to the fault address of described fault address storage register group storage, shining upon described fault address in redundant SRAM, make described center module visit described redundant SRAM;
The circuit that reports an error is used for described reparation circuit and shines upon described fault address behind redundant SRAM, described conventional SRAM is carried out error detector, and report an error when detecting fault address;
Read-write control circuit is used for finishing described center module to the read-write operation of conventional SRAM and redundant SRAM.
Preferably, described center module comprises CPU (central processing unit) (C*Core CPU) and DTMB demodulation module.
Preferably, described selfreparing SRAM controller, conventional SRAM and redundant SRAM all are positioned at the DTMB demodulation chip inside based on CPU (central processing unit) (C*Core CPU).
Preferably, described error detector method is: after CPU (central processing unit) (C*Core CPU) write complete zero to all address spaces of conventional SRAM, whether the data of relatively reading from described address were zero one by one, and if not, then make mistakes in described address; After finishing complete zero read-write detection, after CPU (central processing unit) (C*Core CPU) write complete one to all address spaces of conventional SRAM, whether the data of relatively reading from described address were one one by one, and if not, then make mistakes in described address.
Preferably, the described circuit CPU (central processing unit) (C*Core CPU) in the center module when detecting fault address that reports an error reports an error.
Preferably, chip power reset finish after, CPU (central processing unit) (C*Core CPU) writes complete zero to conventional SRAM, the error detector circuit begins conventional SRAM is carried out error detector.
Preferably, repair circuit and shine upon described fault address behind redundant SRAM, CPU (central processing unit) (C*Core CPU) writes complete zero to all address spaces of conventional SRAM, and the circuit that reports an error begins conventional SRAM is carried out error detector.
Preferably, described conventional SRAM spatial content is 59K * 24bit, and described redundant SRAM spatial content is 256 * 24bit.
Preferably, described fault address storage register group is made up of 256 unit, and wherein, the 1-18bit of each unit is the fault address position, and 19bit is zone bit, when described zone bit is that the fault address of its corresponding unit is effective fault address for the moment.
Compared with prior art, selfreparing SRAM controller for the DTMB demodulation chip provided by the invention, solved following technical matters: at first, the design of on-chip SRAM, make the DTMB demodulation chip need not to use outside DRAM storer, can reduce system cost, avoid the encapsulation of multi-chip again, reduce packaging cost; Secondly, overcome chip in use because some element failure, caused the defective that entire chip can't operate as normal, integrated by selfreparing SRAM controller can remedy this type of defective, improves chip reliability; Simultaneously, because big capacity SRAM is easy to produce manufacturing defect in manufacture process, the function by selfreparing can remedy these manufacturing defect as far as possible, and the chip that major part should be scrapped can normally use, and has improved the production yield of chip.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Shown in Figure 1 is DTMB demodulation chip structural representation provided by the invention;
Shown in Figure 2 is the selfreparing SRAM controller architecture synoptic diagram for the DTMB demodulation chip provided by the invention;
Shown in Figure 3 is error detector circuit error detector method flow diagram provided by the invention;
Shown in Figure 4 is reparation circuit restoring method process flow diagram provided by the invention;
Shown in Figure 5 is the circuit that the reports an error provided by the invention process flow figure that reports an error.
Embodiment
Hereinafter will describe the present invention with reference to the accompanying drawings and in conjunction with the embodiments in detail.Need to prove that under the situation of not conflicting, embodiment and the feature among the embodiment among the application can make up mutually.
Shown in Figure 1 is DTMB demodulation chip structural representation provided by the invention.As shown in Figure 1, DTMB demodulation chip provided by the invention comprises center module 1, selfreparing SRAM controller 4, conventional SRAM5 and redundant SRAM6, and wherein said center module 1 comprises CPU (central processing unit) 2(C*Core CPU) and DTMB demodulation module 3.
In this, described CPU (central processing unit) 2(C*Core CPU) be that Chinese C Core Technology (Suzhou) Co., Ltd. releases, have the general microcontroller processor of independent intellectual property right.
Particularly, CPU (central processing unit) 2(C*Core CPU) is used for control DTMB demodulation module 3 and selfreparing SRAM controller 4, can also open and close error detector function, the repair function of described selfreparing SRAM controller 4, and the warning message of accepting described selfreparing SRAM controller 4.
DTMB demodulation module 3 is used for the terrestrial DTV radiofrequency signal that receives is carried out demodulation, utilizes conventional SRAM5 as the storage of intermediate data in demodulating process.
Conventional SRAM5 is used for the normal visit storage of center module 1 data, and its spatial content is 59K * 24bit; Redundant SRAM6 is used for repairing the SRAM that makes mistakes, and its spatial content is 256 * 24bit.
Shown in Figure 2 is the selfreparing SRAM controller architecture synoptic diagram for the DTMB demodulation chip provided by the invention.As shown in Figure 2, selfreparing SRAM controller 4 provided by the invention comprises fault address storage register group 10, error detector circuit 20, reparation circuit 30, circuit 40 and read-write control circuit 50 report an error.
Particularly, described selfreparing SRAM controller 4 has error detector, mistake reparation and the function that reports an error.If on-chip SRAM is owing to making or other reason causes partial fault, described selfreparing SRAM controller 4 is by CPU (central processing unit) 2(C*Core CPU) can detect it after starting and whether make mistakes and fault address; When the visit of the 1 pair of on-chip SRAM of center module, selfreparing SRAM controller 4 can be to the error unit reparation, guarantees that the data that described center module 1 has access to from on-chip SRAM are correct.Simultaneously the function that reports an error of selfreparing SRAM controller 4 modules can be when detecting error unit and exceed repair coverage and maybe can't repair, give CPU (central processing unit) 2(C*Core CPU) send false alarm information, make the user learn entire chip cisco unity malfunction this moment.
In this, fault address storage register group 10 is made up of 256 unit, and wherein, the 1st～18bit of each unit is the fault address position, and 19bit is zone bit, when described zone bit is that the fault address of its corresponding unit is effective fault address for the moment.
In the present embodiment, read-write control circuit 50 is used for finishing the control from the read-write operation of 1 couple of conventional SRAM5 of center module and redundant SRAM6.
Below in conjunction with Fig. 3～Fig. 5 the workflow of each circuit module in the selfreparing SRAM controller provided by the invention is launched to describe in detail.
Shown in Figure 3 is error detector circuit error detector method flow diagram provided by the invention.As shown in Figure 3, error detector circuit error detector method provided by the invention comprises step 101～104.
Step 101: after CPU (central processing unit) (C*Core CPU) write complete zero to conventional SRAM, whether error detector circuit judges sense data was zero.
Particularly, chip power reset finish after, CPU (central processing unit) (C*Core CPU) writes complete zero to conventional SRAM, the error detector circuit begins conventional SRAM is carried out error detector, judges namely whether read data from the current address is zero.
Step 102: if not, described error detector circuit stores fault address in the fault address storage register into, and executive address is from increasing complete zero detection of continuation, until finishing whole conventional SRAM spacescans.
Particularly, be zero if described error detector circuit is read data from the current address, then executive address continues zero to survey entirely from increasing, until the scanning of finishing whole conventional SRAM address spaces.
Step 103: after CPU (central processing unit) (C*Core CPU) write complete one to conventional SRAM, whether error detector circuit judges sense data was one.
As mentioned above, after finishing complete zero detection, the error detector circuit begins a full detection.
Step 104: if not, described error detector circuit stores fault address in the fault address storage register into, and executive address is from increasing the full detection of continuation, until finishing whole conventional SRAM spacescans.
Particularly, be one if described error detector circuit is read data from the current address, then executive address continues a full detection from increasing, until the scanning of finishing described whole conventional SRAM address spaces.
Shown in Figure 4 is reparation circuit restoring method process flow diagram provided by the invention.As shown in Figure 4, reparation circuit restoring method provided by the invention comprises step 201～202.
Step 201: when center module is visited conventional SRAM, repair the reference address of the described center module of circuit judges and whether in fault address storage register group, store.
Particularly, if the reference address of center module is not stored in the described fault address storage register group, then described center module normally removes to visit conventional SRAM.
Step 202: if described reparation circuit mapping fault address makes described center module visit described redundant SRAM in redundant SRAM.
Particularly, if repairing the reference address of circuit judges center module has been stored in the described fault address storage register group, illustrate that this address is fault address, described reparation circuit is mapped to described fault address among the redundant SRAM, makes described center module visit described redundant SRAM.
Shown in Figure 5 is the circuit that the reports an error provided by the invention process flow figure that reports an error.As shown in Figure 5, the circuit that the reports an error provided by the invention disposal route that reports an error comprises step 301～303.
Step 301: described reparation circuit shines upon described fault address behind redundant SRAM, and CPU (central processing unit) (C*Core CPU) writes complete zero to conventional SRAM, and whether the circuit judges that reports an error sense data is zero.
Particularly, after the reparation circuit was finished reparation, the circuit that reports an error began that conventional SRAM is begun complete zero and surveys.It is non-vanishing that circuit is read data in the current address if report an error, and illustrates that described current address is fault address, then reports an error to CPU (central processing unit) (C*Core CPU), and withdraw from the treatment scheme that reports an error.
Step 302: if, repair the circuit executive address from increasing after finishing whole address scans, CPU (central processing unit) (C*Core CPU) writes complete one to conventional SRAM, and whether the circuit judges that reports an error sense data is one.
As mentioned above, if the reparation circuit is finished complete zero of conventional SRAM is surveyed, then begin a full detection.
Step 303: if not, the described circuit that reports an error reports an error to described CPU (central processing unit) (C*Core CPU), and withdraws from the treatment scheme that reports an error.
Particularly, when the circuit that reports an error was found fault address in a full detection process, (C*Core CPU) reported an error to CPU (central processing unit), and withdraws from the treatment scheme that reports an error.
In sum, selfreparing SRAM controller for the DTMB demodulation chip provided by the invention by the setting of on-chip SRAM, makes the DTMB demodulation chip need not to use outside DRAM storer, avoid the encapsulation of multi-chip, reduced encapsulation and system cost simultaneously.In addition, the whole difficult problem of scrapping that some element failure causes in the chip use has been avoided in the design of controller self-repair function, can improve the reliability of entire chip; Make chip simultaneously in manufacturing process, produce yield and be greatly improved.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments herein.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments herein.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (9)
1. a selfreparing SRAM controller is characterized in that, comprising:
Fault address storage register group is for the conventional SRAM address of memory error;
The error detector circuit is used for conventional SRAM is carried out error detector, and the fault address that detects is stored in the described fault address storage register group;
Repair circuit, be used for when center module has access to the fault address of described fault address storage register group storage, shining upon described fault address in redundant SRAM, make described center module visit described redundant SRAM;
The circuit that reports an error is used for described reparation circuit and shines upon described fault address behind redundant SRAM, described conventional SRAM is carried out error detector, and report an error when detecting fault address;
Read-write control circuit is used for finishing described center module to the read-write operation of conventional SRAM and redundant SRAM.
2. SRAM controller according to claim 1 is characterized in that, described center module comprises CPU (central processing unit) (C*Core CPU) and DTMB demodulation module.
3. SRAM controller according to claim 1 and 2 is characterized in that, described selfreparing SRAM controller, conventional SRAM and redundant SRAM all are positioned at the DTMB demodulation chip inside based on CPU (central processing unit) (C*Core CPU).
4. SRAM controller according to claim 1 and 2, it is characterized in that, described error detector method is: after CPU (central processing unit) (C*Core CPU) writes complete zero to all address spaces of conventional SRAM, whether the data of relatively reading from described address are zero one by one, if not, then make mistakes in described address; After finishing complete zero read-write detection, after CPU (central processing unit) (C*Core CPU) write complete one to all address spaces of conventional SRAM, whether the data of relatively reading from described address were one one by one, and if not, then make mistakes in described address.
5. SRAM controller according to claim 1 and 2 is characterized in that, the described circuit CPU (central processing unit) (C*Core CPU) in the center module when detecting fault address that reports an error reports an error.
6. SRAM controller according to claim 1 and 2 is characterized in that, chip power reset finish after, CPU (central processing unit) (C*Core CPU) writes complete zero to conventional SRAM, the error detector circuit begins conventional SRAM is carried out error detector.
7. SRAM controller according to claim 1 and 2, it is characterized in that, repair circuit and shine upon described fault address behind redundant SRAM, CPU (central processing unit) (C*Core CPU) writes complete zero to all address spaces of conventional SRAM, and the circuit that reports an error begins conventional SRAM is carried out error detector.
8. SRAM controller according to claim 1 is characterized in that, described conventional SRAM spatial content is 59K * 24bit, and described redundant SRAM spatial content is 256 * 24bit.
9. SRAM controller according to claim 1, it is characterized in that, described fault address storage register group is made up of 256 unit, wherein, the 1-18bit of each unit is the fault address position, 19bit is zone bit, when described zone bit is that the fault address of its corresponding unit is effective fault address for the moment.
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| CN104833376A (en) * | 2015-04-24 | 2015-08-12 | 中国人民大学 | Self-repairing sensing chip and preparation method thereof |
| CN110785811A (en) * | 2017-08-10 | 2020-02-11 | 美光科技公司 | Shared address counter for multiple operating modes in a memory device |
| TWI711036B (en) * | 2020-01-22 | 2020-11-21 | 大陸商珠海南北極科技有限公司 | Repair circuit of memory and method thereof |
| CN114639439A (en) * | 2022-04-08 | 2022-06-17 | 北京得瑞领新科技有限公司 | Chip internal SRAM test method and device, storage medium and SSD device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104833376A (en) * | 2015-04-24 | 2015-08-12 | 中国人民大学 | Self-repairing sensing chip and preparation method thereof |
| CN110785811A (en) * | 2017-08-10 | 2020-02-11 | 美光科技公司 | Shared address counter for multiple operating modes in a memory device |
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| TWI711036B (en) * | 2020-01-22 | 2020-11-21 | 大陸商珠海南北極科技有限公司 | Repair circuit of memory and method thereof |
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| CN114639439A (en) * | 2022-04-08 | 2022-06-17 | 北京得瑞领新科技有限公司 | Chip internal SRAM test method and device, storage medium and SSD device |
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