CN103300844A - Twelve-lead electrocardiosignal synchronous acquisition module - Google Patents

Abstract

A twelve-lead electrocardiogram synchronous acquisition module, which belongs to the technical field of medical equipment, solves the problems of inconvenient detection and high cost of measurement equipment that the existing twelve-lead electrocardiogram adopts wired measurement, including sequentially connected body surface electrodes , ECG signal input circuit, differential amplification circuit, filter circuit, lead selection circuit, signal amplification circuit, analog-to-digital conversion circuit, single-chip computer and level conversion circuit. When in use, the acquisition module of the present invention is connected to the serial port to WIFI module, and then wirelessly connected to the computer to form a low-cost household 12-lead electrocardiogram wireless measurement system to realize the home wireless measurement of the electrocardiogram, thereby making the electrocardiogram detection convenient. And the detection equipment cost is low.

Description

A twelve-lead electrocardiographic signal synchronous acquisition module

technical field

The invention belongs to the technical field of medical equipment, in particular to an electrocardiographic signal acquisition device.

Background technique

Twelve-lead ECG detection is an important means of heart function and heart disease diagnosis. The existing 12-lead electrocardiogram adopts wired measurement, which makes the detection inconvenient and the price of the measuring equipment is high, so that the measurement of the 12-lead electrocardiogram can only be completed in the hospital.

Contents of the invention

In order to solve the problem that the existing twelve-lead electrocardiogram adopts wired measurement, the detection is inconvenient and the cost of the measurement equipment is high, the present invention provides a twelve-lead electrocardiogram synchronous acquisition module, and its technical scheme is as follows:

A twelve-lead ECG signal synchronous acquisition module:

It includes sequentially connected body surface electrodes, electrocardiographic signal input circuit, differential amplifier circuit, filter circuit, lead selection circuit, signal amplifier circuit, analog-to-digital conversion circuit, single-chip computer and level conversion circuit.

As a preferred version of the inventive method:

The body surface electrodes include right foot RF electrode, left foot LF electrode, left hand L electrode, right hand R electrode, and electrode V1, electrode V2, electrode V3, electrode V4, electrode V5 and electrode V6, wherein the right foot electrode RF ground terminal ;

The electrocardiographic signal input circuit includes four operational amplifiers LM324, and resistance R101, resistance R102, resistance R103, resistance R104, resistance R105, resistance R106, resistance R107, resistance R108 and resistance R109, and Wilson network;

Among them, the Wilson network includes a star connection composed of resistors R116, R117 and R118 with a resistance value of 30K ohms. The inner end of the resistor R116, the inner end of the resistor R117 and the inner end of the resistor R118 are connected together. Constitute the center point of the Wilson network; the resistance R110 and the resistance R111 are connected in series between the outer end of the resistance R116 and the outer end of the resistance R117, and the resistance R115 is connected in series between the outer end of the resistance R116 and the outer end of the resistance R118 Resistor R112 and resistor R113 are sequentially connected in series between the outer terminal of resistor R114 and the outer terminal of resistor R118; resistor R110, resistor R111, resistor R112, resistor R113, resistor R114 and resistor R115 form a delta connection; resistor The resistance values of R110, resistor R111, resistor R112, resistor R113, resistor R114 and resistor R115 are all 20K ohms;

Among them, the four operational amplifier LM324 includes the first operational amplifier, the third operational amplifier and the fourth operational amplifier; the VCC terminal of the four operational amplifier LM324 is connected to the +5V power supply, and the VEE terminal of the four operational amplifier LM324 is connected to the -5V power supply; the left foot LF electrode is connected to the The non-inverting input terminal of the fourth operational amplifier is connected, and the inverting input terminal of the fourth operational amplifier is connected with the output terminal of the fourth operational amplifier to form a left foot LF voltage follower; the left-hand L electrode is connected with the non-inverting input terminal of the third operational amplifier , the inverting input terminal of the third operational amplifier is connected with the output terminal of the third operational amplifier to form a left-hand L voltage follower; the right-hand R electrode is connected with the non-inverting input terminal of the first operational amplifier, and the inverting input terminal of the first operational amplifier Connect with the output terminal of the first operational amplifier to form a right-hand R voltage follower; the right-hand R voltage follower is connected to the outer terminal of the resistor R118, the left-foot LF voltage follower is connected to the outer terminal of the resistor R116, and the left-hand L voltage follower The device is connected to the outer end of the resistor R117;

The differential amplifier circuit includes twelve data amplifiers AD620, which are respectively U201, U202, U203, U204, U205, U206, U207, U208, U209, U210, U211 and U212; the 5 pins of the data amplifier U201, the data amplifier U202 5 pins of data amplifier U203, 5 pins of data amplifier U204, 5 pins of data amplifier U205, 5 pins of data amplifier U206, 5 pins of data amplifier U207, 5 pins of data amplifier U208 The pins, the 5 pins of the data amplifier U209, the 5 pins of the data amplifier U210, the 5 pins of the data amplifier U211 and the 5 pins of the data amplifier U212 are all ground terminals;

Among them, the electrode V1 is connected to the non-inverting input terminal of the data amplifier U206 after passing through the resistor R106, the electrode V2 is connected to the non-inverting input terminal of the data amplifier U205 after passing through the resistor R105, and the electrode V3 is connected to the non-inverting input terminal of the data amplifier U204 after passing through the resistor R104. V4 is connected to the non-inverting input terminal of the data amplifier U203 through the resistor R103, the electrode V5 is connected to the non-inverting input terminal of the data amplifier U202 after passing through the resistor R102, and the electrode V6 is connected to the non-inverting input terminal of the data amplifier U201 after passing through the resistor R101; the data amplifier U201 The inverting input terminal of the data amplifier U202, the inverting input terminal of the data amplifier U203, the inverting input terminal of the data amplifier U204, the inverting input terminal of the data amplifier U205 and the inverting input terminal of the data amplifier U206 Both are connected to the central point of the Wilson network;

Among them, the non-inverting input terminal of the data amplifier U207 is connected to the left-hand LF voltage follower after passing through the resistor R107, and the inverting input terminal of the data amplifier U207 is connected to the left-hand L voltage follower after passing through the resistor R108; Connect the right-hand R voltage follower, the inverting input terminal of the data amplifier U208 is connected to the Wilson zero potential point between the resistor R110 and the resistor R111; the non-inverting input terminal of the data amplifier U209 is connected to the left foot LF voltage follower through the resistor R107, The inverting input terminal of the amplifier U209 is connected to the right-hand R voltage follower through the resistor R109; the non-inverting input terminal of the data amplifier U210 is connected to the left foot LF voltage follower after passing through the resistor R107, and the inverting input terminal of the data amplifier U210 is connected to the resistor R112 and the resistor R112 The Wilson zero potential point between R113 is connected; the noninverting input terminal of the data amplifier U211 is connected to the left-hand L voltage follower after passing through the resistor R108, and the inverting input terminal of the data amplifier U211 is connected to the right-hand R voltage follower after passing through the resistor R109; the data amplifier U212 The non-inverting input terminal of the data amplifier U212 is connected to the Wilson zero potential point between the resistor R114 and the resistor R115 after being connected to the left-hand L voltage follower through the resistor R108;

The filter circuit includes twelve bandpass filters, each of which includes a first-order RC high-pass filter with a cutoff frequency of 0.16 Hz connected to the output of the data amplifier, and the output of the first-order RC high-pass filter The end is connected with a first-order RC low-pass filter with a cutoff frequency of 106Hz;

The lead selection circuit includes an analog electronic switch U301, an analog electronic switch U302, and an inverter composed of a triode T301, a resistor R301 and a resistor R302; both the analog electronic switch U301 and the analog electronic switch U302 are multi-way selector switches KCF4051BE; Transistor T301 is triode C1815; VDD terminal of analog electronic switch U301 is connected to +5V power supply; VDD terminal of analog electronic switch U302 is connected to +5V power supply; VSS terminal of analog electronic switch U301 is grounded; VEE terminal of analog electronic switch U301 is connected to -5V Power supply; the VSS terminal grounding terminal of the analog electronic switch U302; the VEE terminal of the analog electronic switch U302 is connected to the -5V power supply; the resistance value of the resistance R301 is 22K ohms, the resistance value of the resistance R302 is 1M ohms, and the inner terminal of the resistance R301 is connected to the The collector of the transistor T301 is connected, the outer terminal of the resistor R301 is connected to the +5V power supply; the inner terminal of the resistor R302 is connected to the base of the transistor T301; the collector of the transistor T301 is connected to the chip selection terminal INH of the analog electronic switch U301, and the transistor T301 The emitter ground terminal;

Wherein the output terminal of the data amplifier U201 is connected to the X3 terminal of the analog electronic switch U301 after the output terminal of the data amplifier U201 passes through a described band-pass filter; after the output terminal of the data amplifier U202 passes through a described band-pass filter, the output signal V5 is connected to to the X2 terminal of the analog electronic switch U301; after the output terminal of the data amplifier U203 passes through a said band-pass filter, the output signal V4 is connected to the X1 terminal of the analog electronic switch U301; the output terminal of the data amplifier U204 passes through a said band-pass filter After the filter, the output signal V3 is connected to the X0 end of the analog electronic switch U301; the output signal V2 of the data amplifier U205 is connected to the X7 end of the analog electronic switch U302 after the output end of the data amplifier U205 passes through a described band-pass filter; After the output terminal passes through one of the band-pass filters, the output signal V1 is connected to the X6 terminal of the analog electronic switch U302; after the output terminal of the data amplifier U207 passes through one of the above-mentioned band-pass filters, the output signal III is connected to the analog electronic switch U302 X2 end of the data amplifier U208; the output signal aVR of the data amplifier U208 is connected to the X3 end of the analog electronic switch U302 after passing through a said band-pass filter; Signal II is connected to the X1 end of the analog electronic switch U302; after the output end of the data amplifier U210 is passed through a said band-pass filter, the output signal aVF is connected to the X5 end of the analog electronic switch U302; the output end of the data amplifier U211 is passed through a said After the band-pass filter, the output signal I is connected to the X0 end of the analog electronic switch U302; the output signal aVL of the data amplifier U212 is connected to the X4 end of the analog electronic switch U302 after passing through one of the band-pass filters;

Wherein the A end of the analog electronic switch U301 and the A end of the analog electronic switch U302 are connected to the P1.0 end of the unit chip AT89C2051; the B end of the analog electronic switch U301 and the B end of the analog electronic switch U302 are connected to the unit The P1.1 terminal of the chip computer AT89C2051; the C terminal of the analog electronic switch U301 and the C terminal of the analog electronic switch U302 are connected to the P1.2 terminal of the unit chip computer AT89C2051; the outer terminal of the resistor R302 is connected to the analog electronic switch U302 The chip selection terminal INH, the P1.3 terminal of the unit chip AT89C2051;

Described signal amplifying circuit comprises data amplifier U303, and data amplifier U303 is data amplifier AD620; The potentiometer R303 that resistance value is 1K ohm is connected between the 1 pin of data amplifier U303 and 8 pins; The same phase input end of data amplifier U303 is connected The output terminal X of the analog electronic switch U301, the output terminal X of the analog electronic switch U302, the ground terminal of the inverting input terminal of the data amplifier U303, the output terminal of the data amplifier U303 is connected to the input terminal AIN0 of the A/D converter TLC2543; the data amplifier Pin 7 of U303 is connected to +5V power supply, pin 4 of data amplifier U303 is connected to -5V power supply; pin 5 of data amplifier U303 is connected to the positive pole of diode D301, the negative pole of diode D301 is connected to the positive pole of diode D302, and the negative pole of diode D302 is connected to The positive pole of the diode D303, the negative pole of the diode D303 is connected to the positive pole of the diode D304, and the negative pole of the diode D304 is grounded; the 5 pin of the data amplifier U303 is connected to a resistor R304 with a resistance value of 22K ohms, and the other end of the resistor R304 is connected to a +5V power supply; The output terminal of the amplifier U303 is connected to the cathode of the diode D305, and the anode of the diode D305 is grounded;

The analog-to-digital conversion circuit includes a serial A/D converter TLC2543, AIN1 end, AIN2 end, AIN3 end, AIN4 end, AIN5 end, AIN6 end, AIN7 end, AIN8 end, AIN9 end of A/D converter TLC2543, AIN10 terminal, negative reference voltage terminal REF- and GND terminal are all ground terminals; the VDD terminal of A/D converter TLC2543 is connected to +5V power supply; the synchronous clock terminal SCLK of A/D converter TLC2543 is connected to the unit chip AT89C2051 P1.4 terminal, the serial data input terminal DIN of the A/D converter TLC2543 is connected to the P1.5 terminal of the unit chip AT89C2051, and the serial data output terminal DOUT of the A/D converter TLC2543 is connected to the unit The P1.6 terminal of the chip computer AT89C2051, the chip selection terminal CS of the A/D converter TLC2543 is connected to the P1.7 of the unit chip computer AT89C2051; one end of the resistor R401 with a resistance value of 1K ohms is connected to the +5V power supply, and the resistor R401 The other end of the A/D converter TLC2543 is connected to the positive reference voltage terminal REF+; between the positive reference voltage terminal REF+ of the A/D converter TLC2543 and the ground terminal, a sliding resistor R402 with a resistance value of 5K ohms and a resistance value of The 4.7K ohm resistor R403, the 3 pins of the voltage regulator tube TL431 are connected to the positive reference voltage terminal REF+, the 1 pin of the voltage regulator tube TL431 is connected between the sliding resistor R402 and the resistor R403, the 2 pins of the voltage regulator tube TL431 are grounded end;

Described single-chip computer comprises described unit chip AT89C2051, is provided with reset circuit on the unit chip AT89C2051, and described reset circuit comprises the electric capacity C401 that is connected between the VCC end of unit chip AT89C2051 and the RST end, reset key K401 One end is connected to the VCC terminal of the unit chip AT89C2051, the other end of the reset key K401 is connected to the resistor R404, the other end of the resistor R404 is connected to the RST terminal of the unit chip AT89C2051, one end of the resistor R405 is connected to the RST terminal of the unit chip AT89C2051, and the resistor R405 is connected to the RST terminal of the unit chip AT89C2051. The other end is grounded; the unit chip AT89C2051 is provided with an oscillating circuit, which includes a crystal oscillator X401 connected between the XTL2 end and the XTL1 end of the unit chip AT89C2051, the frequency of the crystal oscillator X401 is 11.0592MHz, and the XTL2 end and XTL1 Capacitor C402 and capacitor C403 are also connected in series between the terminals, and the ground terminal between capacitor C402 and capacitor C403; the P1.1 terminal of the unit chip AT89C2051 is connected to the pull-up resistor R406, and the other end of the pull-up resistor R406 is connected to the +5V power supply ; The P1.0 terminal of the unit chip AT89C2051 is connected to the pull-up resistor R407, and the other end of the pull-up resistor R407 is connected to the +5V power supply; the GND terminal of the unit chip AT89C2051 is grounded;

Described level conversion circuit comprises level conversion circuit and RS232C interface, and level conversion circuit comprises level conversion chip MAX232, and capacitance C404, capacitance C405, capacitance C406 and capacitance C407 that capacitance value is 1 microfarad; Capacitor C404 One end is connected to +5V power supply, and the other end of capacitor C404 is connected to pin 2 of level conversion chip MAX232; capacitor C405 is connected between pin 1 and pin 3 of level conversion chip MAX232; pin 4 of level conversion chip MAX232 Connect capacitor C406 between pin 5 and pin 5; connect capacitor C407 between pin 6 and pin 8 of level conversion chip MAX232; pin 8 and pin 10 of level conversion chip MAX232 are grounded; level conversion chip MAX232 The 11 pins of the unit chip AT89C2051 are connected to the TXD end of the unit chip, the 14 pins of the level conversion chip MAX232 are connected to the RXD end of the RS232C interface; the TXD end of the RS232C interface is connected to the 13 pins of the level conversion chip MAX232 12 pins of the level conversion chip MAX232 are connected to the RXD end of the unit chip AT89C2051; 16 pins of the level conversion chip MAX232 are connected to the +5V power supply; the GND end of the RS232C interface is grounded.

When in use, the acquisition module of the present invention is connected to the serial port to WIFI module, and the serial port to WIFI module is wirelessly connected to a computer to form a low-cost household 12-lead electrocardiogram wireless measurement system to realize home wireless measurement of the electrocardiogram.

The invention solves the problems of ECG signal detection, ECG signal digitization and ECG signal external transmission, provides a low-cost twelve-lead ECG signal detection module, and realizes twelve-lead ECG signal detection module. The functions of synchronous detection, digitization of analog signals and external transmission of digital signals through the serial port make the detection of the twelve-lead electrocardiogram convenient, and the cost of the detection equipment is low.

The working process of the system of the present invention is as follows:

1. When the module is powered on, it is in the waiting command state;

2. When the module receives the command from the serial port, it decides to continue to wait or execute the 12-lead ECG signal detection work according to the command: when the command is "#00H", continue to wait; when the command is "#01H～#0FFH", respectively Perform twelve-lead ECG data acquisition with different data volumes;

3. Collection process: collect 1 byte -> transmit 1 byte -> collect 1 byte -> transmit 1 byte...;

4. The data collected each time and sent through the serial port is a one-dimensional array that is arranged sequentially with each lead of "V6, I, II, III, aVR, aVL, aVF, V1, V2, V3, V4, V5" as a cycle;

5. The time taken to collect and send each byte through the serial port is 260.0μs (measured value).

Concrete technical effect of the present invention is as follows:

1. A voltage follower composed of a general-purpose operational amplifier is used as the buffer stage of the left foot LF, left hand L, and right hand R leads, which greatly reduces the output resistance of the three leads, so that it can drive the Wilson network well and improve the unipolar chest. Accuracy of lead ECG signal measurement.

2. The general-purpose data amplifier AD620 is used to differentially amplify the signals of each lead to simplify the circuit and reduce the cost.

3. The first-order RC passive bandpass filter is used to perform DC blocking filtering and anti-aliasing filtering on the differentially amplified lead signals, which reduces the complexity of the circuit on the premise of ensuring that the ECG signal can be sampled correctly (more refined filtering is left to more economical digital filter processing).

4. Under the control of the single-chip microcomputer, the analog electronic switch is used to gate the signals of each lead in turn, and the synchronization requirements of the signal measurement of each lead are met (the delay of adjacent leads is 0.26ms, and the maximum delay between leads is 3.21ms, which is far less than The duration of QRS complex is 60ms, and it can also be adjusted by software to display a fully synchronized 12-lead ECG), which simplifies the circuit design.

5. A general-purpose data amplifier is used to moderately amplify the selected lead signal. The magnification is adjusted between +200 and +500 times, which not only ensures the measurement accuracy, but also simplifies the circuit design.

6. Under the control of the single-chip computer AT89C2051, the controllable data collection is carried out: ① waiting for the command from the serial port; ② deciding whether to carry out data collection and how much data to collect continuously according to the serial port command.

7. Continuous data acquisition: select a lead under the control of the single-chip microcomputer, perform A/D conversion on the selected lead, and send the conversion result through the RS232C serial port; select the next lead and perform A/D conversion and serial port data on it Send; ... ; Repeat the above process with 12 leads as a cycle until the required amount of data collection is completed.

Description of drawings

Fig. 1 is the circuit diagram of a kind of 12-lead electrocardiogram synchronous acquisition module of the present invention;

FIG. 2 is an algorithm design diagram of a twelve-lead electrocardiographic signal synchronous acquisition module in FIG. 1 .

Detailed ways

A twelve-lead electrocardiographic signal synchronous acquisition module as shown in Figure 1 is composed of the following circuits:

1. Hardware Circuit Composition

1.1 ECG signal input part

ECG signal input part is composed of LM324 and R101-R118.

ECG signals come from the body surface. Electrocardiographic signals are obtained through nine surface electrodes of the left foot LF, left hand L, right hand R, and V1, V2, V3, V4, V5, and V6. The right foot electrode RF is connected to the ground terminal of the entire acquisition module.

The six electrode signals of V1 ~ V6 are respectively connected to the differential amplification part through six 10K resistors of R106 ~ R101.

The three electrode signals of the left foot LF, the left hand L and the right hand R are respectively connected to the non-inverting input terminals of the three operational amplifiers of the LM324; the inverting input terminals of each operational amplifier are respectively connected to their own output terminals to form a voltage follower; from the voltage follower The left foot LF, left hand L and right hand R signals are respectively connected to the Wilson network and the differential amplification part; resistors R110~R118 form the Wilson network to provide zero potential points for unipolar chest leads and unipolar limb leads; each zero point of the Wilson network The potential points are respectively connected to the differential amplification section.

The LM324 is powered by ±5V dual power supplies.

1.2 Differential amplification part

The differential amplification part is composed of data amplifiers U201-U212.

The six electrode signals of V1～V6 are respectively connected to the non-inverting input terminals of the data amplifier U206～U201 through the six 10K resistors R106～R101, and the inverting input terminals of U206～U201 are connected to the central point of the Wilson network; the non-inverting input terminals of U207～U212 The terminals are respectively connected to the left foot LF voltage follow signal, right hand R voltage follow signal, left foot LF voltage follow signal, left foot LF voltage follow signal, left hand L voltage follow signal, left hand L voltage follow signal, and the inverting input terminals of U207~U212 Connect the left-hand L voltage following signal, Wilson zero potential point, right-hand R voltage following signal, Wilson zero potential point, right-hand R voltage following signal, Wilson zero potential point; the output terminals of data amplifiers U201~U212 respectively output V6~V1, III , aVR, II, aVF, I, aVL lead differential amplification signal, the amplification factor is +1; U201 ~ U212 use general data amplifier AD620, ± 5V dual power supply.

1.3 Filtering part

The filtering part is composed of C201~C224, R201~R224.

C201～C212, R201～R212 form twelve first-order RC high-pass filters, the cutoff frequency is 0.16Hz; C213～C224, R213～R224 form twelve first-order RC low-pass filters, the cutoff frequency is 106Hz; The high-pass and low-pass filters together form twelve band-pass filters, and the pass-band frequency is 0.16Hz to 106Hz.

1.4 Lead selection part

The lead selection part is composed of analog electronic switches U301, U302, triode T301, resistors R301, R302.

The analog electronic switches U301 and U302 use 8-to-1 multi-channel selection switch KCF4051BE to select each lead. The chip selection of the two electronic analog switches is realized by an inverter composed of a triode C1815. The input resistance of the inverter adopts 1M large resistor, the purpose is to reduce the control current of the microcontroller AT89C2051 control terminal P1.3.

The lead signals I, II, III, aVR, aVL, aVF, V1, V2 from the filter are respectively connected to the input selection terminals X0~X7 of U302, and V3~V6 are respectively connected to the input selection terminals X0~X3 of U301; The channel selection switch KCF4051BE (U301, U302) adopts ±5V dual power supply, the chip selection terminal INH is active at low level, and the chip selection signal comes from the control terminal P1.3 of the microcontroller AT89C2051; To the P1.0, P1.1, P1.2 terminals of the unit chip AT89C2051, P1.3 is connected to the chip selection terminal INH of U302, and connected to the chip selection terminal of U301 after the inverter composed of R301, T301 and R302 INH is connected.

1.5 Signal amplification part

The signal amplification part is composed of data amplifier U303, potentiometer R303, resistor R304 and diodes D301~D305.

实际采用值为A_u＝+500）；AD620的同相输入端接U301及U302的输出端X，反相输入端接地端，输出端接到A/D转换器TLC2543的输入端AIN0；AD620采用±5V双电源供电；电阻R304、二极管D301～D304组成+2.4V钳位电路，目的是使输出的心电信号为正电压，以满足A/D转换器TLC2543的输入要求；二极管D305是A/D转换器TLC2543的输入端保护二极管，确保TLC2543的输入端电压在-0.6V以上。U303 adopts data amplifier AD620, and adjusting potentiometer R303 can obtain the required magnification (

The actual value used is A _u = +500); the non-inverting input terminal of AD620 is connected to the output terminal X of U301 and U302, the inverting input terminal is grounded, and the output terminal is connected to the input terminal AIN0 of the A/D converter TLC2543; AD620 uses ± 5V dual power supply; resistor R304, diode D301 ~ D304 form a +2.4V clamping circuit, the purpose is to make the output ECG signal a positive voltage to meet the input requirements of the A/D converter TLC2543; diode D305 is the A/D The input terminal protection diode of the converter TLC2543 ensures that the input terminal voltage of the TLC2543 is above -0.6V.

1.6A/D conversion part

A/D conversion part is made up of U401, U402, R401- 403.

The A/D conversion adopts the serial A/D converter TLC2543 (U401), the ECG signals of each lead are input from the AIN0 terminal, AIN1～AIN10 and the negative reference voltage terminal REF- are grounded, the regulator tube TL431 (U402) and the resistor R401～403 form a voltage regulator circuit to provide +4.00V standard voltage for the positive reference voltage terminal REF+; the synchronous clock terminal SCLK, serial data input terminal DIN, serial data output terminal DOUT and chip select terminal CS of TLC2543 are respectively connected with the single chip AT89C2051 P1.4, P1.5, P1.6, P1.7 are connected; the working voltage of TLC2543 is +5V.

1.7 Single-chip computer part

The single-chip computer part is composed of single-chip computer AT89C2051 (U403), crystal oscillator X401, reset key K401, resistors R404~R407, and capacitors C401~C403.

The single-chip computer adopts the cost-effective unit chip AT89C2051 (U403) produced by ATMEL; K401, C401, R404, and R405 form the single-chip reset circuit; X401, C402, and C403 form the single-chip oscillation circuit. The frequency crystal oscillator is to obtain a more accurate serial communication baud rate; the resistors R406 and R407 are the pull-up resistors of the I/O port P1.1 and P1.0 of the microcontroller respectively.

1.8 Level conversion part

The level conversion part is composed of level conversion chip U404, capacitors C404~C407 and RS232C interface (U405).

The level conversion chip adopts MAX232, which forms a level conversion circuit with capacitors C404~C407, which is responsible for the two-way conversion between the TTL level of the single chip microcomputer and the EIA (American Electronics Industries Association) level of the RS232C interface.

1.9 Power section

The power supply uses a ±5V dual power supply (actually, eight 1.2V rechargeable batteries are used to form a ±4.8V dual power supply) to supply power to the module.

2. MCU system working mode

1.1 ECG signal lead selection control

The P1 port of the microcontroller AT89C2051 is used as a common I/O port. When the output of P1.3P1.2P1.1P1.0 is 0000～0111, select the input terminals X0～X7 of U302 respectively, that is, select the leads I, II, III, aVR, aVL, aVF, V1 and V2 respectively; when P1 When the output of .3P1.2P1.1P1.0 is 1000~1011, select the input terminals X0~X3 of U301 respectively, that is, select the leads of V3~V6 respectively; so when the output of P1.3P1.2P1.1P1.0 is 0000~1011 When selecting the lead signals of I, II, III, aVR, aVL, aVF, V1~V6 respectively, only the selected lead signals can enter the amplifying circuit and the A/D conversion circuit.

1.2A/D conversion control

Under the control of the single-chip microcomputer AT89C2051, firstly make P1.4 (that is, the SCLK terminal) low level, and then make P1.7 (that is, the CS terminal) low level, at this time, a bit A is output from the DOUT terminal to P1.6 /D conversion result (actual setting: 8-bit unsigned number, high bit first); keep P1.7 low, make P1.4 (SCLK terminal) high, at this time TLC2543 reads from DIN A command word (high bit first); keep P1.7 low, make P1.4 (that is, SCLK terminal) low, at this time TLC2543 outputs a bit of A/D conversion result from DOUT; in this way, In the case of keeping P1.7 at low level, through the level change of P1.4 terminal, TLC2543 reads in the command word and outputs the A/D conversion result from high bit to low bit until the 8-bit command word and 8 Bit A/D conversion result has been read in and outputted.

1.3 Data communication control

Under the control of single-chip microcomputer AT89C2051, every time an 8-bit A/D conversion result is read, the conversion result (one byte) is sent to the RS232C serial communication interface through MAX232; The command word is used to determine whether to start the acquisition and the number of bytes collected continuously after the start of the acquisition (the number of bytes collected continuously determines the duration of the acquisition).

1.4 MCU working mode

The serial port communication baud rate is 57600bps; the sampling data is 8-bit binary number (12 bytes/sample); when the MCU receives the command word #01H～#0FFH from the RS232C interface in the interrupt service program, the MCU continuously collects and sends to the RS232C The interface transmits 1 × 12 × 960 ~ 255 × 12 × 960 sampling data; the collection process: collect 1 byte -> transmit 1 byte -> collect 1 byte -> transmit 1 byte...; due to the A/D converter The working mode of TLC2543 is "outputting the A/D conversion data of the previous lead - reading the command word of the next lead - A/D conversion of this lead" three tasks are carried out synchronously, so the data collected and output by the MCU each time is A one-dimensional array arranged sequentially with each lead of "V6, I, II, III, aVR, aVL, aVF, V1, V2, V3, V4, V5" as a cycle, that is, array elements A0, A12, A24... are V6 The signal data of the lead, the array elements A1, A13, A25... are the signal data of the I lead, the array elements A2, A14, A26... are the signal data of the II lead, ...; the MCU receives the command word #00H , the single-chip microcomputer maintains the state of waiting for commands, and the single-chip microcomputer is also in the state of waiting for commands after it is turned on or reset.

1.5 Sampling rate test

Estimation of single-byte sampling period: From the serial port communication baud rate of 57600bps, it can be known that the serial port single-byte transmission time is 139μs, and the time required for serial A/D converter TLC2543 single-byte conversion is about 88μs, so the single-byte sampling period is about It is 227μs; because in the sampling process, in addition to the above necessary time, there are some processes such as judgment and number setting that require a certain amount of time, so the actual sampling period will be slightly longer than the estimated value.

Single-byte sampling cycle test: Through parameter setting, let the single-chip microcomputer continuously collect and transmit 255×12×960 sampling data to the RS232C interface, record the time required to complete these data collections with a stopwatch, and calculate the average time required for each byte collection Time (the measured value is 260.0μs/Byte); when the command word #02H is sent to the microcontroller, the sampling time is 5.99 seconds (about one tenth of a minute).

Claims (2)

1. 12 lead electrocardiosignal synchronous acquisition module is characterized in that:

Comprise successively the external electrode, electrocardiosignal input circuit, differential amplifier circuit, the filter circuit that connect, lead and select circuit, signal amplification circuit, analog to digital conversion circuit, one-chip computer and level shifting circuit.

2. a kind of 12 lead electrocardiosignal synchronous acquisition module according to claim 1 is characterized in that:

Described external electrode comprises right crus of diaphragm RF electrode, left foot LF electrode, left hand L electrode, right hand R electrode, and electrode V1, electrode V2, electrode V3, electrode V4, electrode V5 and electrode V6, wherein right crus of diaphragm electrode RF earth terminal;

Described electrocardiosignal input circuit comprises four-operational amplifier LM324, and resistance is resistance R 101, resistance R 102, resistance R 103, resistance R 104, resistance R 105, resistance R 106, resistance R 107, resistance R 108 and the resistance R 109 of 10K ohm, and the Wilson's network;

Wherein the Wilson's network comprises by resistance and is the Y-connection that resistance R 116, resistance R 117 and the resistance R 118 of 30K ohm consist of, the inner women's head-ornaments of the inner termination of the inner termination of resistance R 116, resistance R 117 and resistance R 118 link together, and consist of Wilson's network center point; Successively series resistor R110 and resistance R 111 between the external end head of the external end head of resistance R 116 and resistance R 117, successively series resistor R115 and resistance R 114 between the external end head of the external end head of resistance R 116 and resistance R 118, successively series resistor R112 and resistance R 113 between the external end head of the external end head of resistance R 117 and resistance R 118; Resistance R 110, resistance R 111, resistance R 112, resistance R 113, resistance R 114 are connected with resistance R and are consisted of triangle and connect; The resistance of resistance R 110, resistance R 111, resistance R 112, resistance R 113, resistance R 114 and resistance R 115 is 20K ohm;

Wherein four-operational amplifier LM324 comprises the first operational amplifier, the 3rd operational amplifier and four-operational amplifier; The VCC termination of four-operational amplifier LM324+5V power supply, the VEE termination of four-operational amplifier LM324-5V power supply; Left foot LF electrode is connected with the in-phase input end of four-operational amplifier, and the inverting input of four-operational amplifier is connected with the outfan of four-operational amplifier, forms left foot LF voltage follower; Left hand L electrode is connected with the in-phase input end of the 3rd operational amplifier, and the inverting input of the 3rd operational amplifier is connected with the outfan of the 3rd operational amplifier, forms left hand L voltage follower; Right hand R electrode is connected with the in-phase input end of the first operational amplifier, and the inverting input of the first operational amplifier is connected with the outfan of the first operational amplifier, forms right hand R voltage follower; Right hand R voltage follower is connected with the external end head of resistance R 118, and left foot LF voltage follower is connected with the external end head of resistance R 116, and left hand L voltage follower is connected with the external end head of resistance R 117;

Described differential amplifier circuit comprises 12 data amplifier AD620, is respectively U201, U202, U203, U204, U205, U206, U207, U208, U209, U210, U211 and U212; 5 pins of 5 pins of 5 pins of 5 pins of 5 pins of data amplifier U201,5 pins of data amplifier U202, data amplifier U203,5 pins of data amplifier U204, data amplifier U205,5 pins of data amplifier U206, data amplifier U207,5 pins of data amplifier U208, data amplifier U209,5 pins of data amplifier U210,5 pins of data amplifier U211 and the equal earth terminal of 5 pins of data amplifier U212;

Wherein electrode V1 is connected to the in-phase input end of data amplifier U206 after resistance R 106, electrode V2 is connected to the in-phase input end of data amplifier U205 after resistance R 105, electrode V3 is connected to the in-phase input end of data amplifier U204 after resistance R 104, electrode V4 is connected to the in-phase input end of data amplifier U203 after resistance R 103, electrode V5 is connected to the in-phase input end of data amplifier U202 after resistance R 102, electrode V6 is connected to the in-phase input end of data amplifier U201 after resistance R 101; The inverting input of the inverting input of the inverting input of the inverting input of the inverting input of the inverting input of data amplifier U201, data amplifier U202, data amplifier U203, data amplifier U204, data amplifier U205 and data amplifier U206 all is connected to Wilson's network center point;

Wherein the in-phase input end of data amplifier U207 connects left foot LF voltage follower after resistance R 107, and the inverting input of data amplifier U207 connects left hand L voltage follower after resistance R 108; The in-phase input end of data amplifier U208 connects right hand R voltage follower after resistance R 109, the inverting input of data amplifier U208 is connected with Wilson's zero-potential point between resistance R 110 and the resistance R 111; The in-phase input end of data amplifier U209 connects left foot LF voltage follower after resistance R 107, the inverting input of data amplifier U209 connects right hand R voltage follower after resistance R 109; The in-phase input end of data amplifier U210 connects left foot LF voltage follower after resistance R 107, the inverting input of data amplifier U210 is connected with Wilson's zero-potential point between resistance R 112 and the resistance R 113; The in-phase input end of data amplifier U211 connects left hand L voltage follower after resistance R 108, the inverting input of data amplifier U211 connects right hand R voltage follower after resistance R 109; The in-phase input end of data amplifier U212 connects left hand L voltage follower after resistance R 108, the inverting input of data amplifier U212 is connected with Wilson's zero-potential point between resistance R 114 and the resistance R 115;

Described filter circuit comprises 12 band filters, each band filter comprises the single order RC high pass filter that a cut-off frequency that is connected with the outfan of data amplifier is 0.16Hz, and the outfan of single order RC high pass filter is connected with the single order RC low pass filter that a cut-off frequency is 106Hz;

Described leading selects circuit to comprise simulant electronic switch U301, simulant electronic switch U302, and the phase inverter that is made of audion T301, resistance R 301 and resistance R 302; Simulant electronic switch U301 and simulant electronic switch U302 are multidiameter option switch KCF4051BE; Audion T301 is audion C1815; The vdd terminal of simulant electronic switch U301 connects+the 5V power supply; The vdd terminal of simulant electronic switch U302 connects+the 5V power supply; The VSS end earth terminal of simulant electronic switch U301; The VEE termination of simulant electronic switch U301-5V power supply; The VSS end earth terminal of simulant electronic switch U302; The VEE termination of simulant electronic switch U302-5V power supply; Wherein the resistance of resistance R 301 is 22K ohm, and the resistance of resistance R 302 is 1M ohm, and the inner termination of resistance R 301 is connected with the colelctor electrode of audion T301, and the external end head of resistance R 301 connects+the 5V power supply; The inner termination of resistance R 302 is connected with the base stage of audion T301; The sheet choosing end INH of the colelctor electrode connecting analog electrical switch U301 of audion T301, the grounded emitter end of audion T301;

Wherein the outfan of data amplifier U201 via a described band filter after, output signal V6 is connected to the X3 end of simulant electronic switch U301; The outfan of data amplifier U202 via a described band filter after, output signal V5 is connected to the X2 end of simulant electronic switch U301; The outfan of data amplifier U203 via a described band filter after, output signal V4 is connected to the X1 end of simulant electronic switch U301; The outfan of data amplifier U204 via a described band filter after, output signal V3 is connected to the X0 end of simulant electronic switch U301; The outfan of data amplifier U205 via a described band filter after, output signal V2 is connected to the X7 end of simulant electronic switch U302; The outfan of data amplifier U206 via a described band filter after, output signal V1 is connected to the X6 end of simulant electronic switch U302; The outfan of data amplifier U207 via a described band filter after, output signal III is connected to the X2 end of simulant electronic switch U302; The outfan of data amplifier U208 via a described band filter after, output signal aVR is connected to the X3 end of simulant electronic switch U302; The outfan of data amplifier U209 via a described band filter after, output signal II is connected to the X1 end of simulant electronic switch U302; The outfan of data amplifier U210 via a described band filter after, output signal aVF is connected to the X5 end of simulant electronic switch U302; The outfan of data amplifier U211 via a described band filter after, output signal I is connected to the X0 end of simulant electronic switch U302; The outfan of data amplifier U212 via a described band filter after, output signal aVL is connected to the X4 end of simulant electronic switch U302;

Wherein the A of the A of simulant electronic switch U301 end, simulant electronic switch U302 holds all P1.0 ends of the unit's of being connected to sheet machine AT89C2051; The B end of described simulant electronic switch U301, the B end of simulant electronic switch U302 be the P1.1 end of the unit's of being connected to sheet machine AT89C2051 all; The C end of described simulant electronic switch U301, the C end of simulant electronic switch U302 be the P1.2 end of the unit's of being connected to sheet machine AT89C2051 all; The P1.3 end of sheet choosing end INH, the sheet machine AT89C2051 of unit of the external end head connecting analog electrical switch U302 of resistance R 302;

Described signal amplification circuit comprises data amplifier U303, and data amplifier U303 is data amplifier AD620; Connecting resistance between 1 pin of data amplifier U303 and 8 pins is the potentiometer R303 of 1K ohm; Outfan X, the outfan X of simulant electronic switch U302 of the in-phase input end connecting analog electrical switch U301 of data amplifier U303, the reverse inter-input-ing ending grounding end of data amplifier U303, the outfan of data amplifier U303 are received the input AIN0 of A/D converter TLC2543; 7 pins of data amplifier U303 connect+the 5V power supply, and 4 pins of data amplifier U303 connect-the 5V power supply; 5 pins of data amplifier U303 connect the positive pole of diode D301, the negative pole of diode D301 connects the positive pole of diode D302, the negative pole of diode D302 connects the positive pole of diode D303, and the negative pole of diode D303 connects the positive pole of diode D304, the minus earth end of diode D304; 5 pins of data amplifier U303 connect the resistance R 304 that resistance is 22K ohm, another termination of resistance R 304+5V power supply; The negative pole of the output terminating diode D305 of data amplifier U303, the plus earth end of diode D305;

Analog-digital conversion circuit as described comprises serial a/d transducer TLC2543, the AIN1 end of A/D converter TLC2543, AIN2 end, AIN3 end, AIN4 end, AIN5 end, AIN6 end, AIN7 end, AIN8 end, AIN9 end, AIN10 end, negative reference voltage end

Hold equal earth terminal with GND; The vdd terminal of A/D converter TLC2543 connects+the 5V power supply; The synchronised clock end SCLK of A/D converter TLC2543 is connected to the P1.4 end of the described sheet machine AT89C2051 of unit, the serial data input DIN of A/D converter TLC2543 is connected to the P1.5 end of the described sheet machine AT89C2051 of unit, the serial data outfan DOUT of A/D converter TLC2543 is connected to the P1.6 end of the described sheet machine AT89C2051 of unit, and the sheet choosing end CS of A/D converter TLC2543 is connected to the P1.7 of the described sheet machine AT89C2051 of unit; Resistance is one termination+5V power supply of the resistance R 401 of 1K ohm, the reference voltage end REF+ of another termination A/D converter TLC2543 of resistance R 401; Being connected in series successively swept resistance R402 and the resistance that resistance is 5K ohm between the reference voltage end REF+ of A/D converter TLC2543 and the ground end is the resistance R 403 of 4.7K ohm, 3 pins of stabilivolt TL431 connect reference voltage end REF+, 1 pin of stabilivolt TL431 is connected between swept resistance R402 and the resistance R 403, the 2 pin earth terminals of stabilivolt TL431;

Described one-chip computer comprises the described sheet machine AT89C2051 of unit, be provided with reset circuit on the sheet machine AT89C2051 of unit, described reset circuit comprises the VCC end of the sheet machine AT89C2051 of the unit of being connected to and the capacitor C 401 between the RST end, the end of reset key K401 connects the VCC end of the sheet machine AT89C2051 of unit, the other end contact resistance R404 of reset key K401, the other end of resistance R 404 connects the RST end of the sheet machine AT89C2051 of unit, one end of resistance R 405 connects the RST end of the sheet machine AT89C2051 of unit, the other end earth terminal of resistance R 405; Be provided with oscillating circuit on the sheet machine AT89C2051 of unit, described oscillating circuit comprises the XTL2 end of the sheet machine AT89C2051 of the unit of being connected to and the crystal oscillator X401 between the XTL1 end, the frequency of crystal oscillator X401 is 11.0592MHz, also be serially connected with successively capacitor C 402 and capacitor C 403, earth terminal between capacitor C 402, the capacitor C 403 between XTL2 end and the XTL1 end; The P1.1 end of the sheet machine AT89C2051 of unit connects pull-up resistor R406, another termination of pull-up resistor R406+5V power supply; The P1.0 end of the sheet machine AT89C2051 of unit connects pull-up resistor R407, another termination of pull-up resistor R407+5V power supply; The GND end earth terminal of the sheet machine AT89C2051 of unit;

Described level shifting circuit comprises level shifting circuit and RS232C interface, and level shifting circuit comprises electrical level transferring chip MAX232, and the appearance value is capacitor C 404, capacitor C 405, capacitor C 406 and the capacitor C 407 of 1 microfarad; One termination of capacitor C 404+5V power supply, 2 pins of another termination electrical level transferring chip MAX232 of capacitor C 404; Connect capacitor C 405 between 1 pin of electrical level transferring chip MAX232 and 3 pins; Connect capacitor C 406 between 4 pins of electrical level transferring chip MAX232 and 5 pins; Connect capacitor C 407 between 6 pins of electrical level transferring chip MAX232 and 8 pins; 8 pins of electrical level transferring chip MAX232,10 pin earth terminals; 11 pins of electrical level transferring chip MAX232 connect the TXD end of the described sheet machine AT89C2051 of unit, and 14 pins of electrical level transferring chip MAX232 connect the RXD end of described RS232C interface; The TXD end of described RS232C interface connects 13 pins of electrical level transferring chip MAX232, and 12 pins of electrical level transferring chip MAX232 connect the RXD end of the described sheet machine AT89C2051 of unit; 16 pins of electrical level transferring chip MAX232 connect+the 5V power supply; The GND end earth terminal of described RS232C interface.