CN103297158B - Receiver Built-In Self-Test circuit and method - Google Patents
Receiver Built-In Self-Test circuit and method Download PDFInfo
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- CN103297158B CN103297158B CN201310173545.8A CN201310173545A CN103297158B CN 103297158 B CN103297158 B CN 103297158B CN 201310173545 A CN201310173545 A CN 201310173545A CN 103297158 B CN103297158 B CN 103297158B
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Abstract
The present invention relates to a kind of receiver Built-In Self-Test circuit and method, test for receiver intermediate-frequency circuit provides intermediate frequency complex signal, described receiver Built-In Self-Test circuit comprises: frequency dividing circuit, be connected to clock generator, from the clock signal that clock generator produces, divide the intermediate frequency clock signal that occurs frequently; Complex signal produces circuit, is connected, for converting the intermediate frequency clock signal of input to complex intermediate frequency clock signal with frequency dividing circuit; Amplitude control circuit, produces circuit with complex signal and is connected, for the complex intermediate frequency clock signal of input is converted to intermediate frequency complex signal.Use the present invention, do not need the complex intermediate frequency signal producing test intermediate-frequency circuit needs with instrument, and simple with the connection of receiver, debugging is convenient, and cost is low.
Description
Technical field
The present invention relates to a kind of receiver Built-In Self-Test circuit and method, particularly a kind of in particular to intermediate-freuqncy signal generation circuit during a kind of receiver test and method.
Background technology
The general structure of modern communications receiver is that radiofrequency signal receives from antenna, and just can obtain complex intermediate frequency signal by complex mixing, described complex intermediate frequency signal by converting digital signal to after the process of intermediate-frequency circuit, and then carries out digital demodulation.
Once intermediate-frequency circuit is out of joint, or Water demand and the incomplete place of test macro, just need to go to detect to intermediate-frequency circuit input complex signal, existing detection method produces intermediate frequency complex signal by external instrument, then detected by described intermediate frequency complex signal input intermediate-frequency circuit.
But the complex intermediate frequency signal produced with instrument, easily plural number is uneven, and complicated with the connection of intermediate-frequency circuit, inconvenient debugging, and in addition, the instrument producing complex intermediate frequency signal is also somewhat expensive.
Summary of the invention
The technical problem that the present invention will solve is, for the deficiency in correlation technique, provides a kind of receiver Built-In Self-Test circuit, and the clock signal that the clock generator in receiver produces is converted to the test that complex intermediate frequency signal carries out intermediate-frequency circuit.
Another technical problem that the present invention will solve is, for the deficiency in correlation technique, a kind of method of testing of receiver Built-In Self-Test circuit is provided, the clock signal that the clock generator in receiver produces is converted to the test that complex intermediate frequency signal carries out intermediate-frequency circuit.
Described receiver Built-In Self-Test circuit comprises: frequency dividing circuit, is connected to clock generator, from the clock signal that clock generator produces, divide the intermediate frequency clock signal that occurs frequently;
Complex signal produces circuit, is connected, for converting the intermediate frequency clock signal of input to complex intermediate frequency clock signal with frequency dividing circuit; And
Amplitude control circuit, produces circuit with complex signal and is connected, for the complex intermediate frequency clock signal of input is converted to intermediate frequency complex signal,
Described amplitude control circuit is made up of real part circuit and imaginary part circuit, and real part circuit and imaginary part circuit have identical circuit structure, real part circuit comprises the resistance of multiple series connection, form divider resistance array, each resistance is connected to the input of a sub-control circuit, the output of sub-control circuit connects one end of an electric capacity, the other end ground connection of electric capacity, and described sub-control circuit comprises at least one memory.
Further, described clock generator is the clock generator in receiver.
Further, described frequency dividing circuit, be made up of multiple d type flip flop, each d type flip flop has a frequency dividing ratio preset, all d type flip flops are connected to dividing frequency control circuit, the frequency dividing ratio of the signal that described dividing frequency control circuit needs according to test selects the d type flip flop needed, thus exports the intermediate frequency clock signal needed.
Further, described sub-control circuit is at least one memory.
Further, the quantity of described memory is two.
Further, described amplitude control circuit comprises two memories.
Described method of testing comprises step: clock signal receiving step: the clock signal that frequency dividing circuit receive clock generator produces;
Dividing step: frequency dividing circuit divides the intermediate frequency clock signal that occurs frequently from described clock signal.
Complex intermediate frequency clock signal generating step: complex signal produces circuit and converts the intermediate frequency clock signal of input to complex intermediate frequency clock signal.
Intermediate frequency complex signal generating step: the complex intermediate frequency clock signal of input is converted to intermediate frequency complex signal by amplitude control circuit.
The invention has the beneficial effects as follows: by receiver Built-In Self-Test circuit, the clock signal that the clock generator of receiver produces is converted to complex intermediate frequency signal, tested by the intermediate-frequency circuit of described complex intermediate frequency signal to receiver, thus without the need to producing intermediate-freuqncy signal with instrument, and it is simple with the connection of receiver, debugging is convenient, and cost is low.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that receiver Built-In Self-Test circuit in an embodiment of the present invention is connected to receiver.
Fig. 2 is the module map of the receiver Built-In Self-Test circuit in an embodiment of the present invention.
Fig. 3 is for utilizing the oscillogram of the various signals in the process of the multiple intermediate-freuqncy signal of the Built-In Self-Test of receiver shown in Fig. 2 circuit conversion.
Fig. 4 is the circuit diagram of the frequency dividing circuit in the Built-In Self-Test of receiver shown in Fig. 2 circuit.
Fig. 5 is the circuit diagram of the amplitude control circuit in the Built-In Self-Test of receiver shown in Fig. 2 circuit.
Fig. 6 is for being applied to the flow chart of the method for the generation complex intermediate frequency signal of the Built-In Self-Test of receiver shown in Fig. 2 circuit.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can be combined with each other, and are described in further detail the present invention below in conjunction with the drawings and specific embodiments.
As shown in Figure 1, for the receiver Built-In Self-Test circuit 1 in an embodiment of the present invention is connected to the schematic diagram of receiver 2.Between the clock generator 21 that described receiver Built-In Self-Test circuit 1 is connected to described receiver 2 and intermediate-frequency circuit 22, the complex intermediate frequency signal needed when the clock signal for being produced by clock generator 21 is modulated to test intermediate-frequency circuit.
As shown in Figure 2, be the module map of the receiver Built-In Self-Test circuit 1 in an embodiment of the present invention.Receiver Built-In Self-Test circuit 1 comprises frequency dividing circuit 11, complex signal produces circuit 12 and amplitude control circuit 13.Illustrate that the clock signal that clock generator 21 produces to be modulated to the process of complex intermediate frequency signal by described receiver Built-In Self-Test circuit 1 below in conjunction with the signal waveforms shown in Fig. 3.The first waveform 31 in Fig. 3 is the initial waveform of the clock signal that clock generator 21 produces.Described frequency dividing circuit 11 divides the intermediate frequency clock signal that occurs frequently from described clock signal, and the waveform of described intermediate frequency clock signal is as the second waveform 32 in Fig. 3.Complex signal produces circuit 12 and is connected with frequency dividing circuit 11, and for converting the intermediate frequency clock signal of input to complex intermediate frequency clock signal, complex intermediate frequency clock signal, as shown in the 3rd waveform 33 in Fig. 3, is divided into real part and imaginary part.In present embodiment, any circuit that intermediate frequency clock signal can be become complex signal all can be applicable to the present invention, is prior art, does not repeat them here because complex signal produces circuit.
Described amplitude control circuit 13, produces circuit 12 with complex signal and is connected, and for the complex intermediate frequency clock signal of input is converted to intermediate frequency complex signal, the waveform of described intermediate frequency complex signal is as shown in the 4th waveform 34 in Fig. 3.The clock signal that receiver Built-In Self-Test circuit 1 like this can utilize the clock generator 21 of receiver 2 self to produce produces complex intermediate frequency signal, thus tests the intermediate-frequency circuit 22 of receiver.
In the present embodiment, as shown in Figure 4, described frequency dividing circuit 11 is made up of multiple d type flip flop 111, each d type flip flop has a frequency dividing ratio preset, all d type flip flops 111 are connected to a dividing frequency control circuit 112, the frequency dividing ratio of the signal that described dividing frequency control circuit 112 needs according to test selects the d type flip flop 111 needed, thus the intermediate frequency clock signal that output test needs.
In present embodiment, described dividing frequency control circuit 112 comprises two memories 1121, selects intermediate frequency clock signal to export by controlling d type flip flop 111 with the connection of memory 1121.In other embodiments, one or memory 1121 more than two can also be selected as required.This memory 1121 can be the memory devices such as register, disk or CD.
In present embodiment, as shown in Figure 5, described amplitude control circuit 13 is made up of real part circuit 131 and imaginary part circuit 132, and real part circuit 131 and imaginary part circuit 132 have identical circuit structure.Only be described for real part circuit 131 at this.Described real part circuit 131 comprises the resistance 133 of multiple series connection, form divider resistance array, each resistance 133 is connected to a sub-control circuit 134, the output of described sub-control circuit 134 connects an electric capacity 135, so, the complex intermediate frequency clock signal inputting described real part circuit 131 carries out dividing potential drop step by step through described multiple resistance 133, can adjust the amplitude of described complex intermediate frequency clock signal, described sub-control circuit 134 exports for selecting to test the signal behavior resistance needed, the adjustment of the amplitude to output signal can be realized, the signal exported is again after electric capacity 135 carries out harmonic wave minimizing, namely complex intermediate frequency signal is obtained.
In present embodiment, described sub-control circuit 134 comprises two memories 1341, is selected the resistance 133 exported, realize the selection of signal amplitude by memory 1341.In other embodiments, one or memory 1341 more than two can also be selected as required.This memory 1341 can be the memory devices such as register, disk or CD.
Fig. 6, for being applied to the flow chart of the method for the generation complex intermediate frequency signal of the Built-In Self-Test of receiver shown in Fig. 2 circuit, comprising:
Step S601, clock signal receiving step: the clock signal that frequency dividing circuit 11 receive clock generator 21 produces;
Step S602, dividing step: frequency dividing circuit 11 divides the intermediate frequency clock signal that occurs frequently from described clock signal.
Step S603, complex intermediate frequency clock signal generating step: complex signal produces circuit 12 and converts the intermediate frequency clock signal of input to complex intermediate frequency clock signal.
Step S604, intermediate frequency complex signal generating step: the complex intermediate frequency clock signal of input is converted to intermediate frequency complex signal by amplitude control circuit 13.
In addition, one of ordinary skill in the art will appreciate that all or part of flow process realized in above-described embodiment method, that the hardware that can carry out instruction relevant by program has come, described program can be stored in a computer-readable recording medium, described program, when performing, can comprise the flow process of the embodiment as above-mentioned each side method.Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-OnlyMemory, ROM) or random store-memory body (RandomAccessMemory, RAM) etc.
Although illustrate and describe embodiments of the invention, for the ordinary skill in the art, be appreciated that and can carry out multiple change, amendment, replacement and modification to these embodiments without departing from the principles and spirit of the present invention, scope of the present invention is limited by claims and equivalency range thereof.
Claims (7)
1. a receiver Built-In Self-Test circuit, the test for receiver intermediate-frequency circuit provides intermediate frequency complex signal, it is characterized in that, described receiver Built-In Self-Test circuit comprises:
Frequency dividing circuit, is connected to clock generator, from the clock signal that clock generator produces, divide the intermediate frequency clock signal that occurs frequently;
Complex signal produces circuit, is connected, for converting the intermediate frequency clock signal of input to complex intermediate frequency clock signal with frequency dividing circuit; And
Amplitude control circuit, produces circuit with complex signal and is connected, for the complex intermediate frequency clock signal of input is converted to intermediate frequency complex signal,
Described amplitude control circuit is made up of real part circuit and imaginary part circuit, and real part circuit and imaginary part circuit have identical circuit structure, real part circuit comprises the resistance of multiple series connection, form divider resistance array, each resistance is connected to the input of a sub-control circuit, the output of sub-control circuit connects one end of an electric capacity, the other end ground connection of electric capacity, and described sub-control circuit comprises at least one memory.
2. receiver Built-In Self-Test circuit according to claim 1, is characterized in that, described clock generator is the clock generator in receiver.
3. receiver Built-In Self-Test circuit according to claim 1, it is characterized in that, described frequency dividing circuit, be made up of multiple d type flip flop, each d type flip flop has a frequency dividing ratio preset, all d type flip flops are connected to dividing frequency control circuit, and the frequency dividing ratio of the signal that described dividing frequency control circuit needs according to test selects the d type flip flop needed, thus export the intermediate frequency clock signal needed.
4. receiver Built-In Self-Test circuit according to claim 1, is characterized in that, described sub-control circuit is at least one memory.
5. receiver Built-In Self-Test circuit according to claim 4, is characterized in that, the quantity of described memory is two.
6. receiver Built-In Self-Test circuit according to claim 5, is characterized in that, described amplitude control circuit comprises two memories.
7. one kind is applied to the test of the receiver Built-In Self-Test circuit according to any one of claim 1 to 6
Method, comprises step:
Clock signal receiving step: the clock signal that frequency dividing circuit receive clock generator produces;
Dividing step: frequency dividing circuit divides the intermediate frequency clock signal that occurs frequently from described clock signal;
Complex intermediate frequency clock signal generating step: complex signal produces circuit and converts the intermediate frequency clock signal of input to complex intermediate frequency clock signal; And
Intermediate frequency complex signal generating step: the complex intermediate frequency clock signal of input is converted to intermediate frequency complex signal by amplitude control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310173545.8A CN103297158B (en) | 2013-05-10 | 2013-05-10 | Receiver Built-In Self-Test circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310173545.8A CN103297158B (en) | 2013-05-10 | 2013-05-10 | Receiver Built-In Self-Test circuit and method |
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| CN103297158A CN103297158A (en) | 2013-09-11 |
| CN103297158B true CN103297158B (en) | 2015-12-09 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1176539A (en) * | 1996-08-12 | 1998-03-18 | 美国电报电话公司 | Self-testing transceiver |
| CN1213226A (en) * | 1997-06-13 | 1999-04-07 | 日本电气株式会社 | Clock signal control method and device |
| US6040738A (en) * | 1997-12-10 | 2000-03-21 | Nec Corporation | Direct conversion receiver using single reference clock signal |
| CN101378258A (en) * | 2007-08-29 | 2009-03-04 | 中国科学院电子学研究所 | Modularization frequency division unit and frequency divider |
| CN101572558A (en) * | 2009-05-11 | 2009-11-04 | 苏州通创微芯有限公司 | Intermediate frequency transceiving chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW532016B (en) * | 2000-12-18 | 2003-05-11 | Asulab Sa | Correlation and demodulation circuit for a receiver for signals modulated by a specific code |
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2013
- 2013-05-10 CN CN201310173545.8A patent/CN103297158B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1176539A (en) * | 1996-08-12 | 1998-03-18 | 美国电报电话公司 | Self-testing transceiver |
| CN1213226A (en) * | 1997-06-13 | 1999-04-07 | 日本电气株式会社 | Clock signal control method and device |
| US6040738A (en) * | 1997-12-10 | 2000-03-21 | Nec Corporation | Direct conversion receiver using single reference clock signal |
| CN101378258A (en) * | 2007-08-29 | 2009-03-04 | 中国科学院电子学研究所 | Modularization frequency division unit and frequency divider |
| CN101572558A (en) * | 2009-05-11 | 2009-11-04 | 苏州通创微芯有限公司 | Intermediate frequency transceiving chip |
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| CN103297158A (en) | 2013-09-11 |
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Granted publication date: 20151209 Termination date: 20180510 |