CN103296202A - Phase change memory and manufacturing method thereof - Google Patents

Abstract

A phase change memory and its manufacturing method, said method comprising: providing a semiconductor substrate, which includes a first region and a second region; depositing a dielectric layer, forming a lower layer in the dielectric layer on the second region of the semiconductor substrate Electrodes; phase change material is deposited and etched to form a patterned phase change material layer at the position corresponding to the lower electrode above the dielectric layer, a pseudo phase change pad is formed at a local position corresponding to the first semiconductor region, and the patterned phase change There is a gap between the material layer and the dummy phase change pad, the dummy phase change pad includes at least two parts, and there is a gap between adjacent parts; after the dummy phase change pad is formed, the semiconductor substrate is cleaned. The invention effectively solves the problem that the pseudo-phase-change pad is easy to peel off during the cleaning process after the phase-change material is etched after the pseudo-phase-change pad is divided into a plurality of parts with intervals therebetween.

Description

Phase change memory and manufacturing method thereof

technical field

The invention belongs to the field of microelectronics manufacturing, and in particular relates to a phase-change memory and a manufacturing method thereof.

Background technique

Phase Change Memory (PCM) has the characteristics of high read speed, low power, high capacity, high reliability, high erasable times, low working voltage, etc., and is very suitable for combining with CMOS technology, and can be used as a relatively High-density stand-alone or embedded memory applications are currently very promising next-generation memories. Due to the unique advantages of phase change memory technology, it is also considered very likely to replace the current highly competitive volatile memory (Volatile Memory) such as SRAM and DRAM and non-volatile memory (Non-volatile Memory) such as Flash. It is expected to become a new generation of semiconductor memory with great potential in the future.

Phase-change memory uses the difference in resistance of phase-change materials in crystalline and amorphous states to store data, and it mainly uses the control of current pulse waves to complete write, erase, and read operations. FIG. 1 is a simplified schematic diagram of a common phase-change memory. As shown in FIG. 1 , the phase-change memory 11 sequentially includes a lower electrode 13, a phase-change material layer 14, and an upper electrode 15 formed in a dielectric layer 12 from bottom to top. The surface of the lower electrode 13 is flush with the surface 12 a of the dielectric layer 12 . When the writing operation is to be performed, a relatively high current (such as 0.6 milliamps) can be provided for a short time (for example, 50 nanoseconds), so that the phase-change material layer portion 14a in contact with the lower electrode 13 is melted and cooled rapidly to An amorphous phase change material is formed. Since the amorphous phase change material has relatively high resistance (for example, 10 ⁵ -10 ⁷ ohms), when performing a read operation, providing a read current can obtain a higher voltage. When the erasing operation is to be performed, a relatively low current (for example, 0.3 mA) can be provided for a long time (for example, 100 nanoseconds), so that the amorphous phase-change material layer part 14a is converted into crystallization due to crystallization phase change material. Since the crystalline phase change material has low resistance (for example, 10 ² -10 ⁴ ohms), when performing a read operation, a relatively low voltage can be obtained by providing a read current. Accordingly, the operation of the phase change memory can be performed.

An existing manufacturing method of a phase-change memory includes the following steps:

As shown in FIG. 2 , a first dielectric layer 2 such as silicon oxide, silicon nitride or silicon oxynitride is deposited on a semiconductor substrate 1 . Then, the first dielectric layer 2 is patterned by using, for example, photolithography and etching processes, so as to form via holes (not shown) in the first dielectric layer 2 . Fill the through hole with conductive material to form the lower electrode 3 of the phase change memory. A phase change material layer 4 is formed on the semiconductor substrate 1 formed with the first dielectric layer 2 and the lower electrode 3 , such as Ge—Sb—Te chalcogenide. Then, a barrier layer 5 is formed on the phase-change material layer 4 to protect the phase-change material layer 4 for subsequent processes.

As shown in Figure 3, a photoresist 6 is formed on the semiconductor substrate 1 formed with a phase-change material layer 4 and a barrier layer 5, and the photoresist 6 is patterned using a photolithography process to form a pattern on the photoresist 6 A window 7 is formed in the middle to ensure that the position above the barrier layer 5 corresponding to the lower electrode 3 is covered with a photoresist 6 .

As shown in Figure 4, the barrier layer 5 not covered by the photoresist 6 and the phase-change material layer 4 below are etched. After etching, the position corresponding to the lower electrode 3 is covered with a phase-change material, this part of the phase change material constitutes the patterned phase change material layer 4' of the memory. During the etching process, some undesired by-products 8 in the semiconductor process, such as polymer, will be formed on the surface of the semiconductor substrate 1 . Therefore, the etched semiconductor substrate 1 needs to be cleaned.

As shown in FIG. 5, the photoresist 6 is removed. Washing with HF acid solution containing water removes by-product 8.

After cleaning, according to subsequent process requirements, as shown in FIG. 6 , a second dielectric layer 9 such as silicon oxide, silicon nitride, silicon oxynitride, etc. will be formed on the semiconductor substrate 1 . Then, the second dielectric layer 9 is polished by a chemical mechanical polishing (CMP) process until the surface of the barrier layer 5 is exposed. In this process, the barrier layer 5 can be used as a polishing stop layer, so that the second dielectric layer 9 Grind to desired thickness. Then form the upper electrode (not shown) of the phase change memory, the upper electrode, the lower electrode 3, and the patterned phase change material layer 4' between the upper electrode and the lower electrode 3 constitute the phase change memory.

When the above-mentioned chemical mechanical polishing is performed on the second dielectric layer 9, the following situation may exist: as shown in FIG. No pattern structure is formed on the first dielectric layer 2 on the right side), so that after the chemical mechanical polishing process, pits will be formed in the second dielectric layer 9, resulting in uneven polishing.

In order to solve the above problem of uneven polishing, as shown in FIG. 4, when the phase change material layer 4 is etched to form the patterned phase change material layer 4' of the phase change memory, the patterned phase change material layer will be A dummy pad (dummy pad) 10 is formed on one side of 4' (the left side is taken as an example in the figure), so as to improve the polishing uniformity of the subsequent chemical mechanical polishing process.

Because the adhesion between the phase-change material layer and the dielectric layer below it is not strong, when the above-mentioned cleaning process is carried out to the semiconductor substrate, the false phase-change pad 10 will often be peeled off, as shown in Figure 5 and Figure 8 (Figure 8 is A partial top view of Figure 5). The dummy phase change pad 10 and the barrier layer 5 drawn by dotted lines in FIG. 5 and the dummy phase change pad 10 placed obliquely in FIG. 8 represent that the dummy phase change pad 10 is no longer adsorbed on the semiconductor substrate after cleaning. More seriously, even when the concentration of the cleaning solution is as small as 3000:1 (volume ratio of water to HF acid), the problem of peeling off of the pseudo phase change pad cannot be improved.

Contents of the invention

The problem to be solved by the present invention is to provide a method for manufacturing a phase change memory, so as to prevent the false phase change pad from peeling off during the cleaning process after the phase change material layer is etched.

In order to solve the above problems, the present invention provides a method for manufacturing a phase change memory, the method comprising:

providing a semiconductor substrate comprising a first region and a second region;

depositing a dielectric layer to form a lower electrode within the dielectric layer in the second region;

Depositing a phase change material, and then etching it, to form a patterned phase change material layer at a position corresponding to the lower electrode above the dielectric layer, and form a pseudo phase change pad at a local position corresponding to the first region, the patterned There is a space between the phase change material layer and the pseudo phase change pad, and the pseudo phase change pad includes at least two parts, and there is a space between adjacent parts;

Cleaning is performed on the dielectric layer formed with the patterned phase-change material layer and the pseudo-phase-change pad.

Optionally, the surface of the lower electrode is flush with or lower than the surface of the dielectric layer.

Optionally, the manufacturing step of the lower electrode includes:

forming vias in the dielectric layer on the second region of the semiconductor substrate;

depositing a conductive material such that the via hole is filled with the conductive material;

performing chemical mechanical polishing on the conductive material until the dielectric layer is exposed;

Part of the conductive material in the through hole is removed, and the remaining conductive material forms the bottom electrode.

Optionally, the manufacturing steps of the patterned phase-change material layer and the pseudo-phase-change pad include:

sequentially depositing a phase-change material layer and a barrier layer on the semiconductor substrate formed with the lower electrode;

forming a patterned photoresist on the barrier layer, so that the position corresponding to the lower electrode and the local position corresponding to the first region of the semiconductor substrate above the barrier layer are covered with photoresist;

removing the barrier layer and the phase-change material layer not covered by the photoresist, forming a patterned phase-change material layer on the lower electrode, and forming a dummy phase-change pad above the dielectric layer on the first region of the semiconductor substrate, There is a space between the dummy phase change pad and the patterned phase change material layer, the dummy phase change pad includes at least two parts, and there is a space between adjacent parts.

Optionally, the barrier layer is made of TiN.

Optionally, the width of the interval between the part and adjacent parts is 40nm-180nm.

Optionally, the pseudo phase change pad has a width of 1 μm˜10 μm and a length of 1 μm˜10 μm.

Optionally, the cleaning treatment step is performed using HF acid containing water, and the volume ratio of water to HF acid is 1000:1˜15000:1.

Optionally, the time for the cleaning treatment is 20s˜120s.

Optionally, the dielectric layer is PETEOS.

At the same time, the present invention also provides a phase change memory, comprising:

a dielectric layer located on a semiconductor substrate comprising a first region and a second region;

a lower electrode disposed within the dielectric layer on the second region of the semiconductor substrate;

a layer of patterned phase change material overlying the lower electrode;

A dummy phase change pad, which is located above the dielectric layer on the first region of the semiconductor substrate, there is a space between the dummy phase change pad and the patterned phase change material layer, and the dummy phase change pad includes at least two parts with intervals between adjacent parts.

Optionally, the upper surface of the lower electrode is flush with or lower than the surface of the dielectric layer.

Optionally, a barrier layer is provided above the patterned phase change material layer and the dummy phase change pad.

Optionally, the barrier layer is made of TiN.

Optionally, the width of the interval between the part and adjacent parts is 40nm-180nm.

Optionally, the pseudo phase change pad has a width of 1 μm˜10 μm and a length of 1 μm˜10 μm.

Optionally, the dielectric layer is PETEOS.

Compared with the prior art, after the pseudo phase change pad is divided into multiple parts with intervals between each other, the present invention effectively improves the possibility of the pseudo phase change pad being easily peeled off during the cleaning process after the phase change material layer is etched. question.

Description of drawings

Figure 1 is a simplified schematic diagram of a common phase change memory.

2 to 6 are schematic diagrams of manufacturing a conventional phase change memory.

FIG. 7 is a schematic diagram of performing chemical mechanical polishing on the dielectric layer to cause uneven polishing without forming a dummy phase change pad on one side of the patterned phase change material layer.

FIG. 8 is a schematic diagram of the peeling off of the pseudo-phase-change pad during the cleaning process after the phase-change material layer is etched in the conventional phase-change memory.

FIG. 9 is a flow chart of manufacturing a phase change memory in an embodiment of the method for manufacturing a phase change memory of the present invention.

10 to 16, FIG. 18, and FIG. 19 are cross-sectional views of a phase change memory in an embodiment of the manufacturing method of the phase change memory of the present invention.

FIG. 17 is a schematic diagram showing that the dummy phase change pad does not peel off during the cleaning process after phase change material etching according to the present invention.

Detailed ways

The problem to be solved by the present invention is to provide a method for manufacturing a phase change memory, so as to prevent the false phase change pad from peeling off during the cleaning process after the phase change material layer is etched.

In order to solve the above problems, the inventors found that when the pseudo-phase-change pad is divided into multiple parts with intervals between each other, the adhesion between the pseudo-phase-change pad and the underlying dielectric layer will be significantly enhanced, effectively improving The problem that the pseudo-phase-change pad is easy to peel off during the cleaning process after the etching of the phase-change material layer is solved.

The technical solution of the present invention will be described clearly and completely through specific embodiments below in conjunction with the accompanying drawings. Apparently, the described embodiments are only a part of the possible implementation modes of the present invention, not all of them. According to these embodiments, all other implementation manners that can be obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.

FIG. 9 is a flow chart of manufacturing a phase change memory in an embodiment of the method for manufacturing a phase change memory of the present invention. As shown in Figure 9, the method includes:

Step S100: providing a semiconductor substrate, which includes a first region and a second region.

Step S200: Deposit a dielectric layer, and form a lower electrode in the dielectric layer on the second region of the semiconductor substrate.

Step S300: Depositing a phase change material and etching it to form a patterned phase change material layer above the dielectric layer at a position corresponding to the lower electrode, to form a pseudo phase change pad at a local position corresponding to the first semiconductor region, and to form a patterned phase change pad. There is a space between the layer of the change material and the dummy phase change pad, the pseudo phase change pad includes at least two parts, and there is a space between adjacent parts.

Step S400: Cleaning the dielectric layer formed with the patterned phase change material layer and the dummy phase change pad.

10 to 19 are cross-sectional views of the phase change memory in an embodiment of the manufacturing method of the phase change memory of the present invention. The manufacturing method of the phase change memory of the present invention will be described below by combining FIGS. 10 to 19 with FIG. 9 .

Step S100 is first performed: providing a semiconductor substrate, which includes a first region and a second region.

As shown in FIG. 10 , a semiconductor substrate 20 is provided, which is divided into at least two regions: a first region I and a second region II. In other embodiments of the present invention, the semiconductor substrate can also be divided into three or more regions for forming other semiconductor devices of integrated circuits. In a preferred embodiment of the present invention, the semiconductor substrate 20 is a silicon substrate, but the present invention is not limited thereto, and the semiconductor substrate 20 may be composed of other semiconductor materials. The semiconductor substrate 20 may be a substrate that has completed the CMOS front-end process, that is, the semiconductor substrate may contain isolation structures, capacitors, diodes or similar semiconductor device structures.

In order to control the operation of the phase change memory, before forming the lower electrode of the phase change memory on the semiconductor substrate, it is necessary to form a switching element (not shown) on the semiconductor substrate, and the switching element is electrically connected to the subsequently formed phase change memory, By heating the electrodes of the phase-change memory, the crystal state of part of the phase-change material layer (the part of the phase-change material layer in contact with the lower electrode) changes. The switch element includes a vertical diode (vertical diode) composed of a P-type semiconductor layer and an N-type semiconductor layer, but the present invention is not limited thereto, and the switch element can also be a bipolar junction transistor (bipolar junction transistor, BJT) or metal Oxide semiconductor field effect transistor (metal oxide semiconductor field effect transistor, MOSFET).

Next, step S200 is performed: depositing a dielectric layer, forming a lower electrode in the dielectric layer on the second region of the semiconductor substrate, and the surface of the lower electrode is flush with or lower than the surface of the dielectric layer.

As shown in FIG. 11 , a dielectric layer 21 is deposited on a semiconductor substrate 20 , and the dielectric layer 21 can be an oxide layer or a nitride layer. The oxide layer may include silicon oxide (SiO ₂ ), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicate Glass (USG), Spin On Glass (SOG), High Density Plasma (HDP) or Spin On Dielectric (SOD). The nitride layer may include silicon nitride (silicon nitride Si ₃ N ₄ ) or silicon oxynitride (SiON). In a preferred embodiment of the present invention, the dielectric layer 21 is SiO ₂ formed using TEOS, ie PETEOS. Using the PETEOS method to deposit SiO ₂ has a relatively high rate, which is of great benefit to improving the yield of silicon wafers in integrated circuits.

In one embodiment of the present invention, as shown in FIG. 11 , the dielectric layer 21 is patterned using, for example, photolithography and etching processes, so as to form a A through hole (not shown), the position of the through hole corresponds to the switch element in the semiconductor substrate 20, so that the phase change memory and the switch element can be electrically connected together. Then, a conductive material is deposited on the semiconductor substrate 20 until the via hole is filled with the conductive material. The conductive material can be Ti, W, Ta, TiN, TiW, TaN, TiAl, TiWN, TiAlN and the like. In a preferred embodiment of the present invention, the conductive material is W. Before depositing the conductive material, a diffusion barrier layer (not shown), such as TiN, may be deposited on the sidewalls and bottom of the via to prevent the conductive material subsequently deposited in the via from diffusing into the dielectric. layer. Next, chemical mechanical polishing is performed on the conductive material until the dielectric layer 21 is exposed. So far, as shown in FIG. 11 , the lower electrode 22 can be formed in the dielectric layer 21 on the second region II of the semiconductor substrate, and the surface 22 a of the lower electrode 22 is flush with the surface 21 a of the dielectric layer 21 .

As shown in Fig. 1, when the phase-change memory is to realize the conversion between logic value 0 and logic value 1, it is necessary to use enough energy to stimulate the temperature of the phase-change material layer part 14a to rise to the melting temperature. At the same time, it is necessary to avoid heating the phase change material around the phase change material layer part 14a, and then perform a rapid quenching treatment to make the phase change material layer part 14a change from a crystalline state to an amorphous state, thereby realizing data storage. However, there are some problems in this phase-change memory structure: when the phase-change material layer part 14a is heated, the heat is easily transferred to the phase-change material around the phase-change material layer part 14a, so that the phase-change memory cannot be realized in logic. Conversion between value 0 and logical value 1.

In order to improve the above problems, in a preferred embodiment of the present invention, after forming the lower electrode 22 whose surface is flush with the surface 21a of the dielectric layer, as shown in FIG. material forms the final bottom electrode. Therefore, in this phase change memory structure, the surface 22a of the bottom electrode is lower than the surface 21a of the dielectric layer. The removal method may be a common semiconductor etching method such as dry etching, wet etching or a combination of both. In one embodiment of the invention, about half of the conductive material inside the via can be removed.

Next, step S300 is performed: depositing a phase-change material, and etching it to form a patterned phase-change material layer above the dielectric layer at a position corresponding to the lower electrode, and to form a pseudo-phase-change pad at a local position corresponding to the first semiconductor region. There is a gap between the phase change material layer and the dummy phase change pad, the dummy phase change pad includes at least two parts, and there is a gap between adjacent parts.

As shown in FIG. 13, a phase-change material layer 23 is deposited on the semiconductor substrate 20 formed with the lower electrode 22, and the phase-change material layer 23 may include chalcogenides, such as germanium-antimony-tellurium (Ge-Sb-Te), Arsenic-antimony-tellurium (As-Sb-Te), tin-antimony-tellurium (Sn-Sb-Te), tin-indium-antimony-tellurium (Sn-In-Sb-Te), arsenic-germanium-antimony-tellurium (As-Ge-Sb-Te), tantalum-antimony-tellurium (Ta-Sb-Te), niobium-antimony-tellurium (Nb-Sb-Te), vanadium-antimony-tellurium (V-Sb-Te), tungsten - Antimony-tellurium (W-Sb-Te), molybdenum-antimony-tellurium (Mo-Sb-Te), chromium-antimony-tellurium (Cr-Sb-Te), tungsten-antimony-selenium (W-Sb-Se) , molybdenum antimony selenium (Mo-Sb-Se), chromium-antimony-selenium (Cr-Sb-Se), Ga-Sb, In-Sb, In-Se, Sb-Te, Ge-Te, Ag-In-Sb -Te wait. In a preferred embodiment of the present invention, the phase change material layer 23 is germanium-antimony-tellurium (Ge-Sb-Te, GST). Of course, the phase change material layer 23 may also include other phase change materials well known to those skilled in the art.

Continue to refer to shown in Figure 13, in one embodiment of the present invention, according to the needs of follow-up process, after depositing phase-change material layer 23, can deposit barrier layer (barrier layer) 24 on phase-change material layer 23, barrier layer 24 One of the functions it plays is to protect the phase change material layer 23 below it. The barrier layer 24 may include suitable conductive materials such as TiN, TiW, or the like. In a preferred embodiment of the invention, barrier layer 24 is TiN.

As shown in FIG. 14 , a patterned photoresist is formed on the barrier layer 24, so that the position above the barrier layer 24 is covered with a photoresist 25a corresponding to the position of the lower electrode 22, and the position above the barrier layer 24 is covered with the first electrode corresponding to the semiconductor substrate. Partial locations of the region I are covered with photoresist 25b. Wherein, there is a space between the photoresist 25a above the lower electrode 22 and the photoresist 25b on the first region 1 of the semiconductor substrate, and the photoresist 25b on the first region 1 of the semiconductor substrate includes at least two parts, corresponding to There are gaps between adjacent parts.

As shown in FIG. 15 , using the patterned photoresist as a mask, remove the barrier layer 24 and the phase change material layer 23 not covered by the photoresist, form a patterned phase change material layer 26 on the lower electrode 22, and form a patterned phase change material layer 26 on the semiconductor A dummy phase change pad 27 is formed above the dielectric layer 21 on the first region I of the substrate, and there is a space between the dummy phase change pad 27 and the patterned phase change material layer 26 . Wherein, the dummy phase-change pad 27 does not have a device function, and the lower part does not need to be connected to the electrode, and the upper part will not be connected to the upper electrode in the subsequent process. There are many ways to remove the barrier layer 24 and the phase change material layer 23, such as dry etching, wet etching or a combination of both. In order to obtain a better CMP effect in the subsequent processing, the plurality of dummy phase change pads 27 and the phase change material layer 26 are uniformly arranged as a whole. Each dummy phase change pad 27 includes at least two parts A contacting the surface of the dielectric layer 21 , and there is a space B between adjacent parts A. In a preferred embodiment of the present invention, the width W ₁ of the space B in the dummy phase change pad 27 is 40nm to 180nm, and the width W ₂ of the part A is 40nm to 180nm, which can ensure that the dummy phase change pad 27 and the dielectric layer below 21 have sufficient adhesive force, so that the pseudo phase change mat will not peel off during the subsequent cleaning process.

Continuing to refer to FIG. 15, when the lower electrode surface 22a formed in the above-mentioned step S200 is lower than the dielectric layer surface 21a, the deposited phase-change material layer 23 not only covers the dielectric layer 21, but also has a part of the phase-change material The layer 23 fills in the via hole where the lower electrode 22 is located, and is in contact with the lower electrode 22 . When the phase-change memory works, the lower electrode will heat the phase-change material layer, because the phase-change material layer part 23a filled in the through hole will be in close contact with the lower electrode 22, and the surrounding of the phase-change material layer part 23a will be The dielectric layer 21 is surrounded, so when the heating process is carried out, only the phase change material layer part 23a will be heated, and the phase change material around the phase change material layer part 23a will not be heated, so that the phase change memory can be easily implemented in logic The conversion between the value 0 to the logic value 1, and can also reduce the power consumption of the phase change memory.

In this embodiment, a dummy phase change pad is formed on one side (left side) of the patterned phase change material layer as an example. The dummy phase-change pads are formed on both sides (left and right) of the change material layer, and the number of the dummy phase-change pads can be adjusted according to actual production conditions.

Compared with the prior art, the pseudo phase change mat in the present invention is divided into multiple parts with intervals between each other, but the division form of the pseudo phase change mat should not be limited to the accompanying drawings, and other similar division forms are also available. within the protection scope of the present invention.

In this embodiment, after the deposition of the phase change material layer, a barrier layer will be deposited on the phase change material layer according to the requirements of the subsequent manufacturing process. Therefore, when forming a patterned phase change material layer and a pseudo phase change pad, the pseudo phase change pad In this case, the barrier layer can also be regarded as a part of the pseudo phase change mat. In other embodiments of the present invention, according to changes in the manufacturing method of the phase change memory, after the phase change material layer is deposited, a material layer for other purposes (except the barrier layer) may be formed on the phase change material layer, such as for Form the conductive material of the upper electrode, and then etch the material layer and the phase change material layer to form a patterned phase change material layer and a pseudo phase change pad. At this time, the material layer will be covered above the pseudo phase change pad, and the material layer The layer will form part of the pseudo phase change mat.

Continuing to refer to Fig. 15, in the process of removing the phase change material layer, some undesirable by-products 28 in the semiconductor process will be formed on the surface of the semiconductor substrate 20, such as polymer (polymer), in order to avoid the by-products on the phase change The electrical performance of the memory is adversely affected, and the semiconductor substrate needs to be cleaned.

Finally, step S400 is performed: cleaning the dielectric layer formed with the patterned phase change material layer and the dummy phase change pad.

As shown in FIG. 16 , the photoresist is removed, and then the semiconductor substrate 20 is cleaned with an HF acid solution containing water to remove the residual by-products 28 . In a preferred embodiment of the present invention, the volume ratio of water to HF acid in the solution is 1000:1˜15000:1. When the cleaning time is 20s-120s, it can ensure that the residual by-product 28 is removed.

The inventor used multiple HF acid solutions containing water with different concentrations to clean the semiconductor substrate successively, and detected the adhesion state between the pseudo phase change pad and the semiconductor substrate after cleaning. After the phase change pad 27 is divided into multiple parts with intervals between each other, the adhesive force between the dummy phase change pad 27 and the dielectric layer 21 below is significantly enhanced, and the substrate 20 will not appear after the cleaning process. The peeling off of the pseudo phase-change pad 27 (as shown in FIG. 8 ) is shown in FIG. 17 .

After performing the cleaning step, in one embodiment of the present invention, as shown in FIG. 18 , a dielectric layer 29 can be deposited on the semiconductor substrate 20, and then the dielectric layer 29 is chemically mechanically polished until the barrier is exposed. layer 24 surface. In this step, barrier layer 24 may serve as a stop layer for chemical mechanical polishing. Although the pseudo-phase-change pad 27 is divided into a plurality of parts A with intervals B therebetween, the pseudo-phase-change pad 27 is still a whole as a whole due to the small width W ₂ of the intervals A. The pseudo phase change pad 27 can improve the polishing uniformity in the chemical mechanical polishing process described above. The overall size of the pseudo-phase change pad has a significant impact on polishing uniformity. In a preferred embodiment of the present invention, as shown in FIG. 17 , the width of the dummy phase change pad 27 (dimensions in the same direction as the width of part A and gap B) W ₃ is 1 μm to 10 μm (the width of part A and gap B sum of width), length (dimensions perpendicular to the width direction of part A and gap B) W ₄ is 1 μm to 10 μm.

After the chemical mechanical polishing process, as shown in FIG. 19 , a dielectric layer 30 is deposited on the semiconductor substrate 20, and then the dielectric layer 30 is patterned so that the dielectric layer 30 corresponds to the A through hole is formed at the position of the lower electrode 22, and then a conductive metal, such as Cu, is filled into the through hole to form the upper electrode 31 of the phase change memory.

At the same time, the present invention also provides a phase change memory, as shown in Figure 11, Figure 12, and Figure 16, which includes:

A dielectric layer 21, which is located on the semiconductor substrate 20 including the first region I and the second region II, in a preferred embodiment of the present invention, the material of the dielectric layer 21 is PETEOS;

a lower electrode 22, which is disposed in the dielectric layer 21 on the second region II of the semiconductor substrate;

patterned phase change material layer 26, which is located above the lower electrode 22;

The dummy phase change pad 27 is located above the dielectric layer 21 on the first region I of the semiconductor substrate, there is a gap between the dummy phase change pad 27 and the patterned phase change material layer 26, and the dummy phase change pad 27 includes at least two A part A in contact with the dielectric layer 21, there is a space B between adjacent parts A, in a preferred embodiment of the present invention, the width W ₂ and W ₁ of the space B between the part A and the adjacent part A is 40nm ~180 nm, the width W ₃ of the pseudo phase change pad is 1 μm-10 μm, and the length W ₄ is 1 μm-10 μm.

Optionally, a barrier layer 24 is provided above the patterned phase-change material layer 26 and the dummy phase-change pad 27, and its material may be TiN.

Compared with the prior art, the present invention effectively improves the problem that the pseudo-phase-change pad is easy to peel off during the cleaning process after the phase-change material is etched by dividing the pseudo-phase-change pad into multiple parts with intervals between each other. question.

The above descriptions through the embodiments should enable those skilled in the art to better understand the present invention, and to be able to reproduce and use the present invention. It is obvious to those skilled in the art that various changes and modifications can be made to the above-mentioned embodiments based on the principles described herein without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be construed as limited to the above-described embodiments shown herein, but its protection scope should be defined by the appended claims.

Claims (17)

1. the manufacture method of a phase transition storage is characterized in that, described manufacture method comprises:

Semiconductor substrate is provided, and it comprises first area, second area;

Dielectric layer forms bottom electrode in the dielectric layer of second area;

The sediment phase change material, then it is carried out etching, form pseudo-phase transformation pad with the position formation patterned phase change material layer of corresponding bottom electrode above described dielectric layer, the local location of corresponding first area, exist between described patterned phase change material layer and the described pseudo-phase transformation pad at interval, described pseudo-phase transformation pad comprises two parts at least, exists between the adjacent part at interval;

The dielectric layer that is formed with described patterned phase change material layer, pseudo-phase transformation pad is carried out clean.

2. manufacture method according to claim 1 is characterized in that, the surface of described bottom electrode and described dielectric layer flush or be lower than described dielectric layer surface.

3. manufacture method according to claim 2 is characterized in that, the making step of described bottom electrode comprises:

Form through hole in the dielectric layer on the Semiconductor substrate second area;

Deposits conductive material makes described through hole be filled up by electric conducting material;

Described electric conducting material is carried out cmp, until exposing described dielectric layer;

Remove the partially conductive material in the described through hole, residual electric conducting material forms bottom electrode.

4. manufacture method according to claim 1 and 2 is characterized in that, the making step of described patterned phase change material layer, pseudo-phase transformation pad comprises:

Be formed with on the Semiconductor substrate of bottom electrode sediment phase change material layer, barrier layer successively;

Form graphical photoresist on described barrier layer, make top, described barrier layer be coated with photoresist in the position of corresponding bottom electrode and the local location of corresponding Semiconductor substrate first area;

Remove the barrier layer, the phase-change material layers that are not covered by photoresist, form the patterned phase change material layer at described bottom electrode, and above the dielectric layer on the Semiconductor substrate first area, form pseudo-phase transformation pad, exist between described pseudo-phase transformation pad and the patterned phase change material layer at interval, described pseudo-phase transformation pad comprises two parts at least, exists at interval between the adjacent part.

5. manufacture method according to claim 4 is characterized in that, the material on described barrier layer is TiN.

6. manufacture method according to claim 1 is characterized in that, the width at interval is 40nm～180nm between described part and the adjacent part.

7. manufacture method according to claim 1 is characterized in that, the width of described pseudo-phase transformation pad is that 1 μ m～10 μ m, length are 1 μ m～10 μ m.

8. manufacture method according to claim 1 is characterized in that, utilizes the HF acid that contains water to carry out described clean step, and the volume ratio of water and HF acid is 1000: 1～15000: 1.

9. manufacture method according to claim 1 is characterized in that, the time of described clean is 20s～120s.

10. manufacture method according to claim 1 is characterized in that, described dielectric layer is PETEOS.

11. a phase transition storage is characterized in that, comprising:

Dielectric layer, it is positioned on the Semiconductor substrate that comprises first area, second area;

Bottom electrode, it is located in the dielectric layer on the Semiconductor substrate second area;

The patterned phase change material layer, it is positioned at the bottom electrode top;

Puppet phase transformation pad, the dielectric layer top that it is positioned on the Semiconductor substrate first area exists at interval between described pseudo-phase transformation pad and the described patterned phase change material layer, and described pseudo-phase transformation pad comprises two parts, existence interval between the adjacent part at least.

12. phase transition storage according to claim 11 is characterized in that, the upper surface of described bottom electrode and described dielectric layer flush or be lower than described dielectric layer surface.

13. phase transition storage according to claim 11 is characterized in that, described patterned phase change material layer, pseudo-phase transformation pad top are provided with the barrier layer.

14. phase transition storage according to claim 13 is characterized in that, the material on described barrier layer is TiN.

15. phase transition storage according to claim 11 is characterized in that, the width at interval is 40nm～180nm between described part and the adjacent part.

16. phase transition storage according to claim 11 is characterized in that, the width of described pseudo-phase transformation pad is that 1 μ m～10 μ m, length are 1 μ m～10 μ m.

17. phase transition storage according to claim 11 is characterized in that, described dielectric layer is PETEOS.

Images