CN103295987A - Semiconductor memory card - Google Patents

Abstract

The present invention provides a semiconductor memory card capable of shortening the wiring length from an external connection terminal to a controller chip. A semiconductor memory card according to an embodiment includes a semiconductor memory device (11) having a SiP structure, and the semiconductor memory device (11) includes: a memory chip (24) arranged on a wiring substrate (12); a controller chip (29); and a sealing resin layer. The electrode pads (301) of the controller chip (29) electrically connected to the external connection terminals are located in the terminal corresponding area X1 on the second surface 12b of the wiring board 12, along the direction of arrangement of the external connection terminals. The controller chips 29 are arranged parallel to the outer shape side of the first outer shape side S1 side of the wiring board 12 on which the external connection terminals are arranged.

Description

semiconductor memory card

This application enjoys the priority of the earlier application with Japanese Patent Application No. 2012-43680 (filing date: February 29, 2012). This application includes the entire contents of the earlier application by referring to the earlier application.

technical field

Embodiments of the present invention relate to semiconductor memory cards.

Background technique

In memory cards (semiconductor memory cards) that incorporate nonvolatile semiconductor memory chips such as NAND-type flash memory, in order to achieve higher capacity, higher speed, and lower manufacturing costs, etc., they are used in card housings. The structure of a semiconductor storage device with a SiP (SyStem in Packing, System-in-Package) structure in which memory chips and/or controller chips are sealed in one package. A semiconductor storage device having a SiP structure includes: a wiring substrate provided with, for example, external connection terminals; a memory chip and a controller chip mounted on the surface of the wiring substrate opposite to the terminal forming surface; and a sealing resin layer on the wiring substrate. The chip mounting surface is formed to seal the memory chip and the controller chip.

In a semiconductor memory device having a SiP structure, a wiring board is generally used in which wiring layers formed by patterning copper foil are provided on both sides of an insulating resin substrate, and the wiring layers on both sides are electrically connected by via holes. A gold plating layer serving as an external connection terminal is formed on a part of the copper wiring layer provided on the terminal forming surface of the wiring board. In conventional semiconductor memory devices having a SiP structure, there is a problem that the wiring length from an external connection terminal electrically connected to an external device to a controller chip tends to be long. Therefore, the signal transmission speed is lowered, and the substrate area tends to increase due to the lowered wiring density. Therefore, shortening the wiring length from the external connection terminal to the controller chip is desired in order to improve the signal transmission speed of the memory card and/or reduce the size of the wiring board constituting the SiP structure.

Contents of the invention

The problem to be solved by the present invention is to provide a semiconductor memory card capable of shortening the wiring length from an external connection terminal to a controller chip.

A semiconductor memory card according to an embodiment includes a semiconductor memory device having a wiring board, a memory chip, a controller chip, a first metal wire, a second metal wire, and a sealing resin layer, and the wiring board has: a plurality of external The first surface of the connection terminal and the first wiring layer, the second surface with the chip mounting region and the second wiring layer, and the through hole electrically connecting the first wiring layer and the second wiring layer; the memory chip is arranged on the wiring substrate. On the chip mounting area, there are first electrode pads arranged along at least one outer shape; the controller chip is stacked on the memory chip, and there are second electrode pads arranged along at least one outer edge; the first metal wire The first electrode pad of the memory chip is electrically connected to the second wiring layer of the wiring substrate; the second metal wire is electrically connected to the second electrode pad of the controller chip and the second wiring layer of the wiring substrate; the sealing resin layer , formed on the second surface of the wiring substrate in such a manner that the memory chip and the controller chip are jointly sealed with the first and second metal lines. The plurality of external connection terminals are arranged along the first outer shape side so as to be located near the first outer shape side of the wiring board. In the second electrode chip of the controller chip, the electrode pads electrically connected to the external connection terminals are located in the area on the second surface corresponding to the formation area of the plurality of external connection terminals on the first surface of the wiring board. Or in the vicinity of the area, the external connection terminals are arranged along the outer shape side of the controller chip which is parallel to the arrangement direction of the plurality of external connection terminals and located on the first outer shape side side of the wiring board.

Description of drawings

FIG. 1 is a plan view showing a semiconductor memory card according to an embodiment.

FIG. 2 is a plan view showing a semiconductor memory device accommodated in the semiconductor memory card shown in FIG. 1 .

3 is a top perspective view showing the semiconductor memory device according to the first embodiment.

Fig. 4 is a sectional view along line A-A of Fig. 3 .

5 is a perspective view of the terminal formation surface of the wiring substrate in the semiconductor memory device shown in FIG. 3 seen through from the upper surface of the semiconductor memory device.

6 is a perspective view of the chip mounting surface of the wiring substrate in the semiconductor memory device shown in FIG. 3 seen through from the upper surface of the semiconductor memory device.

7 is a top perspective view showing a modified example of the semiconductor memory device of the first embodiment.

8 is a top perspective view showing a semiconductor memory device according to a second embodiment.

Fig. 9 is a cross-sectional view along line A-A of Fig. 8 .

10 is a perspective view of the terminal formation surface of the wiring substrate in the semiconductor memory device shown in FIG. 8 seen through from the upper surface of the semiconductor memory device.

11 is a cross-sectional view of the chip mounting surface of the wiring substrate in the semiconductor memory device shown in FIG. 8 seen through from the upper surface of the semiconductor memory device.

Symbol Description

1 semiconductor memory card; 2 card housing; 3, 31, 41 semiconductor storage device; 12 wiring substrate; 12a first surface; 12b second surface; hole; 19 external connection terminal; 20, 22 gold-plated layer; 21 connection pad; 23 chip carrying area; 24 memory chip; 25 electrode pad; 27, 31 metal wire; 29 controller chip; 30 electrode pad; Resin layer; 34 metal layer (Cu layer); 35 plating wire.

Detailed ways

Hereinafter, the semiconductor memory card according to the embodiment will be described with reference to the drawings. FIG. 1 is a plan view showing a semiconductor memory card according to an embodiment. The semiconductor memory card 1 shown in FIG. 1 is used, for example, as an SD ^TM memory card (SD ^TM card), and includes a pair of upper and lower card cases 2 ; and a semiconductor memory device 3 housed in the card case 2 . The semiconductor memory device 3 includes a SiP-structured semiconductor device. The specific structure of the semiconductor memory device 3 will be described in detail below.

(first embodiment)

The SiP-structure semiconductor memory device according to the first embodiment will be described with reference to FIGS. 3 to 6 . 3 is a top perspective view showing the semiconductor storage device according to the first embodiment, FIG. 4 is a cross-sectional view along line A-A of FIG. 3 , and FIG. A perspective view of the terminal formation surface of the wiring substrate in the memory device. FIG. 6 is a perspective view of the chip mounting surface of the wiring substrate in the semiconductor memory device shown in FIG. picture. The semiconductor storage device 11 ( 3 ) shown in these figures includes a wiring board 12 serving also as a substrate for forming external connection terminals and a substrate for mounting semiconductor chips. The wiring board 12 has a first surface 12a serving as a surface on which external connection terminals are formed, and a second surface 12b serving as a mounting surface for a memory chip and/or a controller chip.

Wiring substrate 12 is provided with as shown in FIG. The first wiring layer 14 provided on the first surface 12 a side; the second wiring layer 15 provided on the second surface 12 b side of the resin substrate 13 ; and the via hole 16 electrically connecting the first wiring layer 14 and the second wiring layer 15 . The first and second wiring layers 14 and 15 are formed, for example, by patterning copper foil laminated on both surfaces of the resin base material 13 according to a wiring pattern. The surfaces of the first and second wiring layers 14 and 15 are covered with solder resists 17 and 18 for insulation protection.

The first wiring layer 14 has external connection terminals 19 . An opening pattern is formed on the solder resist 17 at a portion of the first wiring layer 14 serving as the external connection terminal 19 , and a gold plating layer 20 is formed on the first wiring layer 14 through the opening pattern. The external connection terminal 19 includes the first wiring layer 14 and a gold plating layer 20 as a surface layer. The second wiring layer 15 has connection pads 21 ( 21A, 21B). Opening patterns are formed on the solder resist 18 at portions serving as connection pads 21 of the second wiring layer 15 , and a gold-plated layer 22 is formed on the second wiring layer 15 through these opening patterns. The connection pad 21 includes the second wiring layer 15 and a gold plating layer 22 as a surface layer. The gold-plated layers 20 and 22 are formed by, for example, electroplating.

The first surface 12 a of the wiring board 12 has a first wiring layer 14 and a plurality of external connection terminals 19 as shown in FIGS. 4 and 5 . The plurality of external connection terminals 19 are arranged along the first outer side S1 so as to be located near the first outer side S1 of the wiring board 12 . The second surface 12 b of the wiring board 12 has the second wiring layer 15 and the chip mounting region 23 as shown in FIGS. 3 , 4 and 6 . The second wiring layer 15 has connection pads 21A, 21B. The connection pads 21A serve as connections to the electrode pads of the memory chip arranged in the chip mounting region 23 , and the connection pads 21B serve as connections to the electrode pads of the controller chip stacked on the memory chip.

A memory chip 24 is arranged in the chip mounting region 23 of the wiring board 12 . As the memory chip 24, for example, a semiconductor memory chip such as a NAND flash memory is used. 3 and 4 show a state where eight memory chips 24 are stacked and arranged in the chip mounting region 23 . The number of memory chips 24 mounted on the wiring board 12 is not limited to this. The number of mounted memory chips 24 may be one, two, four, or nine or more. The number of memory chips 24 mounted on the wiring board 12 may be one or more.

In FIGS. 3 and 4 , the plurality of memory chips 24 have the same rectangular shape, and each has electrode pads 25 . The electrode pads 25 are located on the second outer side S2 side of the wiring substrate 12 opposite to the first outer side S1 , and are arranged along the outer side of the memory chip 24 on the second outer side S2 side. A plurality of memory chips 24 constitute a memory chip group 26, which is further divided into two chip groups 26A and 26B. The first chip group 26A includes four memory chips 24 arranged in a stacked state on the chip mounting region 23 of the wiring board 12 . The second chip group 26B includes four memory chips 24 arranged in a stacked state on the first chip group 26A.

The four memory chips 24 constituting the first chip group 26A are stacked in steps such that the respective electrode pads 25 are located on the second outer shape side S2 side of the wiring board 12 and the respective electrode pads 25 are exposed. The electrode pads 25 of the four memory chips 24 are sequentially connected via metal wires 27 . In the first chip group 26A, the electrode pads 25 of the memory chip 24 positioned on the lowermost layer are electrically connected to the connection pads 21A of the wiring board 12 via metal wires 27 . On the first chip group 26A, the second chip group 26B is arranged via a partition layer 28 made of insulating resin.

The four memory chips 24 constituting the second chip group 26B are stacked in steps such that the respective electrode pads 25 are located on the second outer shape side S2 side of the wiring board 12 and the respective electrode pads 25 are exposed. The electrode pads 25 of the four memory chips 24 are sequentially connected via metal wires 27 . In the second chip group 26B, the electrode pads 25 of the memory chip 24 positioned on the lowermost layer are electrically connected to the connection pads 21A of the wiring board 12 via the metal wires 27 . In the first chip group 26A, the metal wires 27 connected to the electrode pads 25 of the memory chip 24 located on the uppermost layer are embedded in the insulating resin partition layer 28, thereby preventing them from interfering with the electrode pads 25 of the second chip group 26B. The lowermost memory chip 24 contacts.

A controller chip 29 is laminated on the memory chip group 26 . The controller chip 29 selects a chip for writing and/or reading data from a plurality of memory chips 24, writes data to the selected memory chip 24, and stores data in the selected memory chip 24. Data readout, etc. The controller chip 29 has an L-shaped pad structure with electrode pads 30A arranged along the long side 29a and electrode pads 30B arranged along the short side 29b. The controller chip 29 is arranged such that the long side 29 a is located on the first outer side S1 side of the wiring board 12 , that is, on the first outer side S1 side where the plurality of external connection terminals 19 are arranged, and is parallel to the first outer side S1 .

Electrode pads 30 ( 30A, 30B) of controller chip 29 are electrically connected to connection pads 21B of wiring board 12 via metal wires 31 . The electrode pads 30A arranged along the long side 29a of the controller chip 29 are electrically connected via the wire 31 to the connection pad 21B in the pad area provided on the first outer shape side S1 side of the wiring substrate 12. 32A configuration. The electrode pads 30B arranged along the short side 29b of the controller chip 29 are electrically connected via the wire 31 to the connection pad 21B in the pad area provided on the third external side S3 side of the wiring substrate 12. 32B configuration.

On the second surface 12 b of the wiring board 12 on which the memory chip 24 and/or the controller chip 29 are mounted, a sealing resin layer 33 made of, for example, epoxy resin is molded. The memory chip 24 and/or the controller chip 29 are integrally sealed together with the metal wires 27 , 31 and the like by the sealing resin layer 33 . These constitute the semiconductor memory device 11 ( 3 ) having a SiP structure. As described above, the semiconductor memory card 1 is configured by accommodating the SiP-structured semiconductor memory device 11 in the card case 2 . As shown in FIG. 1 , the card case 2 has openings 4 through which external connection terminals 19 are exposed.

However, memory cards such as the above-mentioned SD ^TM card are required to further increase the storage capacity. Therefore, memory cards having a storage capacity of 64 GB or more are being put into practical use. In such memory cards, it is desired to increase the transmission speed of digital signals in addition to the increase in storage capacity. Therefore, the practical use of a memory card whose theoretical maximum transmission rate of a digital signal is 50 MB/sec or more is progressing. That is, a memory card whose maximum standard value of data read/write speed between the memory card and an external device (host) is 50 MB/sec or higher is being put into practical use. Here, a memory card having the above-mentioned signal transmission speed is called a high-speed operation type (high-speed transmission type) memory card.

For the above-mentioned high-speed operation type memory card, in order to improve the characteristics of the interface (IF) signal between the external device and the memory card, and to meet the transmission speed of the above-mentioned digital signal, it is desired to shorten the communication between the external device and the external device. The wiring length (signal wiring length for IF) from the electrically connected external connection terminal to the electrode pad of the controller chip. Therefore, in the semiconductor memory card 1 of this embodiment, among the electrode pads 30 of the controller chip 29 , the electrode pads (electrode pads for IF) 301 that are directly electrically connected to the external connection terminals 19 are arranged on the wiring board 12 . Inside the region (terminal corresponding region) X1 on the second surface 12 b corresponding to the formation region of the external connection terminal 19 on the first surface 12 a. In addition, the electrode pad 301 for IF may be arrange|positioned near the terminal corresponding area|region X1.

When disposing the IF electrode pad 301 in the terminal corresponding area X1, the controller chip 29 is stacked on the memory chip 24 (memory chip group 26) such that its long side 29a is parallel to the direction in which the external connection terminals 19 are arranged. The first external side S1 of the wiring board 12 , and the long side 29 a is located on the first external side S1 side of the wiring board 12 . IF electrode pads 301 are arranged along the long side 29 a of such a controller chip 29 . The IF electrode pad 301 is electrically connected to the connection pad 21B in the pad region 32A provided on the first outer side S1 side of the wiring board 12 via the wire 31 .

Furthermore, in order to dispose the IF electrode pad 301 near the center of the terminal-corresponding region X1 on the second surface 12b of the wiring board 12, the IF electrode pad 301 is disposed close to the long side 29a of the controller chip 29. The terminal corresponds to the center of the area X1. That is, the position of the IF electrode pad 301 on the long side 29a of the controller chip 29 is set such that the IF electrode pad 301 is in contact with the other electrode pads 30 of the controller chip 29 except the IF electrode pad 301. It is closer to the center of the terminal corresponding area X1 than the terminal.

By applying the arrangement positions of the IF electrode pads 301 as described above, the signal wiring length from the external connection terminal 19 to the IF electrode pads 301 of the controller chip 29 can be shortened. That is, when the IF electrode pad 301 is arranged along the short side 29b of the controller chip 29 and/or the controller chip 29 is on the second surface 12b of the wiring substrate 12 (for example, the side of the memory chip 24 in FIG. 3 Furthermore, compared to the case where the wiring board 12 is arranged on the outer side S3 side), the respective distances from the IF electrode pad 301 to the plurality of external connection terminals 19 are shortened, so the length of the IF signal wiring can be shortened.

In the semiconductor storage device 11 shown in FIG. 3, the controller chip 29 having an L-shaped pad structure is applied, so the electrode pads 30B arranged along the short side 29b of the controller chip 29 and the connecting pads 21B The bonding wire restricts the arrangement position of the IF electrode pad 301 . As shown in FIG. 7 , when the controller chip 29 having a pad structure on one side of a long side is applied, the IF electrode pad 301 can be disposed more centrally in the terminal corresponding region X1 . In any case, by arranging the IF electrode pads 301 along the long side 29 a of the controller chip 29 , the signal wiring length from the external connection terminal 19 to the IF electrode pads 301 can be shortened.

In addition, in order to shorten the wiring length from the external connection terminal 19 provided on the first surface 12a of the wiring board 12 to the connection pad 21B provided on the second surface 12b (the connection pad 21B arranged in the pad region 32A) A part of the via hole 16 electrically connecting the first wiring layer 14 and the second wiring layer 15 is provided between the plurality of external connection terminals 19 . In FIGS. 5 and 6 , the through hole 161 is a through hole for signal wiring, and is provided between the plurality of external connection terminals 19 . By using such a signal wiring via hole 161 , the signal wiring length from the external connection terminal 19 to the IF electrode pad 301 of the controller chip 29 can be further shortened. In addition, FIG. 5 omits illustration of a part of the wiring (wiring from the connection pad 21A to the connection pad 21B, etc.).

As described above, the IF electrodes from the external connection terminal 19 to the controller chip 29 can be shortened based on the arrangement position of the IF electrode pad 301 and/or the electrical connection structure between the first wiring layer 14 and the second wiring layer 15 . The signal wiring length up to the pad 301 improves the electrical characteristics of the IF signal between the external device and the semiconductor memory card 1 . Therefore, the transmission speed of digital signals can be increased. Furthermore, the capacitive load of the memory card will also affect the characteristics of the IF signal. Therefore, in the semiconductor memory card 1 , a region X2 in which the second wiring layer 15 is not provided is set in a part of the terminal-corresponding region X1 on the second surface 12 b of the wiring substrate 12 . Accordingly, it is possible to reduce the capacitive load when the semiconductor memory card 1 is connected to an external device.

Here, when the region X2 where the second wiring layer 15 is not provided is set in a part of the terminal-corresponding region X1, if the region X2 is set as a blank region (a region where nothing is provided), the memory chip 24 and/or the control When the device chip 29 is mounted and/or when the sealing resin layer 33 is formed, warping of the wiring board 12 may become noticeable. Therefore, in the region X2 , the metal layer (Cu layer) 34 constituting the second wiring layer 15 is partially provided in a state electrically independent from the second wiring layer 15 . FIG. 6 shows a state where Cu layer 34 having a dot pattern is formed in region X2. Such a dummy pattern of the Cu layer 34 contributes to reducing the capacity load of the semiconductor memory card 1 while suppressing warpage of the wiring substrate 12 .

Furthermore, the plated wires also affect the capacitive load of the memory card. That is, the second wiring layer 15 has plating leads 35 for forming the surface layer (gold plating layer) 20 of the external connection terminal 19 by plating. If the plating wire 35 becomes longer, the capacitive load when the semiconductor memory card 1 is connected to an external device becomes larger. Therefore, the plating leads 35 provided on the second surface 12 b of the wiring substrate 12 are connected to the first surface 12 a of the wiring substrate 12 through the through holes (through holes for plating leads) 162 provided between the plurality of external connection terminals 19 . The external connection terminal 19 is electrically connected to and drawn out with respect to the first outer side S1 of the wiring board 12 . Thereby, the length of the plating lead wire 35 which forms the gold plating layer 20 of the external connection terminal 19 by electroplating can be shortened significantly.

As mentioned above, by shortening the signal wiring length from the external connection terminal 19 to the IF electrode pad 301 of the controller chip 29, and utilizing the formation of the dummy pattern of the Cu layer 34 and/or the shortening of the plating wire 35 to reduce the semiconductor The capacitive load of the memory card 1 can improve the electrical characteristics of the IF signal between the external device and the semiconductor memory card 1 . Therefore, the transmission speed of digital signals between the external device and the semiconductor memory card 1 can be increased. That is, it is possible to improve the semiconductor memory card 1 capable of realizing a theoretical maximum transfer rate of a digital signal of 50 MB/sec or higher. Thus, the semiconductor memory card 1 of the first embodiment is suitable for a high-speed operation type memory card.

In the semiconductor memory card 1 according to the first embodiment, a part of the via hole 16 electrically connecting the first wiring layer 14 and the second wiring layer 15 of the wiring board 12 is provided between the plurality of external connection terminals 19 . Therefore, the second wiring layer 15 can be formed up to the terminal formation region X1 on the second surface 12 b of the wiring board 12 . In this way, the formation density of the second wiring layer 15 is increased, and the miniaturization of the wiring board 12 is realized. As shown in FIG. 4 , it is possible to increase the storage capacity and reduce the size of the wiring board 12 by stacking the memory chips 24 in multiple layers.

In addition, by increasing the formation density of the second wiring layer 15, the connection pads 21A connected to the memory chip 24 can be collectively arranged on the second external side S2 side of the wiring substrate 12, and the connection pads connected to the controller chip 29 can be concentrated. The pad 21B is arranged on the first outer side S1 side of the wiring board 12 . This also enables miniaturization of the wiring board 12 . In addition, the wiring shape and/or the arrangement structure of the connection pads as described above can be realized without increasing the number of wiring layers of the wiring board 12 . By doing so, the manufacturing cost of the SiP-structured semiconductor memory device 11 and the manufacturing cost of the semiconductor memory card 1 can be reduced.

Furthermore, as shown in FIG. 4, by laminating the first chip group 26A and the second chip group 26B so that the pad array sides of the memory chips 24 constituting them face the same direction, it is possible to connect the memory chips 24 and the wires. The metal wires 27 of the substrate 12 are bonded in the same direction. Accordingly, the mounting area of the memory chip 24 on the wiring board 12 and/or the number of wiring layers of the wiring board 12 can be reduced. Therefore, when the area of the wiring board 12 is made the same, since a larger memory chip 24 can be mounted, the memory capacity can be increased with the semiconductor memory device 11 having the same outer shape. In addition, when the area of the memory chip 24 is made the same, the size of the wiring board 12 and the semiconductor memory device 11 can be reduced.

(Second embodiment)

Next, the SiP-structure semiconductor memory device according to the second embodiment will be described with reference to FIGS. 8 to 11 . 8 is a top perspective view showing a semiconductor storage device according to a second embodiment, FIG. 9 is a cross-sectional view along line A-A of FIG. 8 , and FIG. 10 is a perspective view from the upper surface (molding surface) of the semiconductor storage device. 8 is a perspective view of the terminal formation surface of the wiring substrate of the semiconductor storage device shown in FIG. The perspective view seen from the front. In addition, the same code|symbol is attached|subjected to the same part as 1st Embodiment, and the description is abbreviate|omitted partly.

A semiconductor storage device 41 ( 3 ) shown in FIGS. 8 to 11 includes a wiring board 12 similarly to the first embodiment. The wiring board 12 has, like the first embodiment, the first wiring layer 14 provided on the first surface 12a side of the resin base material 13, and the second wiring layer provided on the second surface 12b side of the resin base material 13. 15; and a via hole 16 electrically connecting the first wiring layer 14 and the second wiring layer 15. The first wiring layer 14 has external connection terminals 19 . The second wiring layer 15 has connection pads 21 ( 21A, 21B).

The first surface 12 a of the wiring board 12 has a first wiring layer 14 and a plurality of external connection terminals 19 as shown in FIGS. 9 and 10 . The plurality of external connection terminals 19 are arranged along the first outer side S1 so as to be located near the first outer side S1 of the wiring board 12 . The second surface 12 b of the wiring board 12 has the second wiring layer 15 and the chip mounting region 23 as shown in FIGS. 8 , 9 and 11 . In the chip mounting region 23 of the wiring board 12 , a memory chip 24 and a controller chip 29 are arranged side by side. The number of mounted memory chips 24 is not limited to one, but may be two, four, eight or more.

The memory chip 24 has electrode pads 25 . The electrode pads 25 are located on the second outer side S2 side of the wiring board 12 and are arranged along the outer side of the memory chip 24 on the second outer side S2 side. The electrode pads 25 of the memory chip 24 are electrically connected to the connection pads 21A of the wiring board 12 via metal wires 27 . The controller chip 29 has a pad structure on one side of a long side, and has electrode pads 30 arranged along the long side. The electrode pads 30 of the controller chip 29 are electrically connected to the connection pads 21B of the wiring board 12 via metal wires 31 .

A part of the via hole 16 electrically connecting the first wiring layer 14 and the second wiring layer 15 is provided between the plurality of external connection terminals 19 . Among the through holes 16 provided between the external connection terminals 19 , the through hole 161 is a through hole for signal wiring, and forms a part of signal wiring electrically connecting the external connection terminal 19 and the electrode pad 30 of the controller chip 29 . That is, at least a part of the plurality of external connection terminals 19 is electrically connected to the electrode pad 30 of the controller chip 29 via the via hole 161 for signal wiring. Thereby, the signal wiring length from the external connection terminal 19 to the electrode pad 30 of the controller chip 29 can be shortened.

In addition, among the through-holes 16 provided between the external connection terminals 19 , the through-holes 162 are through-holes for plating wires, and form a part of wiring electrically connecting the external connection terminals 19 and the plating wires 35 . That is, at least a part of the plurality of external connection terminals 19 is electrically connected to the plating lead wire 35 through the plating lead wire through-hole 162 , and the plating lead wire 35 is drawn out from the first outer shape side S1 of the wiring board 12 . With these, the length of the plating lead wire 35 that forms the gold plating layer 20 of the external connection terminal 19 by plating can be significantly shortened.

On the second surface 12 b of the wiring board 12 on which the memory chip 24 and/or the controller chip 29 are mounted, a sealing resin layer 33 made of, for example, epoxy resin is molded. The memory chip 24 and/or the controller chip 29 are integrally sealed together with the metal wires 27 , 31 and the like by a sealing resin layer 33 . These constitute the semiconductor memory device 11 ( 3 ) having a SiP structure. As described above, the semiconductor memory card 1 is configured by accommodating the SiP-structured semiconductor memory device 11 in the card case 2 . The card case 2 has an opening 4 through which an external connection terminal 19 is exposed, as shown in FIG. 1 .

As described above, by providing a part ( 161 , 162 ) of the through hole 16 between the plurality of external connection terminals 19 , it is possible to shorten the signal wiring length and/or the plating wire 35 from the external connection terminal 19 to the controller chip 29 . length. In addition, a region on the second surface 12 b corresponding to the formation region of the external connection terminal 19 on the first surface 12 a of the wiring board 12 (terminal corresponding region) can be used as a wiring region. By doing so, the wiring density per unit area of the wiring board 12 can be increased, so that the size of the wiring board 12 can be reduced. Accordingly, the manufacturing cost of the SiP-structured semiconductor memory device 11 and the manufacturing cost of the semiconductor memory card 1 can be reduced.

Furthermore, by shortening the signal wiring length from the external connection terminal 19 to the controller chip 29, the signal transmission speed with external devices is improved. By shortening the length of the plating wire 35, the capacitive load when the semiconductor memory card 1 is connected to an external device is reduced. Through these, it is possible to cope with high-speed operation of the semiconductor memory card 1 . In addition, the through-holes 161, 162 provided between the plurality of external connection terminals 19 are shielded by the underside of the rib 5 between the openings 4 when the semiconductor memory device 41 is housed in the card case 2, so that the memory card 1 is protected from the memory card 1. It cannot be seen on the appearance of the memory card 1, and it will not have a negative impact on the work of the memory card 1, etc.

In addition, although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and/or modifications thereof are included in the scope and/or gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Claims (5)

1. A semiconductor memory card comprising a semiconductor memory device, The semiconductor memory device has: A wiring board having: a first surface provided with a plurality of external connection terminals and a first wiring layer; a second surface provided with a chip mounting region and a second wiring layer; and connecting the first wiring layer and the second wiring layer via holes for layer electrical connection; A memory chip disposed on the chip mounting region of the wiring substrate, having first electrode pads arranged along at least one outer shape side; A controller chip, which is stacked on the memory chip, has a second electrode pad arranged along at least one outer shape side; a first metal wire electrically connecting the first electrode pad of the memory chip to the second wiring layer of the wiring substrate; a second metal wire electrically connecting the second electrode pad of the controller chip and the second wiring layer of the wiring substrate; and a sealing resin layer formed on the second surface of the wiring substrate so as to seal the memory chip and the controller chip together with the first and second metal wires, The semiconductor memory card is characterized in that, The plurality of external connection terminals are arranged along the first outer side of the wiring board so as to be located near the first outer side, and the second electrode pads of the controller chip are connected to the first outer side. The electrode pads to which the external connection terminals are electrically connected are located in the area of the second surface corresponding to the formation area of the plurality of external connection terminals in the first surface of the wiring substrate or within the In the vicinity of the region, the controller chip is arranged along the outer shape side of the controller chip which is parallel to the arrangement direction of the plurality of external connection terminals and located on the side of the first outer shape side of the wiring substrate, The terminal-corresponding region on the second surface of the wiring substrate has a region where the second wiring layer is not provided, and in the region where the second wiring layer is not provided, a portion of the second wiring layer is formed. the metal layer is partially provided in a state not electrically connected to the second wiring layer, At least a part of the through hole is provided between the plurality of external connection terminals, and at least a part of the plurality of external connection terminals is connected to the through hole provided between the plurality of external connection terminals. The 2nd electrode pad of the controller chip is electrically connected, Each of the plurality of external connection terminals has a plating layer as a surface layer, and the second wiring layer of the wiring board has a plating lead forming the plating layer, at least a part of the plating lead is passed through the plurality of The through holes provided between the external connection terminals are electrically connected to the external connection terminals. 2. A semiconductor memory card comprising a semiconductor memory device, The semiconductor memory device has: A wiring board having: a first surface provided with a plurality of external connection terminals and a first wiring layer; a second surface provided with a chip mounting region and a second wiring layer; and connecting the first wiring layer and the second wiring layer via holes for layer electrical connection; A memory chip disposed on the chip mounting region of the wiring substrate, having first electrode pads arranged along at least one outer shape side; A controller chip, which is stacked on the memory chip, has a second electrode pad arranged along at least one outer shape side; a first metal wire electrically connecting the first electrode pad of the memory chip to the second wiring layer of the wiring substrate; a second metal wire electrically connecting the second electrode pad of the controller chip and the second wiring layer of the wiring substrate; and a sealing resin layer formed on the second surface of the wiring substrate so as to seal the memory chip and the controller chip together with the first and second metal wires, The semiconductor memory card is characterized in that, The plurality of external connection terminals are arranged along the first outer side so as to be located near the first outer side of the wiring board, Among the second electrode pads of the controller chip, electrode pads electrically connected to the external connection terminals are connected to the plurality of external connection terminals on the first surface of the wiring substrate. In the area of the second surface corresponding to the area where the terminal is formed or in the vicinity of the area, it is located along the first outer shape of the wiring board parallel to the arrangement direction of the plurality of external connection terminals. The outlines of the controller chips are arranged side by side. 3. The semiconductor memory card according to claim 2, wherein: The terminal-corresponding region on the second surface of the wiring substrate has a region where the second wiring layer is not provided, and the second wiring layer is formed in the region where the second wiring layer is not provided. The metal layer is partially provided in a state not electrically connected to the second wiring layer. 4. A semiconductor memory card comprising a semiconductor memory device, The semiconductor memory device has: A wiring board having: a first surface provided with a plurality of external connection terminals and a first wiring layer; a second surface provided with a chip mounting region and a second wiring layer; and connecting the first wiring layer and the second wiring layer via holes for layer electrical connection; A memory chip disposed on the chip mounting region of the wiring substrate, having first electrode pads arranged along at least one outer shape side; A controller chip disposed on the chip mounting area of the wiring substrate or on the memory chip, and having second electrode pads arranged along at least one outer shape side; a first metal wire electrically connecting the first electrode pad of the memory chip to the second wiring layer of the wiring substrate; a second metal wire electrically connecting the second electrode pad of the controller chip and the second wiring layer of the wiring substrate; and a sealing resin layer formed on the second surface of the wiring board so as to seal the memory chip and the controller chip together with the first and second metal wires, The semiconductor memory card is characterized in that, at least a part of the through hole is provided between the plurality of external connection terminals, At least a part of the plurality of external connection terminals is electrically connected to the second electrode pad of the controller chip through the through hole provided between the plurality of external connection terminals. 5. The semiconductor memory card according to claim 4, wherein: Each of the plurality of external connection terminals has a plating layer as a surface layer, and the second wiring layer of the wiring substrate has a plating lead forming the plating layer, At least a part of the plating lead is electrically connected to the external connection terminal through the through hole provided between the plurality of external connection terminals.

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