CN103294648A - Block matrix multiplication vectorization method supporting vector processor with multiple MAC (multiply accumulate) operational units - Google Patents

Abstract

A block matrix multiplication vectorization method for a vector processor supporting multiple MAC operation parts, the process is: (1) according to the number p of the vector processing unit VPE of the vector processor, the number m of MAC operation parts in the VPE, and the vector memory The capacity s and the data size d of matrix elements determine the block size blocksize of the optimal sub-matrix, determine the number of columns and rows of the sub-matrix of the multiplier matrix B, and determine the number of rows and the number of sub-matrix of the multiplicand matrix A Number of columns; (2) Divide the capacity s of the vector memory into two storage areas of equal capacity, Buffer0 and Buffer1, and perform sub-matrix multiplication between Buffer0 and Buffer1 in a ping-pong manner until the entire matrix multiplication calculation is completed. The invention has the advantages of simple implementation, convenient operation, improved parallelism of vector processors, and improved computing efficiency of processors.

Description

Block Matrix Multiplication Vectorization Method for Vector Processors Supporting Multi-MAC Operation Units

technical field

The invention mainly relates to the technical field of data processing, in particular to a block matrix multiplication vectorization method supporting a multi-MAC operation unit vector processor.

Background technique

With the increasing demand for high-performance computing for computing-intensive applications such as solving large-scale dense linear equations, 4G wireless communications, radar signal processing, high-definition video and digital image processing, computer architectures have undergone significant changes, and many new architectures have emerged, such as Many-core architecture, heterogeneous multi-core architecture, stream processor architecture and vector processor architecture, etc. These new architectures integrate multiple processor cores on a single chip, and each core contains a wealth of computing components , greatly improving the computing performance of the chip; at the same time, it also poses new challenges to software development. Because a large number of existing programs and algorithms are designed based on single-core processors, how to fully develop parallelism at all levels and efficiently parallelize and vectorize these application algorithms is currently facing the architectural characteristics of multi-core and multi-computing components. main difficulty.

"Matrix multiplication" is one of the core modules commonly used in high-performance computing (High Performance Computing, HPC), and is a typical calculation-intensive and memory-intensive application. The bandwidth requirement is very high, and the calculation time complexity is very high, about O(N ³ ), where N is the size of the matrix. The traditional method of implementing matrix multiplication with triple loops has relatively low calculation and memory access, missing data in the Cache, and a large proportion of matrix data moving overhead, resulting in low computing efficiency of the processor. The block matrix multiplication method divides the multiplication of a large matrix into a series of sub-matrix multiplications. By setting the block size of the sub-matrix reasonably, the block size of the sub-matrix usually satisfies blocksize<=sqrt(M/3), and M is Cache capacity, so that the data access during sub-matrix calculation can all be hit in the Cache, and the calculation time of the entire large matrix multiplication is reduced by reducing the calculation time of the sub-matrix, thereby greatly improving the operation efficiency of the processor.

Figure 1 is a schematic diagram of the general structure of a multi-MAC computing unit vector processor, which includes a scalar processing unit (Scalar Processing Unit, SPU) and a vector processing unit (Vector Processing Unit, VPU). The SPU is responsible for scalar task calculation and flow control, and the VPU is responsible for Vector computing, including several vector processing elements (Vector Processing Element, VPE), each VPE contains multiple computing functional components such as MAC0 and MAC1, as well as other functional components such as ALU and BP. SPU and VPU provide data channels to transmit and exchange data. The vector data access unit supports Load/Store of vector data and provides a large-capacity dedicated vector memory instead of the Cache mechanism of single-core processors. The existing block matrix multiplication method is not suitable for this type of vector processor. Therefore, there is an urgent need to design an efficient vectorization method for block matrix multiplication of vector processors that supports multi-MAC computing units, so as to optimize the computing efficiency of vector processors.

Contents of the invention

The technical problem to be solved by the present invention is: aiming at the technical problems existing in the prior art, the present invention provides a multi-MAC computing unit that is simple to implement, easy to operate, can improve the parallelism of vector processors, and can improve the computing efficiency of processors Blocked matrix multiplication vectorization method for vector processors.

In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

A block matrix multiplication vectorization method supporting a multi-MAC operation unit vector processor, the process is as follows:

(1) According to the number p of the vector processing unit VPE of the vector processor, the number m of MAC operation units in the VPE, the capacity s of the vector memory and the data size d of the matrix elements, determine the optimal sub-matrix block size blocksize, Determine the number of columns and the number of rows of the submatrix of the multiplier matrix B and determine the number of rows and the number of columns of the submatrix of the multiplicand matrix A;

(2) Divide the capacity s of the vector memory into two storage areas with equal capacity, Buffer0 and Buffer1, and realize the multiplication of the sub-matrix between Buffer0 and Buffer1 in a ping-pong manner until the entire matrix multiplication calculation is completed.

As a further improvement of the present invention:

In the step (1), the number of columns of the sub-matrix of the multiplier matrix B is p*m, and the number of rows is (s/2/2)/(p*m*d); the sub-matrix of the multiplier matrix B is determined After the block size, determine the sub-matrix block size of the multiplicand matrix A; the number of rows and the number of columns of the sub-matrix of the multiplicand matrix A are all equal to the number of rows of the sub-matrix of the multiplier matrix B, i.e. (s/ 2/2)/(p*m*d).

The scalar processing unit SPU of the vector processor reads each element in each row of the multiplicand sub-matrix A in turn, and expands into a vector data; the B0 row of the multiplier sub-matrix B is read by the vector processing unit VPU The data and each element of the aforementioned vector data are multiplied and accumulated separately; when the A0 row data of the multiplicand sub-matrix is traversed, the C0 row data of the result sub-matrix C is calculated; when all the data of the multiplicand sub-matrix A are traversed When running, the calculation of the result sub-matrix C is completed.

In the step (2), the storage area Buffer0 is used for the sub-matrix storage of the multiplier matrix B and the output result matrix C in this sub-matrix multiplication, and at the same time, the multiplication required for the next sub-matrix multiplication is transferred by the DMA controller The sub-matrix data of the number matrix B is moved to the storage area Buffer1, and the last result sub-matrix data is moved to the external memory.

Compared with the prior art, the present invention has the advantages that: the present invention determines the optimal sub-matrix block size blocksize according to the architectural characteristics of the vector processor and the data size of the matrix elements, effectively improving the calculation and memory access of the processor. Compared with that, the multiplication of the sub-matrix can be realized by double-buffering ping-pong method, which can effectively overlap the data moving time with the computing time and reduce the total computing time. The scalar processing unit SPU of the vector processor reads the row data of the multiplicand sub-matrix, and expands it into vector data, and performs multiplication and accumulation for each element of the vector data of the multiplier sub-matrix read by the vector processing unit VPU by row. , avoiding access to column data and summation of vector data. These advantages make the method of the present invention simple to implement, easy to operate, can fully tap the parallelism of each level of instructions, data, tasks, etc. Advantages of the high-performance computing capabilities of component vector processors.

Description of drawings

FIG. 1 is a schematic diagram of a general structure of a vector processor with multiple MAC operation units.

Fig. 2 is a schematic diagram of the execution flow of the method of the present invention.

Fig. 3 is a schematic flow diagram of determining the block size of the optimal sub-matrix according to the architectural characteristics of the vector processor in a specific embodiment.

Fig. 4 is an operational schematic diagram of the specific implementation process of sub-matrix multiplication in the present invention.

Fig. 5 is a schematic flow diagram of implementing sub-matrix multiplication in a double-buffered ping-pong manner in a specific embodiment.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 2, the present invention supports the block matrix multiplication vectorization method of the multi-MAC operation unit vector processor, and the specific process is:

(1) First, according to the number p of the vector processing unit VPE of the vector processor, the number m of MAC operation units in the VPE, the capacity s of the vector memory, and the data size d of the matrix elements, determine the optimal sub-matrix block size blocksize , determine the number of columns and rows of the sub-matrix of the multiplier matrix B and determine the number of rows and columns of the sub-matrix of the multiplicand matrix A.

(2) Divide the capacity s of the vector memory into two storage areas with equal capacity, Buffer0 and Buffer1, and realize the multiplication of the sub-matrix between Buffer0 and Buffer1 in a ping-pong manner until the entire matrix multiplication calculation is completed.

As shown in Figure 3, in specific applications, according to the number p of the vector processing unit VPE of the vector processor, the number m of the MAC operation parts in each VPE, the capacity s of the vector memory and the data size d of the matrix elements, determine the optimal Optimal sub-matrix block size blocksize. Wherein, the number of columns of the sub-matrix of the multiplier matrix B is p*m, and the number of rows is (s/2/2)/(p*m*d). After the sub-matrix block size of the multiplier matrix B is determined, the sub-matrix block size of the multiplicand matrix A is determined. Both the number of rows and the number of columns of the sub-matrix of the multiplier matrix A are equal to the number of rows of the sub-matrix of the multiplier matrix B, that is, (s/2/2)/(p*m*d). As an example, assume that the data of the matrix elements is single-precision floating-point data, the data size is 4B (bytes), the capacity of the vector memory is 1024KB, the number of vector processing units VPE is p=16, and the MAC in each VPE The number of operation components is m=2, then the number of columns of the sub-matrix of the multiplier matrix B is p*m=16*2=32 columns, and the number of rows is (1024*1024/2/2)/(16*2*4 )=2048 rows. The number of rows and the number of columns of the sub-matrix of the multiplicand matrix A are both equal to 2048.

As shown in FIG. 4 , in this embodiment, the sub-matrix of the multiplier matrix B has 4 columns and 8 rows; the sub-matrix of the multiplicand matrix A has 8 rows and 8 columns. The method adopted is to sequentially read each element in each row of the multiplicand sub-matrix A by the scalar processing unit SPU of the vector processor, and expand it into a vector data, such as the a00 element expansion of the A0 row in Figure 4 into a vector (a00, a00, a00, a00), and the a01 element expands into a vector (a01, a01, a01, a01). The B0 row data (b00, b01, b02, b03) of the multiplier sub-matrix B is read by the vector processing unit VPU, and is multiplied and accumulated with each element of the aforementioned vector data. After traversing the A0 row data of the multiplicand sub-matrix, calculate the C0 row data (c00, c01, c02, c03) of the result sub-matrix C. When all the rows of the multiplicand sub-matrix A are traversed, the calculation of the result sub-matrix C is completed.

As shown in Figure 5, the block matrix multiplication in this embodiment adopts the ping-pong method of double buffering (Buffer) to realize the multiplication of the sub-matrix, and the capacity s of the vector memory is divided into two storage areas Buffer0 and Buffer1 with equal capacity, where Buffer0 is used for the sub-matrix storage of the multiplier matrix B and the output result matrix C in this sub-matrix multiplication, and at the same time transfer the sub-matrix data of the multiplier matrix B required for the next sub-matrix multiplication to Buffer1 through the DMA controller , and the last result sub-matrix data is moved to the external memory.

To sum up, through the block matrix multiplication vectorization method of the vector processor supporting multi-MAC operation components implemented by the present invention, the optimal sub-matrix block size blocksize can be determined according to the architecture characteristics of the vector processor. Using the double-buffered ping-pong method to realize the multiplication of the sub-matrix can effectively overlap the data moving time with the computing time and reduce the total computing time. The scalar processing unit SPU of the vector processor reads the row data of the multiplicand sub-matrix, and expands it into vector data, and performs multiplication and accumulation for each element of the vector data of the multiplier sub-matrix read by the vector processing unit VPU by row. , avoiding access to column data and summation of vector data. These advantages make the method of the present invention simple to implement, easy to operate, can fully tap the parallelism of each level of instructions, data, tasks, etc. Advantages of the high-performance computing capabilities of component vector processors.

The above are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions under the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (4)

1. partitioned matrix multiplication vectorization method of supporting many MAC arithmetic unit vector processor is characterized in that flow process is:

(1) according to the quantity p of the vector processing unit VPE of vector processor, quantity m, the capacity s of vector memory of MAC arithmetic unit among the VPE and the size of data d of matrix element, determine the block size blocksize of optimum submatrix, determine line number and the columns of the submatrix of the columns of submatrix of multiplier matrix B and line number and definite multiplicand matrix A;

(2) the capacity s with vector memory is divided into two parts storage area Buffer0 and the Buffer1 that capacity equates, realizes the multiplication of submatrix successively between Buffer0 and Buffer1 with ping-pong, calculates up to whole matrix multiplication and finishes.

2. the partitioned matrix multiplication vectorization method of many MAC of support arithmetic unit vector processor according to claim 1 is characterized in that, in the described step (1), the columns of the submatrix of multiplier matrix B is p*m, and line number is (s/2/2)/(p*m*d); After determining the submatrix block size of multiplier matrix B, determine the submatrix block size of multiplicand matrix A again; The line number of the submatrix of described multiplicand matrix A and columns all equal the line number of the submatrix of multiplier matrix B, i.e. (s/2/2)/(p*m*d).

3. the partitioned matrix multiplication vectorization method of many MAC of support arithmetic unit vector processor according to claim 2, it is characterized in that, the scalar processor unit SPU of described vector processor reads each element in each row of multiplicand submatrix A successively, and is extended to a vector data; Read the B0 line data of multiplier submatrix B and each element of aforementioned vector data carries out multiply accumulating respectively by Vector Processing parts VPU; When having traveled through the A0 line data of multiplicand submatrix, calculate the C0 line data of the Matrix C that bears fruit; When having traveled through all row of multiplicand submatrix A, finish the calculating of the Matrix C that bears fruit.

4. according to the partitioned matrix multiplication vectorization method of claim 1 or 2 or 3 described many MAC of support arithmetic unit vector processors, it is characterized in that, in the described step (2), storage area Buffer0 is used for the multiplier matrix B of this submatrix multiplication and stores with the submatrix of output matrix of consequence C, simultaneously by dma controller will be next time the submatrix data of the needed multiplier matrix B of submatrix multiplication be transported to storage area Buffer1, and the last matrix data that bears fruit is moved external storage.

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