CN103294600B - Based on the automatic design for Measurability method of the automatic design for Measurability system of the EDIF net table level circuit of Perl - Google Patents

Abstract

The invention relates to an automatic testability design method of an automatic testability design system of an EDIF netlist level circuit based on Perl, and relates to an automatic testability design system and an automatic testability design method of an EDIF netlist level circuit. It is designed to meet the needs of automatic design for testability of EDIF netlist-level circuits. The circuit source code analysis module is used to analyze the EDIF netlist-level description of digital logic circuits; the flip-flop modification module is used to complete the testability modification of all flip-flops in EDIF language; the Verilog packaging module is used to describe the circuit to the EDIF netlist Verilog encapsulation; the scan chain connection module is used to complete the scan chain design of the circuit in Verilog language for the EDIF netlist description circuit; the testability circuit generation module is used to re-encapsulate the circuit in Verilog; the test verification module is used to generate test files and Verify the circuit after design for test. The invention is suitable for automatic testability design of EDIF netlist level circuits.

Description

The automatic testability design method of Perl-based EDIF netlist-level circuit automatic testability design system

technical field

The invention relates to an automatic testability design system and an automatic testability design method for EDIF netlist level circuits.

Background technique

Nowadays, with the development of semiconductor technology, integrated circuit chips (IC) have been widely used, and the reliability of integrated circuit chips has become an important issue. The method of testing ICs has become the main way to solve the reliability of ICs, but the low testability of ICs with complex functions seriously restricts the effectiveness of IC testing. The design for testability of IC can effectively improve the controllability and observability of the circuit, and greatly improve the testability of the chip, so that IC testing can be carried out effectively.

The testability design of the circuit is to modify the structure of the original circuit without affecting the function of the circuit, so that the nodes in the circuit that do not have controllability and objectivity can obtain these properties for easy testing. A common method is to transform the flip-flops used in the original circuit into testability flip-flops, and then connect the modified flip-flops into one or several flip-flop chains, called scan chains. The input and output of the scan chain are used as test ports of the circuit, through which the internal nodes of the circuit can be controlled and observed. A commonly used testability trigger is a testability trigger with a multiplexer structure, that is, a multiplexer is added to the input of the original trigger, so that the data of the trigger can be controlled.

In the current circuit design process, the circuit design is often completed by different departments or companies. At the same time, various EDA tools are involved in the entire circuit design process, which involves the problem of data exchange. The EDIF netlist is a standard format for exchanging data between different companies and different EDA tools. EDIF is the English abbreviation of Electronic Design Interchange Format (Electronic Design Interchange Format). It is a data format without copyright restrictions. It proposes and specifies schematic diagrams, symbols and physical layout, interconnection and structural information related to circuit design. . The circuit described by EDIF netlist language can be used as a standard exchange format for information exchange in the design process of each circuit.

EDIF netlist-level circuit is a circuit described in EDIF netlist language. During the circuit design process, the functional design and testability design of the circuit are often separated, and the circuit function designer passes the circuit testability design to the circuit testability designer. Circuit data is often described by EDIF netlist, which mainly describes the use information of each component in the circuit and the connection information between them. By analyzing the EDIF netlist of the circuit, the necessary information of the circuit can be obtained, and the design for testability of the circuit has become an important way of the design for testability of the circuit.

The storage format of EDIF netlist is ASIC coded text format, so it can be analyzed and processed very conveniently using Perl language. The Perl language is an advanced, general-purpose, literal translation, dynamic, and powerful language. Its most important feature is the function of regular expressions integrated inside, as well as the huge third-party code library CPAN. Among them, the regular expression function can process text very well for us, and it can be used to process EDIF netlist very conveniently and efficiently.

In the flip-flop design stage, it is necessary to modify the testability of the flip-flops used in the circuit. The number of flip-flops used in the actual circuit is quite large, so it is necessary to use tools to automate the flip-flops used in the circuit. Revise. Here we can use the Perl language to write automated modification tools to complete this function, instead of time-consuming and laborious manual modification.

In the scan chain design stage, it is necessary to connect flip-flops to circuits that have completed flip-flop modification, and connect those modified flip-flops with testability into one or several chains. Due to the needs of the test, the design of the scan chain often needs to be completed manually, and its connection mode must be modified at any time. Although the EDIF netlist is very general and suitable for software processing, since the EDIF netlist is not a commonly used direct design language, as a circuit designer, it is not very convenient to read and modify it. But at this stage, the designer only needs to know about the flip-flops that need to be connected. Therefore, under the premise of ensuring that the circuit function remains unchanged, the commonly used circuit design language can be used to package the EDIF netlist circuit modified by the trigger, shield the internal information externally and provide the corresponding interface with EDIF for the trigger scan chain design.

In the field of circuit design, Verilog HDL (Verilog Hardware Description Language) is a commonly used design language, which can be used as a design language for encapsulating EDIF netlist circuits, packaging it in the form of Verilog, and providing an interface that conforms to Verilog syntax for external use. Testability designers further facilitate the design. The storage format of the Verilog language is also in the text format, and the packaging work can also be conveniently completed by using the Perl language. At the same time, it can assist scan chain designers to complete the scan chain design work in the Verilog environment.

Contents of the invention

The invention aims at adapting to the requirement of the automatic testability design of the EDIF netlist level circuit, thereby proposing an automatic testability design system and an automatic testability design method of the EDIF netlist level circuit based on Perl.

An automatic testability design system for EDIF netlist-level circuits based on Perl, which includes a circuit source code analysis module 1, a trigger modification module 2, a scan chain design module 3, a testability circuit generation module 4, and a test verification module 5;

The circuit source code analysis module 1 is used to analyze the EDIF netlist-level description of the digital logic circuit, and obtain the information used by all flip-flops in the circuit;

The trigger modification module 2 includes a testability trigger generation module 21 and a trigger testability modification module 22;

The trigger modification module 2 is used to complete the testability modification of all triggers in the file described by the EDIF netlist of the circuit according to the trigger information provided by the circuit source code analysis module;

The scan chain design module 3 includes a Verilog encapsulation module 31 and a scan chain connection module 32;

Verilog encapsulation module 31 is used for according to the circuit EDIF netlist after the trigger information that the circuit source analysis module provides and the trigger modification module provide modification after the trigger, finishes the Verilog encapsulation to EDIF netlist description circuit;

The scan chain connection module 32 is used to complete the circuit scan chain design for the EDIF netlist description circuit using Verilog language according to the trigger information provided by the circuit source code analysis module and the modified circuit EDIF netlist provided by the trigger modification module ;

The testability circuit generation module 4 is used to complete the re-Verilog packaging of the circuit according to the Verilog form of the circuit generated by the scan chain design module, and obtain the final circuit after the testability design;

The test verification module 5 is used to generate test files and verify the design-for-test circuit according to the port and trigger information provided by the circuit source code analysis module and the circuit with completed testability design provided by the testability circuit generation module .

The testability circuit generation module 4 obtains the final circuit design for testability and shields all internal information of the circuit to the outside, and only provides an interface in the form of a common hardware description language.

The automatic testing method of the EDIF netlist level circuit based on Perl, it is realized by the following steps:

Step 1. Use the circuit source code analysis module 1 to analyze the triggers used in the circuit, and use Perl to process in the EDIF environment;

Step 2: Use the trigger modification module 2 to modify the trigger used in the circuit for testability, and use Perl to process it in the EDIF environment;

Step 3. Use Perl to perform Verilog encapsulation on the EDIF circuit after the testability modification of the flip-flop, shield the EDIF details, and then design the scan chain for the flip-flop with the testability modification in the circuit;

Step 4. Use Perl to give the final testable circuit that conforms to Verilog syntax, and after verifying that the modification is correct, use Perl to generate an automatic test file that conforms to Tcl syntax, and then realize the automatic test of the EDIF netlist level circuit.

In step 1, use the circuit source code analysis module 1 to analyze the trigger used in the circuit, and use Perl to process it in the EDIF environment. The specific method is as follows:

Step A1, open the EDIF netlist level circuit file;

Step A2, analyzing the use information of all components in the circuit and the calling information of the circuit from the EDIF netlist level circuit file;

Step A3, from the file of usage information of all components of the circuit obtained in step A2, analyze the calling situation of the specific instance, and save it in the calling format, and save it in the form of a file;

Step A4, from the call information file output in step A3, find the call information related to flip-flops, and analyze the flip-flops used in the circuit.

In step 2, use the trigger modification module 2 to modify the testability of the trigger used in the circuit, and use Perl to process it in the EDIF environment. The specific method is as follows:

Step B1. Obtain the trigger type from all the trigger information analyzed in step 1;

Step B2, generating a testability EDIF component library, which contains testability triggers corresponding to all types of triggers analyzed in step B1;

Step B3, inserting the testability library obtained in step B2 into the EDIF component of the original circuit, the insertion position is after the library related to the flip-flop declaration of the original circuit;

Step B4. Generate trigger modification information according to all trigger information analyzed in step 1;

Step B5. According to the modification information of the generated trigger obtained in step B4, modify the EDIF file in step B3 one by one, modify the reference path of the trigger, add the statement of the test port and the node connection of the test port, and obtain the EDIF file after the modification of the trigger .

In step 3, use Perl to perform Verilog encapsulation on the EDIF circuit that has been modified for testability of the flip-flop, shield the details of the EDIF, and then design the scan chain for the flip-flop that has been modified for testability in the circuit. The specific method is:

Step C1, use Perl to carry out Verilog encapsulation to the EDIF circuit after the flip-flop testability modification has been completed, and retain the functional port of the original circuit and the newly added test port externally in the form of Verilog;

Step C2, connect the flip-flops according to the preset connection mode of the scan chain.

In step 4, use Perl to give the final testable circuit that conforms to Verilog syntax, and after verifying that the modification is correct, the specific method to use Perl to generate an automatic test file that conforms to Tcl syntax is:

Step D1, repackaging the Verilog file of the circuit that has completed the scan chain design generated in step 3, and using Verilog to provide the final circuit form as the final output file of the design for testability;

Step D2, according to the information of the circuit, generate a test file for testing whether the connection of the scan chain is correct;

Step D3, generating a Tcl script for a specific simulator to automatically verify the output file of the design for testability.

The invention can meet the requirement of automatic testability design for EDIF netlist level circuits.

Description of drawings

Fig. 1 is the schematic diagram of the principle of the automatic testability design system of the Perl-based EDIF netlist level circuit of the present invention.

Detailed ways

The specific embodiment one, illustrate this specific embodiment in conjunction with Fig. 1, the automatic testability design system based on the EDIF netlist level circuit of Perl, it comprises circuit source code parsing module 1, flip-flop modification module 2, scan chain design module 3, Testability circuit generation module 4, test verification module 5;

The circuit source code analysis module 1 is used to analyze the EDIF netlist-level description of the digital logic circuit, and obtain the information used by all flip-flops in the circuit;

The trigger modification module 2 includes a testability trigger generation module 21 and a trigger testability modification module 22;

The trigger modification module 2 is used to complete the testability modification of all triggers in the file described by the EDIF netlist of the circuit according to the trigger information provided by the circuit source code analysis module;

The scan chain design module 3 includes a Verilog encapsulation module 31 and a scan chain connection module 32;

Verilog encapsulation module 31 is used for according to the circuit EDIF netlist after the trigger information that the circuit source analysis module provides and the trigger modification module provide modification after the trigger, finishes the Verilog encapsulation to EDIF netlist description circuit;

The scan chain connection module 32 is used to complete the circuit scan chain design for the EDIF netlist description circuit using Verilog language according to the trigger information provided by the circuit source code analysis module and the modified circuit EDIF netlist provided by the trigger modification module ;

The testability circuit generation module 4 is used to complete the re-Verilog packaging of the circuit according to the Verilog form of the circuit generated by the scan chain design module, and obtain the final circuit after the testability design;

The test verification module 5 is used to generate test files and verify the design-for-test circuit according to the port and trigger information provided by the circuit source code analysis module and the circuit with completed testability design provided by the testability circuit generation module .

Embodiment 2. The difference between this embodiment and the automatic testability design system based on Perl-based EDIF netlist level circuits described in Embodiment 1 is that the testability circuit generation module 4 obtains the final design for testability. The latter circuit shields all the internal information of the circuit to the outside, and only provides an interface in the form of a common hardware description language.

The specific embodiment three, the automatic testing method of the EDIF netlist level circuit based on Perl, it is realized by the following steps:

Step 1. Use the circuit source code analysis module 1 to analyze the triggers used in the circuit, and use Perl to process in the EDIF environment;

Step 2: Use the trigger modification module 2 to modify the trigger used in the circuit for testability, and use Perl to process it in the EDIF environment;

Step 3. Use Perl to perform Verilog encapsulation on the EDIF circuit after the testability modification of the flip-flop, shield the EDIF details, and then design the scan chain for the flip-flop with the testability modification in the circuit;

Step 4. Use Perl to give the final testable circuit that conforms to Verilog syntax, and after verifying that the modification is correct, use Perl to generate an automatic test file that conforms to Tcl syntax, and then realize the automatic test of the EDIF netlist level circuit.

Specific embodiment four, this specific embodiment is that the automatic testing method of the described Perl-based EDIF netlist level circuit of specific embodiment three is further limited, adopts circuit source code analysis module 1 in the step 1 to carry out the flip-flop used in the circuit The specific method of analyzing and using Perl to process in the EDIF environment is as follows:

Step A1, open the EDIF netlist level circuit file;

Step A2, analyzing the use information of all components in the circuit and the calling information of the circuit from the EDIF netlist level circuit file;

Analyze the usage information of all components in the circuit and the call information of the circuit from the original EDIF file, including the name of the edif, the name of the library, the names of all the cells in the library, the names of all the views in the cell, and calls in the view The instance name of the instance, and the reference path viewRef, cellRef, libraryRef of this instance, and save these information into a file for subsequent use. The information is stored row by row in the form of "attribute (space) attribute value" in the following form:

edif edifname

library libraryname

cellc ellname

view viewname

instance instancename viewRef viewRefname cellRef cellRefname libraryReflibraryRefname

design designname cellRef cellRefname libraryRef libraryname

For the edif attribute, its value is edif;

For the library attribute, its value is library;

For the cell attribute, its value is cellname;

For the view attribute, its value is viewname;

For the instance attribute, its value is viewname; the instance attribute contains the viewRef attribute, and the attribute value is viewname; it contains the cellRef attribute, and the attribute value is cellname; it may contain the libraryRef attribute, and its value is libraryRefname;

For the design attribute, the attribute value is designname; the design attribute includes the cellRef attribute, and the attribute value is cellRefname; it includes the libraryRef attribute, and the attribute value is libraryRefname;

There is only one edif on the first line, there may be multiple libraries under the edif attribute, the level of the library is the first level, there may be multiple cells under the library, the level of the cell is the second level, and there may be multiple views under the cell, view It is the third level, there may be multiple instances under the view, the instance is the fourth level, and there is only one design, which is located in the last row.

Attribute names other than edif and design appear in order according to the level. If there is a gap, the lower level will appear first.

Step A3, from the file of usage information of all components of the circuit obtained in step A2, analyze the specific instance calling situation, and save it in a calling format, and save it in the form of a file, the format of which is as follows:

{lib.cell.view}{inLib.inCell.inView}[instName1instName2instName3…]

The view of the cell in the lib library is used in the inView of inLib's inCell, and the names used are instName1, instName2, instName3, and so on.

Step A4, from the call information file output in step A3, find the call information related to flip-flops, and analyze the flip-flops used in the circuit.

Specific embodiment five, this specific embodiment is that the automatic test method of the described Perl-based EDIF netlist level circuit of specific embodiment three is further limited, adopts trigger modification module (2) in the step 2 to the trigger used in the circuit The specific method of modifying the testability of the device and using Perl in the EDIF environment is as follows:

Step B1. Obtain the trigger type from all the trigger information analyzed in step 1;

Step B2, generating a testability EDIF component library, which contains testability triggers corresponding to all types of triggers analyzed in step B1;

Step B3, inserting the testability library obtained in step B2 into the EDIF component of the original circuit, the insertion position is after the library related to the flip-flop declaration of the original circuit;

Step B4. According to all trigger information analyzed in step 1, trigger modification information is generated. The format of the modification information is as follows:

{cell}{cellchanges}[portchanges]

The reference path of the trigger cell needs to be changed to the reference path of cellchanges, and the test port to be added is in portchanges.

Step B5. According to the modification information of the generated trigger obtained in step B4, modify the EDIF file in step B3 one by one, modify the reference path of the trigger, add the statement of the test port and the node connection of the test port, and obtain the EDIF file after the modification of the trigger .

Specific embodiment six, this specific embodiment is that the automatic testing method of the described Perl-based EDIF netlist level circuit of specific embodiment three is further limited, uses Perl in the step 3 to the EDIF after completing the flip-flop testability modification The circuit is packaged in Verilog, the details of EDIF are shielded, and then the specific method of designing the scan chain for the flip-flop for testability modification in the circuit is:

Step C1, use Perl to carry out Verilog encapsulation to the EDIF circuit after the flip-flop testability modification has been completed, and retain the functional port of the original circuit and the newly added test port externally in the form of Verilog;

Step C2, connect the flip-flops according to the preset connection mode of the scan chain.

The specific embodiment seven, this specific embodiment is that the automatic test method of the described Perl-based EDIF netlist level circuit of the specific embodiment three is further limited, and in the step 4, use Perl to provide final testability and conform to Verilog Syntax circuit, and after verifying that the modification is correct, the specific method of using Perl to generate an automatic test file that conforms to Tcl syntax is:

Step D1, repackaging the Verilog file of the circuit that has completed the scan chain design generated in step 3, and using Verilog to provide the final circuit form as the final output file of the design for testability;

Step D2, according to the information of the circuit, generate a test file for testing whether the connection of the scan chain is correct;

Step D3, generating a Tcl script for a specific simulator to automatically verify the output file of the design for testability.

The specific embodiment seven, the automatic test method of the EDIF netlist level circuit based on Perl of the present invention is illustrated below with specific parameters:

The following is an example of an EDIF netlist-level circuit, and there is no actual function:

Among them: the EDIF netlist of A1 has three libraries, LIB1, LIB2, and LIB3, and a design A1 is designed with these three libraries. There is a cell named CELL1 in LIB1, and a view named PRIM in CELL1. There is a cell named FD in LIB2, and FD has a view named PRIM, and this FD is a trigger. There is a cell named CELL2 in LIB3. This cell has a view named netlist. This cell contains two instances, one of which is a reference to the PRIM view of CELL1 in LIB1, and the other is FD in LIB2. The call of the PRIM view. The above is the description of the circuit elements and structure used in this example.

Now design for testability of this circuit:

{cell}{cellchanges}[portchanges]

Step (1): Use Perl to analyze the use and structure of components on the EDIF netlist of this circuit.

Step1: Read in this EDIF file

Step2: Use the regular expression provided by Perl to search by row and extract the required information. First, we will extract the name A1 of the edif netlist, then we will extract the LIB1 of the library, and the view of CELL1 and PRIM of LIB1, and so on. When extracting instance information, for example, for INST1, you will get its reference path, the value PRIM of viewRef, the value CELL1 of cellRef, and the value LIB1 of libraryRef. If libraryRef defaults, it means the same library.

The following information describing the circuit components and structure will be obtained:

edif A1

library LIB1

cell CELL1

view PRIM

library LIB2

cell FD

view PRIM

library LIB3

cell CELL2

viewnetlist

instance INST1viewRef PRIM cellRef CELL1libraryRef LIB1

instance INST2viewRef PRIM cellRef FD libraryRef LIB2

design A1cellRef CELL2libraryRef LIB3

Step3: Analyze the information obtained in the first step to obtain mutual calling information, as follows

{LIB1.CELL1.PRIM}{LIB3.CELL2.netlist}[INST1]

{LIB2.FD.PRIM}{LIB3.CELL2.netlist}[INST2]

Step4: Find the call information of the trigger FD in this example

{LIB2.FD.PRIM}{LIB3.CELL2.netlist}[INST2]

Step (2):

Step1: Obtain the trigger type from all the trigger information used in step (1);

Step2: Generate a testability EDIF component library, which contains testability triggers corresponding to all types of triggers analyzed in Step1;

Here, for the FD type trigger, use edif to implement a testability trigger with a multiplexer structure, named FD_T, and the extra ports are port S and port T, and put them as a cell into the testable trigger of your own design library, such as the library DFTFF.

Step3: Insert the testability library of Step2 into the EDIF component of the original circuit, and the insertion position is behind the library of the trigger declaration of the original circuit

Here, put the above-designed testability library behind the code of LIB2 and in front of the line where LIB3 is located.

Step4: Obtain all trigger information used according to step (1) in claim 2, generate the modification information of trigger, the modification information here is:

{LIB3.FD.PRIM}{DFTFF.FD_T.netlist}[S_INST2.INST2T_INST2.INST2Q_INST2.INST2]

Step5: According to the modification information of Step4, modify the EDIF file of Step3 one by one, modify the reference path of the trigger, add the statement of the test port and the node connection of the test port, and obtain the EDIF file after the modification of the trigger.

Step (3): After step (2) is completed, use Perl to perform Verilog encapsulation on the EDIF circuit that has been modified for testability of the flip-flop, shield the details of the EDIF, and then design the scan chain for the flip-flop that has been modified for testability in the circuit , using Perl to assist the designer to complete in the Verilog environment, the algorithm is as follows:

Step1: the generated EDIF of the step (2) in claim 2 is carried out Verilog encapsulation, externally retains the functional port of the original circuit and the newly added test port in the form of Verilog;

Step2: The designer gives the connection method of the scan chain;

Step3: Connect the trigger according to the scan chain connection method given by the designer;

Step (4): Generate the final testability circuit file, use Perl to give the final circuit with testability and conform to Verilog syntax, and verify whether the modification result is correct, use Perl to generate an automatic test file conforming to Tcl syntax, The algorithm is as follows:

Step1: Encapsulate the Verilog file of the circuit of the completed scan chain design generated by step (3) in claim 2, and use Verilog to provide the final circuit form as the output file of the final design for testability .

Step2: According to the information of the circuit, a test file is generated to test whether the connection of the scan chain is correct.

Step3: Generate a Tcl script for a specific simulator to automatically verify the output results of the testability design.

Features of the present invention:

1. The algorithm used and the format of the stored data when analyzing the calling level of the circuit described by the EDIF netlist;

2. The analysis algorithm and stored data format of the flip-flop used in the circuit described by the EDIF netlist, the design of the testability library (library) and the insertion of the library, and the testability design of different triggers structure;

3. Analyze the algorithm and storage format of triggers in the circuit being called and instantiated by different modules;

4. An algorithm for testability modification of all flip-flops used in the circuit described in the EDIF netlist;

5. Use the Verilog language to encapsulate the circuit described in the modified EDIF netlist to make it a circuit that conforms to the Verilog expression;

6. In the Verilog environment, design the scan chain of the circuit according to the Verilog syntax;

7. Automatically generate test files for testing the modified circuit;

8. Automatically generate circuit test files in Tcl form, automatically add test vectors and obtain corresponding test responses.

Claims (4)

1. The automatic testability design method of the Perl-based EDIF netlist-level circuit automatic testability design system, which is realized based on the Perl-based EDIF netlist-level circuit automatic testability design system, the system includes circuit source code Analysis module (1), trigger modification module (2), scan chain design module (3), testability circuit generation module (4), test verification module (5); The circuit source code analysis module (1) is used to analyze the EDIF netlist-level description of the digital logic circuit, and obtain the information used by all flip-flops in the circuit; The trigger modification module (2) includes a testability trigger generation module (21) and a trigger testability modification module (22); The trigger modification module (2) is used to complete the testability modification to all triggers in the file described by the EDIF netlist of the circuit according to the trigger information provided by the circuit source code analysis module; The scan chain design module (3) includes a Verilog encapsulation module (31) and a scan chain connection module (32); Verilog encapsulation module (31) is used for the circuit EDIF netlist after the trigger information that provides according to the trigger information that circuit source analysis module provides and the trigger modification module provides modification, finishes the Verilog encapsulation to EDIF netlist description circuit; The scan chain connection module (32) is used to complete the circuit EDIF netlist modified by the trigger information provided by the circuit source code analysis module and the trigger modified by the trigger modification module, and complete the scanning of the circuit described by the EDIF netlist in Verilog language chain design; The testability circuit generating module (4) is used to complete the Verilog packaging of the circuit again according to the circuit in Verilog form generated by the scan chain design module, and obtain the circuit after the final testability design; The test verification module (5) is used to generate test files according to the port and trigger information provided by the circuit source code analysis module and the circuit with completed testability design provided by the testability circuit generation module, and to test the circuit after the design for testability authenticating; The automatic testability design method of the automatic testability design system based on Perl's EDIF netlist level circuit, it is realized by the following steps: Step 1, using the circuit source code analysis module (1) to analyze the triggers used in the circuit, and use Perl to process in the EDIF environment; Step 2, using the trigger modification module (2) to modify the testability of the trigger used in the circuit, and use Perl to process it in the EDIF environment; Step 3. Use Perl to perform Verilog encapsulation on the EDIF circuit after the testability modification of the flip-flop, shield the EDIF details, and then design the scan chain for the flip-flop with the testability modification in the circuit; Step 4. Use Perl to give the final testable circuit that conforms to Verilog syntax, and after verifying that the modification is correct, use Perl to generate an automatic test file that conforms to Tcl syntax, and then realize the automatic test of EDIF netlist-level circuits; It is characterized in that: use Perl in step 4 to give the final circuit with measurability and conform to Verilog grammar, and after verifying that the modification is correct, the specific method of using Perl to generate an automatic test file conforming to Tcl grammar is: Step D1, repackaging the Verilog file of the circuit that has completed the scan chain design generated in step 3, and using Verilog to provide the final circuit form as the final output file of the design for testability; Step D2, according to the information of the circuit, generate a test file for testing whether the connection of the scan chain is correct; Step D3, generating a Tcl script for a specific simulator to automatically verify the output file of the design for testability. 2. the automatic testability design method of the automatic testability design system based on the EDIF netlist level circuit of Perl according to claim 1, it is characterized in that the automatic testability design system based on the EDIF netlist level circuit of Perl Among them, the testability circuit generation module (4) obtains the final circuit design for testability and shields all internal information of the circuit to the outside, and only provides an interface conforming to the form of a common hardware description language. 3. the automatic testability design method of the automatic testability design system of the EDIF netlist level circuit based on Perl according to claim 1, it is characterized in that adopting circuit source code analysis module (1) to use in the circuit in step one The specific method for analyzing triggers and using Perl to process them in the EDIF environment is as follows: Step A1, open the EDIF netlist level circuit file; Step A2, analyzing the use information of all components in the circuit and the calling information of the circuit from the EDIF netlist level circuit file; Step A3, from the file of the use information of all components of the circuit obtained in step A2, analyze the specific instance call situation, and save it in a call format, and save it in the form of a file; Step A4, from the call information file output in step A3, find the call information related to flip-flops, and analyze the flip-flops used in the circuit. 4. the automatic testability design method of the automatic testability design system of the EDIF netlist level circuit based on Perl according to claim 1, it is characterized in that after using Perl in the step 3 to complete trigger testability modification The EDIF circuit is encapsulated in Verilog, the details of the EDIF are shielded, and then the specific method for designing the scan chain of the flip-flop for testability transformation in the circuit is: Step C1, use Perl to carry out Verilog encapsulation to the EDIF circuit after the flip-flop testability modification has been completed, and retain the functional port of the original circuit and the newly added test port externally in the form of Verilog; Step C2, connect the flip-flops according to the preset connection mode of the scan chain.