CN103294153B - Information processor, image processing system and information processing method - Google Patents

Abstract

The present invention relates to an information processing device, an image forming device, and an information processing method. An information processing apparatus includes: an execution unit that executes a program; a main storage unit including a readable and writable first nonvolatile memory capable of retaining stored data even when power is not supplied. and the main storage unit is provided with a first storage area storing a program executed by the execution unit and a second storage area storing data generated by executing the program by the execution unit; a connection unit connecting the execution unit and the main storage unit; and a condition a storage unit including a readable and writable second nonvolatile memory capable of retaining stored information even when there is no power supply, and a condition storage unit that stores the information set by the connection unit with Conditions for sending and receiving programs and data between execution units and main storage units.

Description

Information processing device, image forming device, and information processing method

technical field

The present invention relates to an information processing device, an image forming device, and an information processing method.

Background technique

Japanese Patent Laid-Open No. 2004-78043 (Patent Document 1) discloses a technique in which a nonvolatile memory is provided in an I/O control unit of an image forming apparatus, and when the image forming apparatus is powered off, the The values of the register set holding the data for the functional blocks of the I/O control unit are copied to the non-volatile memory.

Contents of the invention

An object of the present invention is to provide a technique capable of executing startup processing from a nonvolatile memory when using the nonvolatile memory as a memory storing "data of a program and work data generated by executing the program".

According to the first aspect of the present invention, there is provided an information processing device, the information processing device includes: an execution unit, the execution unit executes the program; a main storage unit, the main storage unit includes a readable and writable first non-volatile memory, the first nonvolatile memory capable of retaining stored information even when power is not supplied, and the main storage unit is provided with a first storage area storing the program executed by the execution unit and a storage The execution unit executes the second storage area of the data generated by the program; the connection unit connects the execution unit and the main storage unit; and the condition storage unit includes a readable and writable first storage unit. Two non-volatile memories, the second non-volatile memory can hold the stored information even when there is no power supply, and the condition storage unit stores the conditions set by the connection unit between the execution unit and the Setting conditions for sending and receiving the program and the data between the main storage unit.

According to a second aspect of the present invention, the information processing apparatus according to the first aspect may further include a setting unit configured to, before the connection unit connects the execution unit and the main storage unit, set communication conditions for communication between the connection unit and the main storage unit as the setting conditions, wherein the condition storage unit may store the communication conditions set by the setting unit as the setting conditions.

According to a third aspect of the present invention, in the information processing device according to the first or second aspect, the main storage unit may further include a readable and writable volatile memory, and the volatile memory The stored information cannot be retained upon provisioning, and the volatile memory may be provided with a second storage area.

According to a fourth aspect of the present invention, in the information processing device according to any one of the first to third aspects, the first nonvolatile memory of the main storage unit may be MRAM, FeRAM, Any of PRAM and ReRAM.

According to a fifth aspect of the present invention, there is provided an image forming apparatus including: an image forming unit that forms an image on a recording material; and a control unit that controls the image forming unit operation, wherein the control unit includes: an execution unit that executes a program for controlling the image forming unit; a main storage unit that includes a readable and writable first nonvolatile memory, the The first nonvolatile memory can retain the stored information even when there is no power supply, and the main storage unit is provided with a first storage area storing the program executed by the executing unit and storing the executed program. A second storage area for the data generated by the unit executing the program; a connection unit connecting the execution unit and the main storage unit; and a condition storage unit including a readable and writable second non- a volatile memory, the second nonvolatile memory capable of retaining stored information even when power is not supplied, and the condition storage unit stores the conditions set by the connection unit between the execution unit and the Conditions for sending and receiving the program and the data between the main storage unit.

According to a sixth aspect of the present invention, there is provided an information processing method, the information processing method comprising the following steps: executing a program; setting a first storage area for storing the program in a first readable and writable non-volatile memory and a second storage area that stores data generated by executing the program, the first nonvolatile memory is capable of retaining stored information even when there is no power supply; connecting a computer to the first nonvolatile memory volatile memory; and storing and setting the setting conditions for sending and receiving the program and the data with the first non-volatile memory in the readable and writable second non-volatile memory, the second non-volatile memory Stored information can be maintained even when there is no power supply.

According to a seventh aspect of the present invention, the information processing method according to the sixth aspect may further include: before connecting to the first nonvolatile memory, setting a device for communicating with the first nonvolatile memory communication conditions as the setting conditions, wherein in the step of storing the setting conditions, the communication conditions may be stored in the second nonvolatile memory as the setting conditions.

According to the first aspect of the present invention, in the case of using a nonvolatile memory as a memory storing "data of a program and work data generated by executing the program", compared to the case of not using this structure, from The non-volatile memory performs startup processing.

According to the second aspect of the present invention, data can be transmitted and received under more suitable conditions than the case where this structure is not used.

According to the third aspect of the present invention, it is possible to increase the storage capacity of the second storage area while preventing an increase in cost, compared to the case where this structure is not used.

According to the fourth aspect of the present invention, data can be transmitted and received from the nonvolatile memory at a higher speed than in the case of using EEPROM or flash memory as the nonvolatile memory.

According to the fifth aspect of the present invention, compared with the case where this structure is not used, in the case of using a nonvolatile memory as a memory storing "data of a program and work data generated by executing the program", it is possible from The nonvolatile memory performs startup processing.

According to the sixth aspect of the present invention, compared with the case where this structure is not used, in the case of using a nonvolatile memory as a memory for storing "data of the program and work data generated by executing the program", the nonvolatile The volatile memory performs boot processing.

According to the seventh aspect of the present invention, it is possible to increase the storage capacity of the second storage area while preventing an increase in cost, compared to the case where this structure is not used.

Description of drawings

Exemplary embodiments of the present invention are described in detail based on the following drawings, in which:

FIG. 1 is a diagram illustrating an example of a configuration of an image forming system according to an exemplary embodiment;

2 is a block diagram illustrating an example of an internal configuration of a control unit provided in the image forming apparatus;

3 is a block diagram illustrating an example of an internal structure of a CPU and an ASIC provided in a control unit;

4 is a block diagram illustrating an example of an internal structure of a CPU-RAM controller provided in a CPU;

5A and 5B are block diagrams illustrating an example of the structure of a CPU-RAM module provided in the operation control unit;

6 is a diagram illustrating an example of the structure of a memory allocation map of a main memory provided in an operation control unit;

FIG. 7 is a flowchart illustrating a boot selection processing procedure involving HW reset processing;

FIG. 8 is a flow chart illustrating a startup processing procedure during ROM boot; and

FIG. 9 is a flowchart illustrating a start-up processing procedure during MRAM boot.

detailed description

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating an example of the structure of an image forming system according to this exemplary embodiment.

The image forming system includes: an image forming apparatus 1 operating as a multifunction machine having a scanning function, a printing function, a copying function, and a facsimile function; a network 2 connected to the image forming apparatus 1; a terminal connected to the network 2 a device 3 ; a facsimile device 4 connected to the network 2 ; and a server device 5 connected to the network 2 .

The network 2 is, for example, an Internet line or a telephone line. A terminal device 3 such as a PC (Personal Computer) instructs the image forming device 1 to execute, for example, image forming processing via the network 2 . The facsimile device 4 transmits and receives facsimiles to and from the image forming device 1 via the network 2 . The server device 5 transmits and receives data (including programs) from the image forming device 1 via the network 2 .

Furthermore, the image forming apparatus 1 includes: an image reading unit 10 that reads an image recorded on a recording medium such as paper; and an image forming unit 20 that forms an image on a recording medium such as paper. Image; User Interface (UI) 30 that receives instructions from the user related to power ON/OFF operations and operations using the scan function, print function, copy function, and facsimile function, and displays a message to the user The transceiver unit 40, the transceiver unit 40 sends data to the terminal device 3, the facsimile device 4, and the server device 5 via the network 2 and receives data from the terminal device 3, the facsimile device 4, and the server device 5; and the control unit 50, the The control unit 50 controls operations of the image reading unit 10 , the image forming unit 20 , the UI 30 , and the transceiving unit 40 . In the image forming apparatus 1, the scanning function is implemented by the image reading unit 10, the printing function is implemented by the image forming unit 20, the copying function is implemented by the image reading unit 10 and the image forming unit 20, and the facsimile function is implemented by the image reading unit 10 , the image forming unit 20, and the transceiver unit 40 are implemented. In addition, for example, the transceiving unit 40 may be separately provided for an Internet line and a telephone line.

FIG. 2 is a block diagram illustrating an example of an internal configuration of a control unit 50 provided in the image forming apparatus 1 illustrated in FIG. 1 .

The control unit 50 according to this exemplary embodiment includes: an operation control unit 51 which controls the operations of the respective units of the image forming apparatus 1; image processing related to the image forming unit 20 ; and a PCIe (PCI Express) bus 53 connecting the operation control unit 51 and the image processing unit 52 .

Among them, the operation control unit 51 includes: a CPU (Central Processing Unit) 511 that performs various operations to control each unit of the image forming apparatus 1; a CPU-MRAM module 61 and a CPU-DRAM module 62 that and a CPU-DRAM module 62 connected to the CPU 511 via a CPU-RAM bus 513 ; and a CPU-ROM module 63 connected to the CPU 511 via a CPU-ROM bus 514 . In the following description, the CPU-MRAM module 61 , the CPU-DRAM module 62 , and the CPU-ROM module 63 connected to the CPU 511 are referred to as a main memory 512 . The operation control unit 51 is configured such that the CPU 511 directly reads and writes data from the main memory 512 .

The CPU-MRAM module 61 includes MRAM (Magnetoresistive RAM) as a memory device and functions as a nonvolatile memory that can hold stored information even when power is not supplied. The CPU-DRAM module 62 includes DRAM (Dynamic RAM) as a memory device and functions as a volatile memory that cannot hold stored information when power is not supplied. In this exemplary embodiment, the CPU-MRAM module 61 and the CPU-DRAM module 62 read and write data according to a common clock frequency (memory clock) set to the CPU-RAM bus 513 . Therefore, the CPU-MRAM module 61 can have the same read and write functions as the CPU-DRAM module 62 . Compared with nonvolatile memory such as UV-EPROM (Ultraviolet Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), or flash memory, the CPU-MRAM module 61 can read and write data at high speed.

The CPU-DRAM module 62 according to this exemplary embodiment is, for example, DDR2-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory of Second Generation).

Unlike this, the CPU-ROM module 63 is a so-called mask ROM, various PROMs (programmable ROM: for example, OTP ROM (one-time programmable ROM), UV-EPROM (ultraviolet erasable programmable ROM), and EEPROM ( Electrically Erasable Programmable ROM)) or Flash memory. In this example, a flash memory is used as the CPU-ROM module 63 .

The image processing unit 52 includes: an ASIC (Application Specific Integrated Circuit) 521 that executes various calculations to process image data input from the image reading unit 10 and image data to be output to the image forming unit 20 , and connected via an ASIC-RAM bus 523 to the main memory 522 of the ASIC521. The main memory 522 provided in the image processing unit 52 includes an ASIC-DRAM module 91 having the same structure as the CPU-DRAM module 62 .

The PCIe bus 53 connecting the operation control unit 51 and the image processing unit 52 performs sending and receiving based on the PCI Express standard to connect the CPU 511 provided in the operation control unit 51 and the ASIC 521 provided in the image processing unit 52 in the control unit 50. In this example, the ASIC 521 executes various image processing based on instructions received from the CPU 511 via the PCIe bus 53 .

FIG. 3 is a block diagram illustrating an example of the internal configuration of the CPU 511 and the ASIC 521 provided in the control unit 50 shown in FIG. 2 . In the following description, among the main memory 512 connected to the CPU 511 , the CPU-MRAM module 61 and the CPU-DRAM module 62 connected to the CPU-RAM bus 513 are referred to as a CPU-RAM module 60 (an example of a main memory unit).

First, the internal structure of CPU511 is described.

The CPU 511 includes: a CPU core 71 that is an example of an execution unit that performs various calculations based on a program; a CPU-RAM controller 72 that controls the connection between the CPU core 71 and the CPU-RAM module 60 and the CPU-ROM controller 73, the CPU-ROM controller 73 controls the data transmission and reception between the CPU core 71 and the CPU-ROM module 63. In addition, the CPU 511 includes: a watchdog timer (WDT, watchdog timer) 74, the watchdog timer (WDT) 74 is used to detect errors when the CPU core 71 executes the program; a CPU/PCIe interface 75, the CPU/PCIe interface 75 controls Data transmission and reception between the CPU core 71 and the outside (such as ^ASIC521 ) ^; send and receive. CPU511 further comprises CPU internal bus 77, and this CPU internal bus 77 connects CPU core 71, CPU-RAM controller 72, CPU-ROM controller 73, check timer 74, CPU/PCIe interface 75 and CPU-1 in CPU511 ² C controller 76 .

The CPU-RAM bus 513 according to this exemplary embodiment includes a memory bus 513 a connected to the CPU-RAM controller 72 and an I ² C bus 513 b connected to the CPU-I ² C controller 76 . The data transfer speed via the memory bus 513a is higher than the data transfer speed via the I ² C bus 513b. The data transfer speed of the memory bus 513 a via the CPU-RAM bus 513 is higher than the data transfer speed via the CPU-ROM bus 514 .

Next, the internal structure of ASIC521 is described.

ASIC521 comprises: ASIC core 81, this ASIC core 81 performs various calculations; ASIC-RAM controller 82, this ASIC-RAM controller 82 controls the data transmission and reception between ASIC core 81 and ASIC-DRAM module 91; ASIC/PCIe Interface 85, the ASIC/PCIe interface 85 controls the data transmission and reception between the ASIC core 81 and the outside (for example, CPU511); and an ASIC-I ² C controller 86, the ASIC-I ² C controller 86 controls the ASIC core 81 Data transmission and reception with the ASIC-DRAM module 91 . In addition, the ASIC 521 includes an ASIC internal bus 87 that connects the ASIC core 81 , the ASIC-RAM controller 82 , the ASIC/PCIe interface 85 , and the ASIC-I ² C controller 86 in the ASIC 521 .

The ASIC-RAM bus 523 according to this exemplary embodiment includes a memory bus 523 a connected to the ASIC-RAM controller 82 and an I ² C bus 513 b connected to the ASIC-I ² C controller 86 . The data transfer speed via the memory bus 523a is higher than the data transfer speed via the I ² C bus 523b.

FIG. 4 is a block diagram illustrating an internal configuration of the CPU-RAM controller 72 provided in the CPU 511 shown in FIG. 3 .

The CPU-RAM controller 72 is an example of a connection unit, and the CPU-RAM controller 72 includes: an internal bus interface 721 that controls data transmission and reception from the CPU internal bus 77; and a memory bus interface 722 that 722 is connected to the internal bus interface 721 and controls data transmission and reception from the memory bus 513a. In addition, the CPU-RAM controller 72 includes a training circuit 723 that executes a method for optimizing data transmission and reception when the CPU-RAM controller 72 and the CPU-RAM module 60 (see FIG. 3 ) are connected to each other via the memory bus 513a. conditional training sequence; and a nonvolatile setting register 724 storing various setting values obtained based on the result of the training sequence of the training circuit 723 and set for the memory bus interface 722 (hereinafter , called the register setting value).

The nonvolatile setting register 724 as an example of a condition storage unit includes the same MRAM as the CPU-MRAM module 61 (see FIG. 3 ), and functions as a nonvolatile memory capable of retaining stored information even when power is not supplied. function.

In this exemplary embodiment, register setting values are required when data is transmitted between the CPU-RAM controller 72 and the CPU-RAM module 60 (CPU-MRAM module 61 and CPU-DRAM module 62 ) via the memory bus 513 a. Viewed from the opposite point of view, it is difficult to transmit data between the CPU-RAM controller 72 and the CPU-RAM module 60 via the memory bus 513a until register setting values are determined.

5A and 5B are block diagrams illustrating an example of the structure of the CPU-RAM module 60 provided in the operation control unit 51 shown in FIG. 2 . Specifically, FIG. 5A is a block diagram illustrating an example of the internal structure of the CPU-MRAM module 61 connected to the CPU 511, and FIG. 5B is a block diagram illustrating an example of the internal structure of the CPU-DRAM module 62 connected to the CPU 511.

First, the internal structure of the CPU-MRAM module 61 is described with reference to FIG. 5A.

CPU-MRAM module 61 comprises: MRAM general storage unit 611, this MRAM general storage unit 611 stores the program that CPU511 executes or the working data that produces when executing program; SPD (Serial Presence Detect: Serial Presence Detect) of characteristic information (for example, the maximum available clock frequency or signal timing) of the module 61; and an MRAM mode storage unit 613 that stores the operation of the CPU-MRAM module 61 model. In addition, the CPU-MRAM module 61 includes: an MRAM internal controller 614, which performs data communication with the CPU-RAM controller 72 (see FIG. ³ ) via the memory bus 513a, and performs communication with the CPU-RAM controller 72 (see FIG. CPU-I ² C controller 76 communicates data, and controls data reading and writing with MRAM general storage unit 611 , MRAMSPD storage unit 612 , and MRAM mode storage unit 613 .

The MRAM internal controller 614 controls the data transmission and reception between the memory bus 513a and the MRAM general-purpose storage unit 611, and controls between the I ² C bus 513b and the MRAM SPD storage unit 612, and between the I ² C bus 513b and the MRAM mode storage unit 613 data sending and receiving.

In this example, the MRAM general storage unit 611 , the MRAM SPD storage unit 612 , and the MRAM pattern storage unit 613 are MRAMs, respectively, but are not limited thereto. For example, considering the difference between the transfer speeds of the memory bus 513a and the I ² C bus 513b, the MRAM general storage unit 611 may be MRAM, while the MRAM SPD storage unit 612 and the MRAM mode storage unit 613 may be EEPROM.

Next, the internal structure of the CPU-DRAM module 62 will be described with reference to FIG. 5B.

CPU-DRAM module 62 comprises: DRAM universal storage unit 621, and this DRAM general storage unit 621 stores for example the work data that CPU511 produces when executing program; DRAMSPD storage unit 622, and this DRAMSPD storage unit 622 stores the SPD of CPU-DRAM module 62; And A DRAM mode storage unit 623 that stores the operation mode of the CPU-DRAM module 62 . In addition, the CPU-DRAM module 62 includes: a DRAM internal controller 624, which performs data communication with the CPU-RAM controller 72 (see FIG. ³ ) via the memory bus 513a, and performs communication with the CPU-RAM controller 72 (see FIG. CPU-I ² C controller 76 communicates data, and controls data reading and writing with DRAM general storage unit 621 , DRAMSPD storage unit 622 , and DRAM mode storage unit 623 .

The DRAM internal controller 624 controls the transmission and reception of data between the memory bus 513a and the DRAM general storage unit 621, and controls between the I ² C bus 513b and the DRAM SPD storage unit 622 and between the I ² C bus 513b and the DRAM mode storage unit 623 data sending and receiving.

In this example, the DRAM general storage unit 621 is a DRAM, while the DRAM SPD storage unit 622 and the DRAM mode storage unit 623 are, for example, EEPROMs, respectively.

The ASIC-DRAM module 91 (see FIG. 3 ) provided in the image processing unit 52 has the same structure as the CPU-DRAM module 62 .

6 is a diagram illustrating an example of the structure of a memory allocation map in the main memory 512 (CPU-MRAM module 61, CPU-DRAM module 62, and CPU-ROM module 63) of the operation control unit 51 shown in FIG. 2 . The CPU 511 provided in the operation control unit 51 performs data reading and writing with the main memory 512 based on the storage map.

In the memory allocation diagram shown in FIG. 6, the storage area A0 which is the entire area of the main memory 512 includes a ROM area A1 basically used as a ROM and a RAM area A2 basically used as a RAM. In this exemplary embodiment, the ROM area A1 is provided across the CPU-ROM module 63 and the CPU-MRAM module 61 , and the RAM area A2 is provided across the CPU-MRAM module 61 and the CPU-DRAM module 62 . Among them, the ROM area A1 includes: a first ROM area A11 that is set in the CPU-ROM module 63 and basically does not allow rewriting of data, and a second ROM area A12 that is set in the CPU-MRAM module 61 and basically allows rewriting of data . The RAM area A2 includes: a first RAM area A21 provided in the CPU-MRAM module 61 and a second RAM area A22 provided in the CPU-DRAM module 62 .

The first ROM area A11 forming the ROM area A1 includes a first reset vector storage area A111 and a compressed program storage area A112. Among them, the first reset vector storage area A111 stores a first IPL (Initial Program Loader: Initial Program Loader), which is a program executed by the CPU 511 (see FIG. 2 ) of the operation control unit 51 when the image forming apparatus 1 is started. The compressed program storage area A112 stores compressed program files obtained by compressing data of programs for controlling the image forming apparatus 1 .

The second ROM area A12 as an example of a first storage area forming the ROM area A1 together with the first ROM area A11 includes a second reset vector storage area A121, a decompressed program storage area A122, and a setting information storage area A123. Among them, the second reset vector storage area A121 stores a second IPL, which is a program executed by the CPU 511 (see FIG. 2 ) of the operation control unit 51 when the image forming apparatus 1 is started. The decompressed program storage area A122 stores decompressed program files obtained by decompressing the compressed program files read from the compressed program storage area A112 of the first ROM area A11 using the CPU 511 . The setting information storage area A123 stores data having the same content as the register setting value stored in the nonvolatile setting register 724 (see FIG. 4 ) of the CPU-RAM controller 72 as setting information.

In this example, the storage capacity of the decompressed program storage area A122 is larger than the storage capacity of the compressed program storage area A112. This is because the file size increases when the compressed file is decompressed.

In this exemplary embodiment, the first IPL is stored in the first reset vector storage area A111 provided in the CPU-ROM module 63, and the second IPL is stored in the second reset vector storage area A111 provided in the CPU-MRAM module 61. in storage area A121. Therefore, in this exemplary embodiment, after the CPU 511 executes a hardware reset (HW reset) to start up the image forming apparatus 1 , one of the first IPL and the second IPL is selectively executed, which will be described in detail later.

In this example, the first RAM area A21 and the second RAM area A22 forming the RAM area A2 as an example of the second storage area are used as a work area A200 that temporarily stores data generated when the CPU 511 executes a program or the CPU 511 Data of instructions output to each component of the image forming apparatus 1 when processing is executed. Thus, in this exemplary embodiment, the RAM area A2 (work area A200 ) is formed by two memories (part of the CPU-MRAM module 61 and all of the CPU-DRAM module 62 ) with different storage methods. The CPU 511 regards the first RAM area A21 provided in the CPU-MRAM module 61 and the second RAM area A22 provided in the CPU-DRAM module 62 as the RAM area A2.

FIG. 7 is a flowchart illustrating a process of starting the image forming apparatus 1 shown in FIG. 1 . For example, when the UI 30 is operated to turn on the image forming apparatus 1 and an HW reset instruction is input to the control unit 50 (specifically, the CPU 511 operating the control unit 51 ), and to the control unit for any reason after the image forming apparatus 1 is turned on. 50 When the HW reset command is input, start processing is executed. In this exemplary embodiment, for example, when an error occurs in the control unit 50 after the image forming apparatus 1 is turned on, and when the image forming apparatus 1 is set to the energy-saving mode (sleep mode) and then reports to the control unit via the UI 30 When an instruction to return the operation mode to the normal mode is input to the control unit 50 , an HW reset instruction is input to the control unit 50 . When the image forming apparatus 1 is set in the energy saving mode, the power supply to the image reading unit 10 or the image forming unit 20 is stopped, and the power supply to the components (circuits) of the control unit 50 is also stopped.

When the startup process starts, HW reset is performed on the CPU 511 provided in the operation control unit 51 of the control unit 50 , and then the HW reset is released (step S11 ). When the HW reset is released, it is determined whether the current startup process is the first startup process (initial startup) after the image forming apparatus 1 is installed (step S12 ).

When the judgment result in step S12 is "No", in other words, when the current start-up process is the second or subsequent start-up process, it is judged whether the current start-up process is based on the check timer 74 ( See Figure 3) for restart processing (step S13) of watchdog timer reset (WDT reset).

When the judgment result in step S13 is "No", the CPU 511 performs booting based on the second IPL read from the second reset vector storage area A121 of the second ROM area A12 provided in the CPU-MRAM module 61 (hereinafter , referred to as "MRAM booting") (step S14).

On the other hand, when the judgment result in step S12 is "Yes" and the judgment result in step S13 is also "Yes", the CPU 511 based on the first reset from the first ROM area A11 provided in the CPU-ROM module 63 The first IPL read by the vector storage area A111 executes booting (hereinafter, referred to as “ROM booting”) (step S15 ).

In this way, in this exemplary embodiment, after the HW reset for the CPU 511 is released, a boot selection process of changing the IPL used in the startup process is performed according to the state before the HW reset.

FIG. 8 is a flowchart illustrating a start-up processing procedure during ROM booting in step S15.

During ROM booting, first, the CPU core 71 reads the first IPL from the first reset vector storage area A111 of the first ROM area A11 provided in the CPU-ROM module 63 via the CPU-ROM controller 73, and executes the first IPL (step S101). Subsequently, an interrupt vector is set (step S102 ) and the memory map shown in FIG. 6 is set to the main memory 512 (step S103 ).

Subsequently, the CPU-ROM controller 73 is initialized (step S104 ) and the CPU-I ² C controller 76 is initialized (step S105 ). Subsequently, each SPD is obtained from the MRAMSPD storage unit 612 provided in the CPU-MRAM module 61 in the CPU-RAM module 60 and the DRAMSPD storage unit 622 provided in the CPU-DRAM module 62 via the initialized CPU-I ² C controller 76 (step S106).

Subsequently, the CPU-RAM controller 72 is initialized (step S107 ). In step S107, the training circuit 723 executes a training sequence for optimizing the communication conditions of the CPU-RAM controller 72 and the CPU-RAM module 60 via the memory bus 513a based on the SPD obtained in step S106, and obtains optimized setting values . Subsequently, the result of the training sequence is written into the non-volatile setting register 724 as a register setting value, and the result of the training sequence is also stored in the CPU-MRAM module 61 of the CPU-RAM module 60 via the memory bus 513a. The setting information is stored in the setting information storage area A123 of the ROM area A12 as setting information.

Subsequently, the MRAM mode storage unit 613 provided in the CPU-MRAM module 61 and the DRAM mode storage unit 623 provided in the CPU-DRAM module 62 of the CPU-RAM module 60 are initialized (step S108 ). Subsequently, the information on the operation mode obtained as a result of the training sequence is stored in each of the MRAM mode storage unit 613 provided in the CPU-MRAM module 61 and the DRAM mode storage unit 623 provided in the CPU-DRAM module 62 .

Subsequently, the internal register (not shown) set in the CPU core 71 is set (step S109) and the MRAM general-purpose storage unit 611 set in the CPU-MRAM module 61 of the CPU-RAM module 60 and the CPU-DRAM module 62 are set Diagnose (check) the state of the DRAM general-purpose memory unit 621 set in (check whether an error has occurred in the memory unit) (step S110 ). In this example, the internal registers of the CPU core 71 are volatile memories.

Subsequently, the CPU core 71 reads the compressed program file stored in the compressed program storage area A112 of the first ROM area A11 provided in the CPU-ROM module 63, decompresses the read compressed program file, and converts the The decompressed program file obtained by compressing the program file is stored in the decompressed program storage area A122 of the second ROM area A12 provided in the CPU-MRAM module 61 (step S111 ).

Subsequently, the CPU core 71 completes the execution of the first IPL and starts executing the program (decompressed program) read from the decompressed program storage area A122 (step S112 ). Subsequently, for example, initialization of the CPU/PCIe interface 75 , initialization of the ASIC 521 via the CPU/PCIe interface 75 and the PCIe bus 53 , and initialization of the transceiving unit 40 are performed to set the image forming apparatus 1 into a usable state. Thereby, the start-up process during ROM booting is completed.

FIG. 9 is a diagram illustrating a start-up processing procedure during MRAM boot in step S14.

In the second or subsequent start-up process in which MRAM boot is selected, the decompressed program obtained through the previous start-up process has been stored in the decompressed program storage area A122 of the second ROM area A12 of the CPU-MRAM module 61. , while the setting information obtained through the previous startup process has already been stored in the setting information storage area A123 of the second ROM area A12 of the CPU-MRAM module 61 .

In the second or subsequent start-up process with MRAM boot selected, the mode information obtained by the previous start-up process has been stored in the MRAM mode storage unit 613 of the CPU-MRAM module 61 and the DRAM mode storage unit 613 of the CPU-DRAM module 62. Unit 623.

Furthermore, in the second or subsequent startup processing in which MRAM boot is selected, register setting values obtained through the previous startup processing have been stored in the nonvolatile setting register 724 provided in the CPU-RAM controller 72 . Therefore, in MRAM boot, unlike ROM boot, when HW reset is released, CPU-RAM controller 72 provided in CPU 511 can access CPU-RAM module 60 (CPU-MRAM module 61 and CPU-DRAM module 62 ).

In the MRAM boot, first, the CPU core 71 reads the second IPL from the second reset vector storage area A121 of the second ROM area A12 provided in the CPU-MRAM module 61 via the CPU-RAM controller 72 (step S201 ). In this case, the CPU 511 monitors the execution of the second IPL by the CPU core 71 by using the watchdog timer 74, and judges whether the second IPL is executable. In other words, when the CPU core 71 executes the second IPL, it obtains the program (read program) fails (step S202).

When the judgment result in step S202 is "Yes", the setting information is read from the setting information storage area A123 of the second ROM area A12 in the CPU-MARM module 61 via the CPU-RAM controller 72, and is controlled from the CPU-RAM. The nonvolatile setting register 724 of the register 72 reads the register setting value (step S203). Subsequently, it is judged whether the setting information read in step S203 is the same as the register setting value (step S204 ).

When the determination result in step S204 is "Yes", an internal register (not shown) provided in the CPU core 71 is set (step S205 ).

Subsequently, the CPU core 71 completes execution of the second IPL and starts executing the program (decompressed program) read from the decompressed program storage area A122 (step S206 ). Subsequently, initialization of the CPU/PCIe interface 75 , initialization of the ASIC 521 via the CPU/PCIe interface 75 and the PCIe bus 53 , and initialization of the transceiving unit 40 are performed to set the image forming apparatus 1 into a usable state, for example. Thereby, the start-up process during MRAM booting is completed.

When the judgment result in step S202 is "No" and the judgment result in step S204 is also "No", the start-up processing by ROM booting is stopped and the processing proceeds to step S15 shown in FIG. out of the ROM to boot.

For example, when there is an error in the second IPL stored in the second reset vector storage area A121 of the second ROM area A12 provided in the CPU-MRAM module 61, the determination result in step S202 is "No". For example, when there is an error in the setting information stored in the setting information storage area A123 of the second ROM area A12 in the CPU-MRAM module 61, or the register settings stored in the nonvolatile setting register 724 of the CPU-RAM controller 72 When there is an error in the value, the determination result in step S204 is "No". Also, for example, when the CPU-MRAM module 61 has been replaced after the previous boot process and before the current boot process, the result of determination in step S204 is "No".

In the second or subsequent startup processing, when the judgment result in step S13 is "Yes" and the judgment result in step S202 or step S204 is "No", the ROM in step S15 (Fig. 8) is executed again Boot to execute startup processing including a training sequence or decompressing a compressed program, and operate the image forming apparatus 1 normally.

In the second or subsequent startup processing, when the judgment result in step S13 is "No" and the judgment result in step S202 or step S204 is "Yes", the startup processing omitting the initialization setting is executed and the startup processing The time required is reduced. In the flowchart of ROM boot shown in FIG. 8 , steps indicated by bold frames correspond to steps omitted in MRAM boot shown in FIG. 9 . In this example, the MRAM boot took about 3.4 seconds less to boot than the ROM boot. This is because the time (about 3.3 seconds) required for reading, decompressing, and storing the compressed program in step S111 shown in FIG. 8 is omitted.

In this exemplary embodiment, the CPU-MRAM module 61 and the CPU-DRAM module 62 form the CPU-RAM module 60, but the present invention is not limited thereto. For example, the CPU-RAM module 60 may be formed using only the CPU-MRAM module 61 .

In this exemplary embodiment, the CPU-MRAM module 61 is used as a nonvolatile memory forming the CPU-RAM module 60, but the present invention is not limited thereto. For example, FeRAM (Ferroelectric Memory), PRAM (Phase Change Memory), or ReRAM (Resistance RAM: Resistance Memory) can be used as the nonvolatile memory used in the CPU-RAM module 60 .

In this exemplary embodiment, a program executed by a computer (CPU 511 ) is stored in a computer-readable storage medium. For example, considering that a CD-ROM medium corresponds to a storage medium, a CD-ROM reader of a computer reads a program, and the program is stored in various memories such as a hard disk in the computer, and then executed. Furthermore, it is considered, for example, that a program transmission device provides a program to a notebook PC or a portable terminal via a network. The program transfer device may include a memory storing the program and a program transfer unit providing the program via a network.

The foregoing description of exemplary embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and changes will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to learn for various embodiments and with various modifications as are suited to the particular use contemplated. understand the invention. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

Claims (7)

1. An information processing device, the information processing device comprising: an execution unit that executes the program; a main storage unit including a readable and writable first nonvolatile memory capable of retaining stored information even when no power is supplied, and the main storage unit is provided with a first storage area storing the program executed by the execution unit and a second storage area storing data generated by the execution unit executing the program; a connection unit connecting the execution unit and the main storage unit; and a condition storage unit which includes a readable and writable second nonvolatile memory capable of retaining stored information even when there is no power supply, and which stores the all The setting conditions set by the connection unit for sending and receiving the program and the data between the execution unit and the main storage unit, the setting conditions include the maximum available clock frequency or signal timing. 2. The information processing device according to claim 1, further comprising: a setting unit that sets communication conditions for communication between the connection unit and the main storage unit before the connection unit connects the execution unit and the main storage unit, as the setting condition, Wherein, the condition storage unit stores the communication condition set by the setting unit as the setting condition. 3. The information processing device according to claim 1 or 2, Wherein, the main storage unit also includes a readable and writable volatile memory, the volatile memory cannot maintain the stored information when there is no power supply, and The volatile memory is provided with the second storage area. 4. The information processing device according to claim 1 or 2, Wherein, the first non-volatile memory of the main storage unit is any one of MRAM, FeRAM, PRAM, and ReRAM. 5. An image forming apparatus comprising: an image forming unit that forms an image on the recording material; and a control unit that controls the operation of the image forming unit, Wherein, the control unit includes: an execution unit that executes a program for controlling the image forming unit; a main storage unit including a readable and writable first nonvolatile memory capable of retaining stored information even when no power is supplied, and the main storage unit is provided with a first storage area storing the program executed by the execution unit and a second storage area storing data generated by the execution unit executing the program; a connection unit connecting the execution unit and the main storage unit; and a condition storage unit which includes a readable and writable second nonvolatile memory capable of retaining stored information even when there is no power supply, and which stores the all Conditions set by the connection unit for sending and receiving the program and the data between the execution unit and the main storage unit, the conditions include a maximum available clock frequency or signal timing. 6. An information processing method, the information processing method comprising the following steps: Execute steps, execute procedures; The step of setting a storage area is to set a first storage area for storing the program and a second storage area for storing data generated by executing the program in a readable and writable first non-volatile memory, the first non-volatile memory Volatile memory retains stored information even when there is no power supply; a connecting step of connecting a computer to the first non-volatile memory; and a step of storing the setting conditions, storing the set conditions in a readable and writable second non-volatile memory, sending the program and the data to the first non-volatile memory and The second non-volatile memory is capable of retaining stored information even when power is not supplied, including a maximum available clock frequency or signal timing. 7. The information processing method according to claim 6, the information processing method further comprising the following steps: a step of setting a communication condition, prior to connecting to the first nonvolatile memory, setting a communication condition for communicating with the first nonvolatile memory, as the setting condition, Wherein, in the step of storing the setting conditions, the communication conditions are stored in the second non-volatile memory as the setting conditions.