CN103281071B - Latch and comprise the divider circuit of this latch - Google Patents

Abstract

The invention relates to a semiconductor device, and discloses a latch and a frequency divider circuit comprising the latch. In the present invention, the latch realizes the processing of two pairs of differential signals on the same current path, realizes multiplexing of current, saves chip area, and reduces power consumption. Using the above latch in the frequency divider circuit, compared with the traditional frequency divider circuit, half of the latches will be used to achieve the same function, saving area and reducing power consumption. At the same time, due to the simple circuit structure, the output signal can be greatly improved The phase orthogonality and amplitude matching can improve the performance of the circuit, and in the feedback path, adding a few more stages of latches can be easily expanded into frequency dividers with different distribution modes, and the scalability is good.

Description

Latch and frequency divider circuit including the latch

technical field

The present invention relates to semiconductor devices, and more particularly to a latch and a frequency divider circuit including the latch.

Background technique

The frequency divider circuit is a very important circuit module in the wireless communication chip. It is usually used after the frequency synthesizer to divide the frequency of the high-frequency carrier generated by the frequency synthesizer in order to generate a carrier signal that meets the requirements of the wireless channel; The performance of the frequency divider directly determines the quality of the output RF signal, and the power consumption of the frequency divider has gradually become the bottleneck that limits the power consumption of the entire wireless communication chip. At present, in order to support high-quality signal modulation and demodulation, the quadrature signal processing mode has been widely used in wireless communication chips, that is, two quadrature signals of I and Q, and the phase difference between them is 90 degrees, that is, 1/4 A cycle. Therefore, quadrature signal frequency divider circuits with high performance and low power consumption have become a major research hotspot.

Generally, the current existing Complementary Metal-Oxide Semiconductor ("CMOS") frequency divider can be shown in Figure 1, mainly including two latch sub-modules (Latch 1 and Latch 2), their data input and output signals D, DN and Q, QN are connected end to end to form a positive feedback loop. Its input signals INPUT_P and INPUT_N are a pair of differential signals with a phase difference of 180 degrees, that is, half a cycle. Its output signals OUT_P and OUT_N are a pair of differential signals. However, the frequency of the output signal is half of the frequency of the input signal, that is, its cycle is twice that of the input signal, thereby realizing the function of dividing the frequency by two of the input signal. The CMOS circuit in each latch is shown in Figure 2, including a differential input stage and a positive feedback coupled comparison output stage, the differential input stage includes power supply, resistors r1, r2 and transistors m1, m2, m3, m4, The differential input stage amplifies the difference of the input signals, and the output comparison stage includes transistors m5 and m6, and the output comparison stage performs shaping and outputting the previously amplified signal.

Therefore, the existing quadrature signal frequency divider is also derived from this CMOS frequency divider. The specific structure is shown in Figure 3. It mainly includes mutually orthogonal I, Q two-way frequency dividers, and a total of 4 latches. The input signals INPUT_IP and INPUT_IN are a pair of differential signals, INPUT_QP and INPUT_QN are another pair of differential signals, and INPUT_IP and INPUT_QP are a pair of quadrature signals with a phase difference of 90 degrees, which is a quarter of a cycle. The output signals OUT_IP and OUT_IN of the quadrature frequency divider are a pair of differential signals, OUT_QP and OUT_QN are another pair of differential signals, and OUT_IP and OUT_QP are a pair of quadrature signals with a phase difference of 90 degrees, that is, quarter one cycle. It is worth noting that the output signal is half the frequency of the input signal, that is, the function of frequency division by two is realized. However, the inventors of the present invention have found that this kind of frequency divider has a large area and relatively large power consumption. Due to its relatively strong complexity, when dealing with high-frequency signals, especially radio frequency signals, the phase of its analog output signal is positive. Intercourse and amplitude matching are difficult to guarantee, that is, the phase difference will deviate from 90 degrees, and the amplitude will be different, thus affecting the performance of the entire system.

Contents of the invention

The purpose of the present invention is to provide a latch and a frequency divider circuit including the latch, which can realize the frequency division function of the input quadrature signal, and has the advantages of low power consumption, small area and high performance.

In order to solve the above technical problems, the embodiment of the present invention discloses a latch, including a differential input stage circuit and an output comparison stage circuit;

The differential input stage circuit consists of:

A first differential pair of tubes, the first differential pair of tubes takes a data input signal and a complementary data input signal as input signals, and outputs a complementary data output signal and a data output signal;

The first and second loads are connected between the power supply and the two first poles of the first differential pair;

Multiplexing differential pair tubes, including a second differential pair tube and a third differential pair tube, the second and third differential pair tubes are respectively used to control the first differential pair tube and output comparison through two pairs of orthogonal differential signals The current path between the stage circuit and the ground;

The output comparator circuit consists of:

The cross-coupling positive feedback circuit performs shaping output on the output signal of the differential input stage circuit.

The embodiment of the present invention also discloses a frequency divider circuit, including at least two of the above-mentioned latches, each of which includes a data signal input terminal, a complementary data signal input terminal, a first trigger signal input terminal, and a second trigger signal input terminal. terminals, first and second complementary trigger signal input terminals, data signal output terminals and complementary data signal output terminals;

Each first trigger signal input terminal is connected to the first trigger signal, and each first complementary trigger signal input terminal is connected to the first complementary trigger signal;

Each second trigger signal input terminal is connected to the second trigger signal, and each second complementary trigger signal input terminal is connected to the second complementary trigger signal;

The latches are connected in series, and the data signal output end and the complementary data signal output end of one latch are respectively connected with the data signal input end and the complementary data signal input end of the other latch to form a positive feedback circuit, wherein The data signal input end and the complementary data signal input end of a latch respectively output the first complementary data output signal and the first data output signal, and the data signal output end and the complementary data signal output end of the latch output the second complementary data signal output respectively. a data output signal, a second data output signal;

The first trigger signal and the second trigger signal are orthogonal signals.

The embodiment of the present invention also discloses a frequency divider circuit, including at least two latches as above, each latch includes a data signal input end, a complementary data signal input end, a first and a second trigger signal Input terminal, first and second complementary trigger signal input terminals, data signal output terminal, complementary data signal output terminal and bias terminal;

Each first trigger signal input terminal is connected to the first trigger signal, and each first complementary trigger signal input terminal is connected to the first complementary trigger signal;

Each second trigger signal input terminal is connected to the second trigger signal, and each second complementary trigger signal input terminal is connected to the second complementary trigger signal;

Each bias terminal is connected with a bias voltage signal;

The latches are connected in series, and the data signal output end and the complementary data signal output end of one latch are respectively connected with the data signal input end and the complementary data signal input end of the other latch to form a positive feedback circuit; The data signal input end and the complementary data signal input end of a latch respectively output the first complementary data output signal and the first data output signal, and the data signal output end and the complementary data signal output end of the latch output the second complementary data signal output respectively. a data output signal, a second data output signal;

The first trigger signal and the second trigger signal are orthogonal signals.

Compared with the prior art, the embodiment of the present invention has the main difference and its effects in that:

The latch of the invention realizes the processing of two pairs of differential signals on the same current path, realizes multiplexing of current, saves chip area and reduces power consumption.

Using the above latch in the frequency divider circuit, compared with the traditional frequency divider circuit, half of the latches will be used to achieve the same function, saving area and reducing power consumption. At the same time, due to the simple circuit structure, the output signal can be greatly improved The phase orthogonality and amplitude matching can improve the performance of the circuit, and in the feedback path, adding a few more stages of latches can be easily expanded into frequency dividers with different distribution modes, and the scalability is good.

Furthermore, a MOS transistor connected to a bias voltage signal is added to the latch, so that the entire latch is in a better working area.

Description of drawings

Fig. 1 is the structural representation of existing a kind of frequency divider circuit;

FIG. 2 is a structural schematic diagram of an existing latch;

Fig. 3 is a structural schematic diagram of an existing frequency divider circuit;

4 is a schematic structural diagram of a latch in the first embodiment of the present invention;

5 is a schematic structural diagram of a latch in the second embodiment of the present invention;

6 is a schematic structural diagram of a frequency divider circuit in a third embodiment of the present invention;

7 is a timing diagram of two pairs of input signals and one pair of output signals of a frequency divider circuit in the third embodiment of the present invention;

8 is a schematic structural diagram of a frequency divider circuit in a third embodiment of the present invention;

9 is a schematic structural diagram of a frequency divider circuit in a fourth embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a frequency divider circuit in a fourth embodiment of the present invention.

detailed description

In the following description, many technical details are proposed in order to enable readers to better understand the application. However, those skilled in the art can understand that without these technical details and various changes and modifications based on the following implementation modes, the technical solution claimed in each claim of the present application can be realized.

In order to make the purpose, technical solution and advantages of the present invention clearer, the following will further describe the implementation of the present invention in detail in conjunction with the accompanying drawings.

The first embodiment of the present invention relates to a latch. FIG. 4 is a schematic diagram of the structure of the latch. As shown in FIG. 4, the latch includes a differential input stage circuit I and an output comparison stage circuit II.

The differential input stage circuit I includes:

A first differential pair of transistors, the first differential pair of transistors takes a data input signal and a complementary data input signal as input signals, and outputs a complementary data output signal and a data output signal.

The first and second loads are connected between the power supply VDD and the two first poles of the first differential pair.

It can be understood that, in various embodiments of the present invention, the first load and the second load may be active or passive. Optionally, in this implementation manner, the load is the first and second resistors R1 and R2 as shown in FIG. 4 , preferably, R1 and R2 are equal. It can be understood that in other embodiments of the present invention, R1 and R2 may also be unequal.

Multiplexed differential pair tubes, including the second differential pair tube and the third differential pair tube, are connected between the first differential pair tube and the output comparison stage circuit II and the ground, and the second and third differential pair tubes are respectively used for passing Two pairs of orthogonal differential signals control the current path between the first differential pair transistor and the output comparison stage circuit II and the ground GND.

The output comparator circuit II includes:

The cross-coupling positive feedback circuit performs shaping and outputting the output signal of the differential input stage circuit I.

Specifically, as shown in FIG. 4 , the first differential pair includes a first MOS transistor M1 and a second MOS transistor M2 . The gates of transistors M1 and M2 are respectively used as data signal input terminals D and complementary data signal input terminals DN to connect data input signals and complementary data input signals, and the first poles of transistors M1 and M2 are respectively used as complementary data signal output terminals QN, data signal The output terminal Q outputs a complementary data output signal and a data output signal, and the two second stages are connected together. It can be understood that the transistors M1 and M2 can be formed by cascading multiple transistors respectively.

In the above-mentioned multiplexed differential pair transistor, the second differential pair transistor includes the fifth MOS transistor M5 and the sixth MOS transistor M6, and the gates of the transistors M5 and M6 are respectively used as the first trigger signal input terminal CKP1 and as the second trigger signal The input terminal CKP2 is connected to the first trigger signal In_IP and the second trigger signal In_QP, the first poles of the transistors M5 and M6 are connected to the second poles of the transistors M1 and M2 respectively, and the second poles of the transistors M5 and M6 are both grounded.

The third differential pair of transistors includes a seventh MOS transistor M7 and an eighth MOS transistor M8, and the gates of the transistors M7 and M8 are connected to the first complementary trigger signal input terminal CKN1 and the second complementary trigger signal input terminal CKN2 respectively. For the trigger signal In_IN and the second complementary trigger signal In_QN, the first poles of the transistors M7 and M8 are connected to the second poles of the transistors M3 and M4 respectively, and the second poles of the transistors M7 and M8 are both grounded.

The above-mentioned cross-coupled positive feedback circuit includes a third MOS transistor M3 and a fourth MOS transistor M4, the gate of the transistor M3 and the first pole of the transistor M4 are connected together and connected to the first pole of the transistor M2, and the gate of the transistor M4 and the first pole of the transistor M3 are connected together and connected to the first pole of the transistor M1, wherein the second poles of the transistors M3 and M4 are connected together.

Wherein, the first trigger signal In_IP and the first complementary trigger signal In_IN are a pair of differential signals, the second trigger signal In_QP and the second complementary trigger signal In_QN are a pair of differential signals, and the first trigger signal In_IP and the second trigger signal In_QP is a quadrature signal

It can be understood that the two pairs of differential signals are orthogonal signals, which can control the current path in time division, so even if the source and drain of each MOS transistor are connected together, it is guaranteed that they will not affect their respective functions.

In this embodiment, preferably, the transistors M1 to M8 are of the same semiconductor type, and the transistors M1 to M8 are NMOS transistors, the above-mentioned first pole is a drain, and the above-mentioned second pole is a source.

It can be understood that in other embodiments of the present invention, each MOS transistor can also be a PMOS transistor, then the above-mentioned first pole is the source, and the second pole is the drain. Correspondingly, the power supply needs to be adjusted to a negative power supply or the power supply and The positions of the ground terminals are exchanged to realize the technical solution of the present invention.

In addition, it can be understood that in other embodiments of the present invention, the types of MOS transistors are not limited to the above-mentioned forms, and since the allocation and connection of MOS transistors of various semiconductor types are common knowledge of those skilled in the art, details are not repeated here.

In this embodiment, the latch realizes the processing of two pairs of differential signals on the same current path, realizes multiplexing of current, saves chip area, and reduces power consumption.

A second embodiment of the present invention relates to a latch. FIG. 5 is a schematic diagram of the structure of the latch.

The second embodiment is improved on the basis of the first embodiment. The main improvement is that a ninth MOS transistor M9 connected to the bias voltage signal is added to the latch to make the entire latch in a better state. Work area. Specifically:

The above-mentioned latch also includes a ninth MOS transistor, that is, the transistor M9 in FIG. It is connected with the second pole of the transistors M5, M6, M7 and M8 in the multiplexing differential pair, and the gate of the transistor M9 is used as a bias voltage terminal to connect to the bias voltage signal VB.

In addition, it can be understood that in other implementation manners of the present invention, there may be no ninth MOS transistor.

The third embodiment of the present invention relates to a frequency divider circuit. FIG. 6 is a schematic structural diagram of the frequency divider circuit. As shown in Figure 6, the frequency divider circuit includes at least two of the above-mentioned latches (Latch 1 and Latch 2 in Figure 6), each latch includes a data signal input terminal D, complementary data Signal input terminal DN, first and second trigger signal input terminals CKP1 and CKP2, first and second complementary trigger signal input terminals CKN1 and CKN2, data signal output terminal Q and complementary data signal output terminal QN.

Each first trigger signal input terminal CKP1 is connected to the first trigger signal In_IP, and each first complementary trigger signal input terminal CKN1 is connected to the first complementary trigger signal In_IN.

Each second trigger signal input terminal CKP2 is connected to the second trigger signal In_QP, and each second complementary trigger signal input terminal CKN2 is connected to the second complementary trigger signal In_QN.

The latches are connected in series, such as latch 1 and latch 2 in Figure 6, the data signal output Q and the complementary data signal output QN of one latch (such as latch 1) are respectively connected to the other The data signal input terminal D of the latch (such as latch 2) and the complementary data signal input terminal DN are connected to form a positive feedback circuit, and the data signal input terminal D of one of the latches (such as latch 1) The complementary data signal input terminal DN respectively outputs the first complementary data output signal Out_IN and the first data output signal Out_IP, and the data signal output terminal Q and complementary data signal output terminal QN of the latch respectively output the second complementary data output signal Out_QN , the second data output signal Out_QP.

The first trigger signal ln_IP and the second trigger signal ln_QP are quadrature signals.

Fig. 7 is a timing diagram of two pairs of input signals and one pair of output signals of a two-frequency divider circuit. An example of a two-frequency divider circuit will be described in detail below in conjunction with FIG. 6 and FIG. 7 .

In this example, the frequency divider circuit basically consists of two latches connected end to end, forming a positive feedback loop. The first trigger signal In_IP and the first complementary trigger signal In_IN input by it are a pair of differential signals, the second trigger signal In_QP and the second complementary trigger signal In_QN are another pair of differential signals, and the first trigger signal In_IP and the second trigger signal The signal In_QP is a pair of quadrature signals with a phase difference of 90 degrees, that is, a quarter period. The output signals of the quadrature frequency divider, the first data output signal Out_IP and the first complementary data output signal Out_IN are a pair of differential signals, the second data output signal Out_QP and the second complementary data output signal Out_QN are another pair of differential signals, The first data output signal Out_IP and the second data output signal Out_QP are a pair of quadrature signals with a phase difference of 90 degrees, that is, a quarter period. It is worth noting that the data output signal is half the frequency of the trigger signal, that is, the function of frequency division by two is realized.

As an optional implementation manner, an N-level frequency divider circuit as shown in FIG. 8 can be formed by connecting N stages of latches in series.

In this embodiment, the above-mentioned latches are used in the frequency divider circuit. Compared with the traditional frequency divider circuit, half of the latches are used to achieve the same function, which saves area and reduces power consumption. At the same time, due to the simple circuit structure, It can greatly improve the phase orthogonality and amplitude matching of the output signal, improve the performance of the circuit, and add a few more stages of latches on the feedback path, it can be easily expanded into a frequency divider with different distribution modes, which is scalable Good sex.

The fourth embodiment of the present invention relates to a frequency divider circuit. FIG. 9 is a schematic structural diagram of the frequency divider circuit. As shown in Figure 9, the frequency divider circuit includes at least two of the above-mentioned latches (Latch 1 and Latch 2 in Figure 9), each latch includes a data signal input terminal D, a complementary data signal Input terminal DN, first and second trigger signal input terminals CKP1 and CKP2, first and second complementary trigger signal input terminals CKN1 and CKN2, data signal output terminal Q, complementary data signal output terminal QN and bias voltage terminal VB.

Each first trigger signal input terminal CKP1 is connected to the first trigger signal In_IP, and each first complementary trigger signal input terminal CKN1 is connected to the first complementary trigger signal In_IN.

Each second trigger signal input terminal CKP2 is connected to the second trigger signal In_QP, and each second complementary trigger signal input terminal CKN2 is connected to the second complementary trigger signal In_QN.

Each bias terminal VB is connected to a bias voltage signal VB.

The latches are connected in series, as shown in Fig. 9, latch 1 and latch 2, the data signal output Q and complementary data signal output QN of one latch (such as latch 1) are respectively connected to the other The data signal input terminal D of the latch (such as latch 2) and the complementary data signal input terminal DN are connected to form a positive feedback circuit, and the data signal input terminal D of one of the latches (such as latch 1) The complementary data signal input terminal DN respectively outputs the first complementary data output signal Out_IN and the first data output signal Out_IP, and the data signal output terminal Q and complementary data signal output terminal QN of the latch respectively output the second complementary data output signal Out_QN , the second data output signal Out_QP.

The first trigger signal ln_IP and the second trigger signal ln_QP are quadrature signals.

As an optional implementation manner, an N-level frequency divider circuit as shown in FIG. 10 can be formed by connecting N stages of latches in series.

In this embodiment, the above-mentioned latches are used in the frequency divider circuit. Compared with the traditional frequency divider circuit, half of the latches are used to achieve the same function, which saves area and reduces power consumption. At the same time, due to the simple circuit structure, It can greatly improve the phase orthogonality and amplitude matching of the output signal, improve the performance of the circuit, and add a few more stages of latches on the feedback path, it can be easily expanded into a frequency divider with different distribution modes, which is scalable Good sex. In addition, a MOS transistor connected to the bias voltage signal is added to the latch, so that the entire latch is in a better working area.

It should be noted that in the claims and description of this patent, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or Any such actual relationship or order between such entities or operations is implied. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Although the present invention has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the present invention. The spirit and scope of the invention.

Claims (5)

1. A latch, characterized in that, comprises a differential input stage circuit and an output comparison stage circuit; The differential input stage circuit includes: A first differential pair of tubes, the first differential pair of tubes takes a data input signal and a complementary data input signal as input signals, and outputs a complementary data output signal and a data output signal; The first and second loads are connected between the power supply and the two first poles of the first differential pair; Multiplexing differential pair tubes, including a second differential pair tube and a third differential pair tube, the second and third differential pair tubes are respectively used to control the first differential pair tube and output comparison through two pairs of orthogonal differential signals The current path between the stage circuit and the ground; The output comparator circuit includes: A cross-coupling positive feedback circuit for shaping and outputting the output signal of the differential input stage circuit; Wherein, the first differential pair of transistors includes a first metal oxide semiconductor MOS transistor and a second MOS transistor, and the gates of the first and second MOS transistors are respectively connected to the data input signal and the complementary data input signal, the first poles of the first and second MOS transistors respectively output complementary data output signals and data output signals, the second poles are connected together, and the first load is connected between the power supply and the first MOS transistor between the first poles of the second load connected between the power supply and the first pole of the second MOS transistor; In the multiplexed differential pair transistor, the second differential pair transistor includes a fifth MOS transistor and a sixth MOS transistor, and the gates of the fifth and sixth MOS transistors are respectively connected to the first trigger signal and the second trigger signal, The first poles of the fifth and sixth MOS transistors are respectively connected to the second poles of the first and second MOS transistors, and the second poles of the fifth and sixth MOS transistors are both grounded; The third differential pair of transistors includes a seventh MOS transistor and an eighth MOS transistor, and the gates of the seventh and eighth MOS transistors are respectively connected to the first complementary trigger signal and the second complementary trigger signal, and the seventh and eighth MOS transistors The first poles of the third and fourth MOS transistors are respectively connected to the second poles of the third and fourth MOS transistors, and the second poles of the seventh and eighth MOS transistors are both grounded; The cross-coupled positive feedback circuit includes a third MOS transistor and a fourth MOS transistor, the gate of the third MOS transistor and the first pole of the fourth MOS transistor are connected together and connected to the first pole of the second MOS transistor. pole; The gate of the fourth MOS transistor and the first pole of the third MOS transistor are connected together and connected to the first pole of the first MOS transistor; The second poles of the third and fourth MOS transistors are connected together; The first trigger signal and the first complementary trigger signal are a pair of differential signals, the second trigger signal and the second complementary trigger signal are a pair of differential signals, and the first trigger signal and the second trigger signal are positive traffic signal; The MOS transistors are all NMOS transistors, the first pole of which is the drain, and the second pole is the source; or the MOS transistors are all PMOS transistors, the first pole of which is the source, and the second pole is the drain. 2. The latch according to claim 1, wherein the first and second loads are active loads or passive resistors, connected to the two first poles of the first differential pair and the power supply between, and the first and second load impedance values are equal. 3. The latch according to claim 1 or 2, further comprising a ninth MOS transistor, the ninth MOS transistor is connected in series between the multiplexing differential pair transistor and the ground, and the ninth MOS transistor of the ninth MOS transistor The two poles are grounded, the first pole is connected to the second poles of the fifth, sixth, seventh, and eighth MOS transistors in the multiplexed differential pair, and the gate of the ninth MOS transistor is used as a bias terminal for biasing voltage signal. 4. A frequency divider circuit, characterized in that, comprises at least two latches as claimed in claim 1 or 2, each latch includes a data signal input end, a complementary data signal input end, the first, The second trigger signal input terminal, the first and second complementary trigger signal input terminals, the data signal output terminal and the complementary data signal output terminal; Each first trigger signal input terminal is connected to the first trigger signal, and each first complementary trigger signal input terminal is connected to the first complementary trigger signal; Each second trigger signal input terminal is connected to the second trigger signal, and each second complementary trigger signal input terminal is connected to the second complementary trigger signal; The latches are connected in series, and the data signal output end and the complementary data signal output end of one latch are respectively connected with the data signal input end and the complementary data signal input end of the other latch to form a positive feedback circuit; one of them The data signal input end and the complementary data signal input end of the latch respectively output the first complementary data output signal and the first data output signal, and the data signal output end and the complementary data signal output end of the latch respectively output the second complementary data an output signal, a second data output signal; The first trigger signal and the second trigger signal are orthogonal signals. 5. A frequency divider circuit, is characterized in that, comprises at least two latches as claimed in claim 3, each latch comprises data signal input end, complementary data signal input end, first, second Trigger signal input terminal, first and second complementary trigger signal input terminals, data signal output terminal, complementary data signal output terminal and bias voltage terminal; Each first trigger signal input terminal is connected to the first trigger signal, and each first complementary trigger signal input terminal is connected to the first complementary trigger signal; Each second trigger signal input terminal is connected to the second trigger signal, and each second complementary trigger signal input terminal is connected to the second complementary trigger signal; Each bias terminal is connected with a bias voltage signal; The latches are connected in series, and the data signal output end and the complementary data signal output end of one latch are respectively connected with the data signal input end and the complementary data signal input end of the other latch to form a positive feedback circuit; The data signal input end and the complementary data signal input end of a latch respectively output the first complementary data output signal and the first data output signal, and the data signal output end and the complementary data signal output end of the latch output the second complementary data signal output respectively. a data output signal, a second data output signal; The first trigger signal and the second trigger signal are orthogonal signals.