CN103280176B - A kind of vertical transfer register and control method, IC chip and TFT panel - Google Patents
A kind of vertical transfer register and control method, IC chip and TFT panel Download PDFInfo
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Abstract
The embodiment of the present invention provides a kind of vertical transfer register and control method thereof, IC chip and TFT panel, vertical transfer register can be connected with IC chip by a control line, the initial shift signal that vertical transfer register the 1st grade of shift register cell needs directly can be provided by this control line, the reset signal that vertical transfer register the 2nd grade of shift register cell needs to N level shift register cell can be provided through reverser by this control line, thus reduce control line quantity, reduce taking of placement-and-routing design space, and outermost control line being arranged on VSR circuit can be avoided, effectively prevent ESD from producing.
Description
Technical field
The present invention relates to Thin Film Transistor (TFT) liquid crystal display (TFT-LCD) technical field, particularly relate to a kind of vertical transfer register and control method, IC chip and TFT panel.
Background technology
At present, on Thin Film Transistor (TFT) (TFT) panel, can include: comprise effective display area (AA) district (can represent with AA) of multiple pixel electrode, carry out the vertical transfer register (VSR) of switch control rule for the TFT connected each pixel electrode in AA district and provide the integrated circuit of signal (IC) chip (can represent with IC) for VSR, the structure of TFT panel can be as shown in Figure 1.
The structural representation of existing VSR can be as shown in Figure 2, VSR can comprise the shift register cell (SR) of multiple cascade, and reset circuit has been included in each SR, therefore VSR needs IC chip to provide initial shift signal (GSP) and reset signal (RESET).Disclose in Chinese patent application CN101978428A, IC chip is respectively VSR by two signal line and provides GSP signal and RESET signal, therefore can cause taking more placement-and-routing's design (Layout) space.When the placement-and-routing's design carrying out VSR circuit, GSP signal wire can be arranged on the outermost of VSR circuit, easily causes the generation of Electro-static Driven Comb (ESD).
Simultaneously, the device used due to existing VSR is more, cause circuit power consumption larger, and TFT panel periphery circuit light transmission rate can be caused less, according to without shadow glue (UV glue) as fluid sealant (Seal glue), the solidification of UV glue can be made to be affected, there is UV glue cannot solidify completely, or, although can solidify completely, reach time of solidifying needs completely longer problem.
Summary of the invention
The embodiment of the present invention provides a kind of vertical transfer register and control method, IC chip and TFT panel, for reducing taking of VSR circuit layout wires design space, reduces the generation of ESD.
A kind of vertical transfer register, described vertical transfer register comprises the N level shift register cell from the 1st grade of shift register cell to N level shift register cell successively cascade, described N be greater than 1 positive integer, wherein:
The shift signal input end of the 1st grade of shift register cell is connected with the output terminal of IC chip by control line;
2nd grade of shift register cell is to the every one-level shift register cell in N level shift register cell, and reset terminal is connected with the output terminal of reverser, and the input end of reverser is connected with the output terminal of IC chip by described control line.
To the method that vertical transfer register as above controls, described method comprises:
The control signal exported by the output terminal of IC chip inputs the shift signal input end of the 1st grade of shift register cell as initial shift signal, and the signal of this control signal after is oppositely inputted the reset terminal of the 2nd grade of shift register cell to every grade of shift register cell in N level shift register cell as reset signal.
A kind of IC chip, the output terminal of described IC chip connects vertical transfer register as above, provides control signal to described vertical transfer register.
A kind of Thin Film Transistor (TFT) TFT panel, described TFT panel comprises vertical transfer register as above.
According to the scheme that the embodiment of the present invention provides, vertical transfer register can be connected with IC chip by a control line, the initial shift signal that vertical transfer register the 1st grade of shift register cell needs directly can be provided by this control line, the reset signal that vertical transfer register the 2nd grade of shift register cell needs to N level shift register cell can be provided through reverser by this control line, thus reduce control line quantity, reduce taking of placement-and-routing design space, and outermost control line being arranged on VSR circuit can be avoided, effectively prevent ESD from producing.
Accompanying drawing explanation
The TFT panel construction schematic diagram that Fig. 1 provides for prior art;
The structural representation of the VSR that Fig. 2 provides for prior art;
The structural representation of the VSR that Fig. 3 provides for the embodiment of the present invention one;
The connection diagram of the VSR that Fig. 4 provides for the embodiment of the present invention one;
The circuit diagram symbol that Fig. 5 provides for the embodiment of the present invention one;
The circuit diagram symbol that Fig. 6 provides for the embodiment of the present invention one;
The 1st grade of shift register cell structural representation that Fig. 7 provides for the embodiment of the present invention one;
The jth level shift register cell structural representation that Fig. 8 provides for the embodiment of the present invention one;
I-th grade of shift register cell structural representation that Fig. 9 provides for the embodiment of the present invention one;
The time diagram that Figure 10 provides for the embodiment of the present invention two.
Embodiment
Two signal wires are needed to provide reset signal and initial shift signal respectively to VSR for IC chip in prior art, cause taking more Layout space, and when the placement-and-routing's design carrying out VSR circuit, GSP signal wire can be arranged on the outermost of VSR circuit, easily cause the problem of the generation of ESD, the embodiment of the present invention proposes to provide reset signal and initial shift signal in conjunction with reverser to VSR by a signal wire by IC chip, thus reduce signal wire quantity, reduce Layout space hold, and avoid outermost signal wire being arranged on VSR circuit, reduce the generation of ESD.
Below in conjunction with Figure of description and each embodiment, the present invention program is described.
Embodiment one,
The embodiment of the present invention one provides a kind of vertical transfer register, the structure of this vertical transfer register can be as shown in Figure 3, the N level shift register cell comprised from the 1st grade of shift register cell to N level shift register cell successively cascade (uses SR1 successively, SR2 ... SRN represents), described N be greater than 1 positive integer, wherein:
The shift signal input end of the 1st grade of shift register cell is connected by the output terminal of control line with IC chip (can represent with IC);
2nd grade of shift register cell is to the every one-level shift register cell in N level shift register cell, the output terminal of reset terminal and reverser (can represent with the INV) tip of Nverter circuit schematic symbol (namely in Fig. 3) is connected, and the input end of the reverser wide end of Nverter circuit schematic symbol (namely in Fig. 3) is connected with the output terminal of IC chip by described control line.
Concrete, the connection diagram of the vertical transfer register that the present embodiment provides (can show in particular the connection diagram of vertical transfer register the 1st grade of shift register cell to the 4th grade of shift register cell) as shown in Figure 4 in Fig. 4, wherein, the signal that the output terminal of IC chip is provided by control line can represent with S & R, first clock signal input terminal CLKA represents, first clock signal CLK1 represents, second clock signal input part CLKB represents, second clock signal CLK2 represents:
First clock signal input terminal CLKA of described 1st grade of shift register cell receives the first clock signal clk 1, and second clock signal input part CLKB receives second clock signal CLK2.Certainly, the shift signal input end (can represent with In1) of the 1st grade of shift register cell is connected with the output terminal of IC chip by control line.As shown in Figure 4, in the present embodiment, the drive output of the 1st grade of shift register cell can represent with GOUT1.
Described 2nd grade of shift register cell is to i-th grade of shift register cell in N level shift register cell, the shift signal input end (can represent with Ini) of each i-th grade of shift register cell is connected with the shift signal output terminal (can represent with NEXTi-1) of the i-th-1 grade shift register cell, first clock signal input terminal CLKA receives the first clock signal clk 1, second clock signal input part CLKB receives second clock signal CLK2, wherein, i is greater than the odd number that 1 is not more than N.Certainly, the reset terminal (reset terminal can represent with XRESET) of each i-th grade of shift register cell is connected with the output terminal of reverser (can represent with INV), and the input end of reverser is connected with the output terminal of IC chip by described control line.As shown in Figure 4, in the present embodiment, the drive output of i-th grade of shift register cell can represent with GOUTi.
2nd grade of shift register cell is to the jth level shift register cell in N level shift register cell, the shift signal input end (can represent with Inj) of each jth level shift register cell is connected with the shift signal output terminal (can represent with NEXTj-1) of jth-1 grade of shift register cell, first clock signal input terminal CLKA receives second clock signal CLK2, second clock signal input part CLKB receives the first clock signal clk 1, wherein, j is greater than the even number that 1 is not more than N.Certainly, the reset terminal of each jth level shift register cell is connected with the output terminal of reverser, and the input end of reverser is connected with the output terminal of IC chip by described control line.As shown in Figure 4, in the present embodiment, the drive output of jth level shift register cell can represent with GOUTj.
In the present embodiment, 1st grade of shift register cell is without the need to comprising reset terminal, the circuit diagram symbol of the 1st grade of shift register cell can be as shown in Figure 5, wherein, first clock signal input terminal CLKA represents, second clock signal input part CLKB represents, shift signal input end IN represents, shift signal output terminal NEXT represents, drive output GOUT represents.
And because the 1st grade of shift register cell is without the need to comprising reset terminal, the device that VSR uses can be reduced, the device solving existing VSR use is more, cause circuit power consumption larger, and TFT panel periphery circuit light transmission rate can be caused less, according to without shadow glue (UV glue) as fluid sealant (Seal glue), the solidification of UV glue can be made to be affected, there is UV glue cannot solidify completely, or, although can solidify completely, reach time of solidifying needs completely longer problem.
2nd grade of shift register cell can be as shown in Figure 6 to the circuit diagram symbol of the every one-level shift register cell in N level shift register cell, wherein, first clock signal input terminal CLKA represents, second clock signal input part CLKB represents, shift signal input end IN represents, shift signal output terminal NEXT represents, drive output GOUT represents, reset terminal XRESET represents.
It should be noted that, in order to ensure the normal work of vertical transfer register, in the clock period of second clock signal high level a clock period of duration and the first clock signal in duration of high level identical, in the clock period of second clock signal, in the clock period of low level duration and the first clock signal, the low level duration is identical, in the clock period of second clock signal, the duration of high level is less than the half of clock period, and the initial time of first of second clock signal high level postponed for 1/2nd clock period than the initial time of first high level of the first clock signal.Thus make:
Under the effect of the signal, the first clock signal and the second clock signal that export at the output terminal of IC chip, the drive output of the 1st grade of shift register cell exports high level in the duration that second clock signal exports the 1st high level;
Under the effect of the signal, the first clock signal and the second clock signal that export at the output terminal of IC chip, the drive output of i-th grade of shift register cell exports high level in the duration that second clock signal exports 2i-1 high level;
Under the effect of the signal, the first clock signal and the second clock signal that export at the output terminal of IC chip, drive output output high level in the duration that the first clock signal exports jth/2 high level of jth level shift register cell.
Preferably, in the present embodiment, the structure of the 1st grade of shift register cell can be as shown in Figure 7, comprise the first sub-reverser (can represent with INV1), the second sub-reverser (can represent with INV2), the first period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV1), the second period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV2), Sheffer stroke gate (can represent with NAND) and the 3rd sub-reverser (can represent with INV3), N1 point is reduction point, wherein:
The input end of the first sub-reverser INV1 is connected with the output terminal of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1, and be connected with the output terminal of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2, the output terminal of the first sub-reverser INV1 is shift signal output terminal, and is connected with the input end of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of the second sub-reverser INV2 is the first clock signal input terminal, be connected with providing the output terminal in the first clock signal source, the output terminal of the second sub-reverser INV2 is connected with the disable end of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1, and is connected with the Enable Pin of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is shift signal input end, is connected with the output terminal of IC chip, and the Enable Pin of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is connected with providing the output terminal in the first clock signal source;
The disable end of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2 is connected with providing the output terminal in the first clock signal source;
The first input end of Sheffer stroke gate NAND is second clock signal input part, is connected with providing the output terminal in second clock signal source, and the second input end is connected with the output terminal of the first sub-reverser INV1;
The 3rd sub-input end of reverser INV3 is connected with the output terminal of Sheffer stroke gate NAND, and the output terminal of the 3rd sub-reverser INV3 is drive output.
Preferably, in the present embodiment, the structure of jth level shift register cell can be as shown in Figure 8, comprise the first sub-reverser (can represent with INV1), second sub-reverser (can represent with INV2), first period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV1), second period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV2), the Thin Film Transistor (TFT) PTFT (can represent with MP) that Sheffer stroke gate (can represent with NAND) and the 3rd sub-reverser (can represent with INV3) and the signal for exporting shift signal output terminal reset, N1 point is reduction point, wherein:
The source class of PTFT is connected with the output terminal of the input end of the first reverser, the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 and the output terminal of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2, the grid of PTFT is reset terminal, be connected with the output terminal of reverser, the input end of reverser is connected with the output terminal of IC chip, and the drain electrode of PTFT connects given voltage source;
The output terminal of the first sub-reverser INV1 is shift signal output terminal, and is connected with the input end of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of the second sub-reverser INV2 is the first clock signal input terminal, be connected with providing the output terminal in second clock signal source, the output terminal of the second sub-reverser INV2 is connected with the disable end of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1, and is connected with the Enable Pin of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is shift signal input end, is connected with the output terminal of IC chip, and the Enable Pin of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is connected with providing the output terminal in the first clock signal source;
The disable end of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2 is connected with providing the output terminal in the first clock signal source;
The first input end of Sheffer stroke gate NAND is second clock signal input part, is connected with providing the output terminal in the first clock signal source, and second input end of Sheffer stroke gate NAND is connected with the output terminal of the first sub-reverser INV1;
The 3rd sub-input end of reverser INV3 is connected with the output terminal of Sheffer stroke gate NAND, and the output terminal of the 3rd sub-reverser INV3 is drive output.
Preferably, in the present embodiment, the structure of i-th grade of shift register cell can as shown in Figure 9 (can be identical with the structure of jth level shift register cell), comprise the first sub-reverser (can represent with INV1), second sub-reverser (can represent with INV2), first period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV1), second period of the day from 11 p.m. to 1 a.m clock reverser (can represent with CKINV2), the Thin Film Transistor (TFT) PTFT (can represent with MP) that Sheffer stroke gate (can represent with NAND) and the 3rd sub-reverser (can represent with INV3) and the signal for exporting shift signal output terminal reset, N1 point is reduction point, wherein:
The source class of PTFT is connected with the output terminal of the input end of the first reverser, the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 and the output terminal of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2, the grid of PTFT is reset terminal, be connected with the output terminal of reverser, the input end of reverser is connected with the output terminal of IC chip, and the drain electrode of PTFT connects given voltage source;
The output terminal of the first sub-reverser INV1 is shift signal output terminal, and is connected with the input end of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of the second sub-reverser INV2 is the first clock signal input terminal, the input end of the second sub-reverser INV2 is connected with providing the output terminal in the first clock signal source, the output terminal of the second sub-reverser INV2 is connected with the disable end of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1, and is connected with the Enable Pin of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2;
The input end of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is shift signal input end, is connected with the output terminal of IC chip, and the Enable Pin of the first period of the day from 11 p.m. to 1 a.m clock reverser CKINV1 is connected with providing the output terminal in the first clock signal source;
The disable end of the second period of the day from 11 p.m. to 1 a.m clock reverser CKINV2 is connected with providing the output terminal in the first clock signal source;
The first input end of Sheffer stroke gate NAND is second clock signal input part, and the first input end of Sheffer stroke gate NAND is connected with providing the output terminal in second clock signal source, and second input end of Sheffer stroke gate NAND is connected with the output terminal of the first sub-reverser INV1;
The 3rd sub-input end of reverser INV3 is connected with the output terminal of Sheffer stroke gate NAND, and the output terminal of the 3rd sub-reverser INV3 is drive output.
Below by embodiment two, the method controlling the vertical transfer register that embodiment one provides is described.
Embodiment two,
The embodiment of the present invention two provides a kind of control method of vertical transfer register, controls, comprising the vertical transfer register that embodiment one provides:
The control signal exported by the output terminal of IC chip inputs the shift signal input end of the 1st grade of shift register cell as initial shift signal, and the signal of this control signal after is oppositely inputted the reset terminal of the 2nd grade of shift register cell to every grade of shift register cell in N level shift register cell as reset signal.
In the method, if the 1st grade of shift register cell employing structure as shown in Figure 7, jth level shift register cell adopts structure as shown in Figure 8, i-th grade of shift register cell employing structure as shown in Figure 9, the sequential relationship of control signal (can represent with S & R), the control signal signal (can represent with xS & R) after oppositely, the first clock signal (can represent with CLK1), second clock signal (can represent with CLK2) can be as shown in Figure 10.In control signal, the initial time of high level is prior to the initial time of first high level in the first clock signal; The finish time of control signal high level is later than the finish time of first high level in the first clock signal, prior to the initial time of second high level in the first clock signal, and prior to the initial time of first high level in second clock signal.When control signal provides initial shift signal (control signal is that high level is effective) to the 1st grade of shift register cell of VSR, the signal of control signal after oppositely provides reset signal (control signal is Low level effective) to the 2nd grade of shift register cell to the every one-level shift register cell in N level shift register cell of VSR, the N1 point of 2nd grade of shift register cell to the every one-level shift register cell in N level shift register cell is resetted, make the 2nd grade of shift register cell to the shift signal output terminal determination output low level of the every one-level shift register cell in N level shift register cell.And the shift signal output terminal of the 1st grade of shift register cell is when the first clock signal exports first high level, just can determines to export high level, the 1st grade of shift register cell also can normally be worked without the need to reset circuit.Thus achieve and provide reset signal and initial shift signal to VSR by signal wire simultaneously.In Fig. 10, comprise 4 grades of shift register cells of cascade successively for vertical transfer register, give the sequential relationship of signal that every grade of vertical transfer register shift signal output terminal exports and the signal that drive output exports and control signal, the first clock signal, second clock signal.
Further, based on the vertical transfer register that the embodiment of the present invention one provides, the embodiment of the present invention can also provide a kind of IC chip, and the output terminal of described IC chip connects the vertical transfer register as embodiment one provides, and provides control signal to described vertical transfer register.
Further, based on the vertical transfer register that the embodiment of the present invention one provides, the embodiment of the present invention can also provide a kind of TFT panel, and described TFT panel comprises the vertical transfer register as embodiment one provides.
Although described the preferred embodiment of the application, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the application's scope.
Obviously, those skilled in the art can carry out various change and modification to the application and not depart from the spirit and scope of the application.Like this, if these amendments of the application and modification belong within the scope of the application's claim and equivalent technologies thereof, then the application is also intended to comprise these change and modification.
Claims (10)
1. a vertical transfer register, is characterized in that, described vertical transfer register comprises the N level shift register cell from the 1st grade of shift register cell to N level shift register cell successively cascade, described N be greater than 1 positive integer, wherein:
The shift signal input end of the 1st grade of shift register cell is connected with the output terminal of IC chip by control line;
2nd grade of shift register cell is to the every one-level shift register cell in N level shift register cell, and reset terminal is connected with the output terminal of reverser, and the input end of reverser is connected with the output terminal of IC chip by described control line.
2. vertical transfer register as claimed in claim 1, is characterized in that,
First clock signal input terminal of described 1st grade of shift register cell receives the first clock signal, and second clock signal input part receives second clock signal;
Described 2nd grade of shift register cell is to i-th grade of shift register cell in N level shift register cell, the shift signal input end of each i-th grade of shift register cell is connected with the shift signal output terminal of the i-th-1 grade shift register cell, first clock signal input terminal receives the first clock signal, second clock signal input part receives second clock signal, wherein, i is greater than the odd number that 1 is not more than N;
Described 2nd grade of shift register cell is to the jth level shift register cell in N level shift register cell, the shift signal output terminal of shift signal input end and jth-1 grade of shift register cell of each jth level shift register cell is connected, first clock signal input terminal receives second clock signal, second clock signal input part receives the first clock signal, wherein, j is greater than the even number that 1 is not more than N.
3. vertical transfer register as claimed in claim 2, is characterized in that,
Under the effect of the signal, the first clock signal and the second clock signal that export at the output terminal of IC chip, the drive output of the 1st grade of shift register cell exports high level in the duration that second clock signal exports the 1st high level;
Under the effect of the signal, the first clock signal and the second clock signal that export at the output terminal of IC chip, the drive output of i-th grade of shift register cell exports high level in the duration that second clock signal exports 2i-1 high level;
Under the effect of the signal, the first clock signal and the second clock signal that export at the output terminal of IC chip, drive output output high level in the duration that the first clock signal exports jth/2 high level of jth level shift register cell;
Wherein, in the clock period of second clock signal high level a clock period of duration and the first clock signal in duration of high level identical, in the clock period of second clock signal, in the clock period of low level duration and the first clock signal, the low level duration is identical, in the clock period of second clock signal, the duration of high level is less than the half of clock period, and the initial time of first of second clock signal high level postponed for 1/2nd clock period than the initial time of first high level of the first clock signal.
4. vertical transfer register as claimed in claim 2 or claim 3, it is characterized in that, 1st grade of shift register cell comprises the first sub-reverser, the second sub-reverser, the first period of the day from 11 p.m. to 1 a.m clock reverser, the second period of the day from 11 p.m. to 1 a.m clock reverser, Sheffer stroke gate and the 3rd sub-reverser, wherein:
The input end of the first sub-reverser is connected with the output terminal of the first period of the day from 11 p.m. to 1 a.m clock reverser, and is connected with the output terminal of the second period of the day from 11 p.m. to 1 a.m clock reverser, and the output terminal of the first sub-reverser is shift signal output terminal, and is connected with the input end of the second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of the second sub-reverser is the first clock signal input terminal, be connected with providing the output terminal in the first clock signal source, the output terminal of the second sub-reverser is connected with the disable end of the first period of the day from 11 p.m. to 1 a.m clock reverser, and is connected with the Enable Pin of the second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of the first period of the day from 11 p.m. to 1 a.m clock reverser is shift signal input end, is connected with the output terminal of IC chip, and the Enable Pin of the first period of the day from 11 p.m. to 1 a.m clock reverser is connected with providing the output terminal in the first clock signal source;
The disable end of the second period of the day from 11 p.m. to 1 a.m clock reverser is connected with providing the output terminal in the first clock signal source;
The first input end of Sheffer stroke gate is second clock signal input part, and be connected with providing the output terminal in second clock signal source, the second input end is connected with the output terminal of the first sub-reverser;
The input end of the 3rd sub-reverser is connected with the output terminal of Sheffer stroke gate, and the output terminal of the 3rd sub-reverser is drive output.
5. vertical transfer register as claimed in claim 2 or claim 3, it is characterized in that, jth level shift register cell, comprise the Thin Film Transistor (TFT) PTFT that the first sub-reverser, the second sub-reverser, the first period of the day from 11 p.m. to 1 a.m clock reverser, the second period of the day from 11 p.m. to 1 a.m clock reverser, Sheffer stroke gate, the 3rd sub-reverser and the signal for exporting shift signal output terminal reset, wherein:
The source class of PTFT is connected with the output terminal of the input end of the first reverser, the first period of the day from 11 p.m. to 1 a.m clock reverser and the output terminal of the second period of the day from 11 p.m. to 1 a.m clock reverser, the grid of PTFT is reset terminal, be connected with the output terminal of reverser, the input end of reverser is connected with the output terminal of IC chip, and the drain electrode of PTFT connects given voltage source;
The output terminal of the first sub-reverser is shift signal output terminal, and is connected with the input end of the second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of the second sub-reverser is the first clock signal input terminal, be connected with providing the output terminal in second clock signal source, the output terminal of the second sub-reverser is connected with the disable end of the first period of the day from 11 p.m. to 1 a.m clock reverser, and is connected with the Enable Pin of the second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of the first period of the day from 11 p.m. to 1 a.m clock reverser is shift signal input end, is connected with the output terminal of IC chip, and the Enable Pin of the first period of the day from 11 p.m. to 1 a.m clock reverser is connected with providing the output terminal in the first clock signal source;
The disable end of the second period of the day from 11 p.m. to 1 a.m clock reverser is connected with providing the output terminal in the first clock signal source;
The first input end of Sheffer stroke gate is second clock signal input part, is connected with providing the output terminal in the first clock signal source, and the second input end of Sheffer stroke gate is connected with the output terminal of the first sub-reverser;
The input end of the 3rd sub-reverser is connected with the output terminal of Sheffer stroke gate, and the output terminal of the 3rd sub-reverser is drive output.
6. vertical transfer register as claimed in claim 2 or claim 3, it is characterized in that, i-th grade of shift register cell, comprise the Thin Film Transistor (TFT) PTFT that the first sub-reverser, the second sub-reverser, the first period of the day from 11 p.m. to 1 a.m clock reverser, the second period of the day from 11 p.m. to 1 a.m clock reverser, Sheffer stroke gate, the 3rd sub-reverser and the signal for exporting shift signal output terminal reset, wherein:
The source class of PTFT is connected with the output terminal of the input end of the first reverser, the first period of the day from 11 p.m. to 1 a.m clock reverser and the output terminal of the second period of the day from 11 p.m. to 1 a.m clock reverser, the grid of PTFT is reset terminal, be connected with the output terminal of reverser, the input end of reverser is connected with the output terminal of IC chip, and the drain electrode of PTFT connects given voltage source;
The output terminal of the first sub-reverser is shift signal output terminal, and is connected with the input end of the second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of the second sub-reverser is the first clock signal input terminal, the input end of the second sub-reverser is connected with providing the output terminal in the first clock signal source, the output terminal of the second sub-reverser is connected with the disable end of the first period of the day from 11 p.m. to 1 a.m clock reverser, and is connected with the Enable Pin of the second period of the day from 11 p.m. to 1 a.m clock reverser;
The input end of the first period of the day from 11 p.m. to 1 a.m clock reverser is shift signal input end, is connected with the output terminal of IC chip, and the Enable Pin of the first period of the day from 11 p.m. to 1 a.m clock reverser is connected with providing the output terminal in the first clock signal source;
The disable end of the second period of the day from 11 p.m. to 1 a.m clock reverser is connected with providing the output terminal in the first clock signal source;
The first input end of Sheffer stroke gate is second clock signal input part, and the first input end of Sheffer stroke gate is connected with providing the output terminal in second clock signal source, and the second input end of Sheffer stroke gate is connected with the output terminal of the first sub-reverser;
The input end of the 3rd sub-reverser is connected with the output terminal of Sheffer stroke gate, and the output terminal of the 3rd sub-reverser is drive output.
7., to the method that the vertical transfer register as described in as arbitrary in claim 1 ~ 6 controls, it is characterized in that, described method comprises:
The control signal exported by the output terminal of IC chip inputs the shift signal input end of the 1st grade of shift register cell as initial shift signal, and the signal of this control signal after is oppositely inputted the reset terminal of the 2nd grade of shift register cell to every grade of shift register cell in N level shift register cell as reset signal.
8. method as claimed in claim 7, is characterized in that,
In control signal, the initial time of high level is prior to the initial time of first high level in the first clock signal;
The finish time of control signal high level is later than the finish time of first high level in the first clock signal, prior to the initial time of second high level in the first clock signal, and prior to the initial time of first high level in second clock signal.
9. an IC chip, is characterized in that, the output terminal of described IC chip connect as arbitrary in claim 1 ~ 6 as described in vertical transfer register, provide control signal to described vertical transfer register.
10. a Thin Film Transistor (TFT) TFT panel, is characterized in that, described TFT panel comprise as arbitrary in claim 1 ~ 6 as described in vertical transfer register.
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| CN104464817B (en) * | 2014-12-05 | 2018-06-15 | 深圳市华星光电技术有限公司 | Liquid crystal display device and its shift register |
| CN104537994B (en) * | 2014-12-30 | 2017-04-12 | 深圳市华星光电技术有限公司 | GOA drive circuit applied to flat panel display and flat panel display |
| CN104537995A (en) * | 2014-12-30 | 2015-04-22 | 深圳市华星光电技术有限公司 | Gate drive circuit and shift register |
| CN105244003B (en) * | 2015-11-12 | 2018-01-09 | 深圳市华星光电技术有限公司 | Gate driving circuit and shift register circuit |
| CN106504696B (en) * | 2016-12-29 | 2018-12-14 | 上海天马有机发光显示技术有限公司 | Display panel and display device comprising it |
| CN110322845B (en) | 2018-03-29 | 2021-08-20 | 瀚宇彩晶股份有限公司 | Gate Drive Circuits and Display Panels |
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