CN103268145B - For the method preserving the virtual address of access instruction - Google Patents
For the method preserving the virtual address of access instruction Download PDFInfo
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- CN103268145B CN103268145B CN201310072202.2A CN201310072202A CN103268145B CN 103268145 B CN103268145 B CN 103268145B CN 201310072202 A CN201310072202 A CN 201310072202A CN 103268145 B CN103268145 B CN 103268145B
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Abstract
A kind of method that the invention provides virtual address for preserving access instruction, described method includes: be provided for preserving the field of oldest exception access instruction information in access queue；When there being new exception access instruction to enter access queue, it is saved in the preceding exception in position access instruction information in program sequence；When receiving exception bus, by the described field zero setting being used for preserving oldest exception access instruction information.Described oldest exception access instruction refers to streamline Program sequence exception access instruction up front.Owing to the present invention has only to the multinomial virtual address in the virtual address of the oldest instruction that exception occurs in save routine sequence rather than program sequence, therefore it is greatly saved hardware resource, also reduces the power consumption of processor simultaneously.
Description
Technical field
The present invention relates to field of microprocessors, more particularly relate to preserve the void of access instruction
The method intending address.
Background technology
Out-of order processor performs instruction out of sequence, then according to program sequence submits (Commit) to
Instruction.The order that in program sequence, i.e. program, the instruction of regulation performs, although out-of order processor is
Perform instruction out of sequence, but instruction must be submitted to according to program sequence, process exception with guarantee
Or can return to accurately when interrupting occur to continue executing with at the instruction of exception or interruption.Generally will
Streamline Program sequence access instruction up front is defined as oldest access instruction.
Instruct when Out-of-order execution and likely can make an exception, now submit to queue to submit in order
Need to empty streamline during to exception instruction, then branch to exception handler and go to perform.
When the instruction that exception occurs is that (peek and number storage order, refer to access instruction with Load and Store
Order represents) time, exception handler is it is to be appreciated that the virtual address of this access instruction, such as Intel
X86 processor occur access instruction exception time can exception access instruction address be put into cr2
Depositor allows exception handler process, thus involve how to preserve out-of order processor
The problem of the virtual address of the middle access instruction that exception occurs.
Existing method is the virtual address of all access instruction to be saved in access queue, when
When access instruction occurs exception, the virtual address directly reading exception access instruction is given at exception
Reason circuit, but this method needs to preserve theirs for all of access instruction in access queue
Virtual address.
But, its virtual address can be converted into physics after searching TLB by access instruction
Cache and internal memory are removed to access in address, and now the virtual address of normal access instruction has not had
With, therefore, access instruction needs outside its virtual address in addition to exceptional, normal memory access
Instruction is the virtual address that need not it, so, when the overwhelming majority, this preservation is all
Waste, both waste hardware circuit resource, also bring huge power consumption.
Be disclosed in that the information of this background of invention technology segment is merely intended to deepen to the present invention is general
The understanding of background technology, and be not construed as recognizing or implying this information structure in any form
Prior art the most known to those skilled in the art.
Summary of the invention
It is an object of the invention to provide the side of a kind of virtual address for preserving access instruction
Method, can save hardware resource and to reduce power consumption.
To achieve these goals, the invention provides a kind of for preserving the virtual of access instruction
The method of address, described method includes: is provided for preserving oldest exception in access queue and visits
Deposit the field of command information；When there being new exception access instruction to enter access queue, it is saved in
The preceding exception in position access instruction information in program sequence；When receiving exception bus, by institute
State the field zero setting of information for preserving oldest exception access instruction.
Preferably, the field of described exception access instruction information includes: exception significance bit, exception
Position in program sequence of the virtual address of access instruction, oldest exception access instruction and old practice
The basic block number at outer access instruction place.
Preferably, the initial value of the field of described oldest exception access instruction information is zero.
Preferably, described method also includes when there is transfer instruction conjecture mistake, by described turn
The basic block number of the basic block number and described oldest exception access instruction place that move instruction place is carried out
Relatively, if the basic block number at described transfer instruction place is in described oldest exception access instruction institute
Basic block number before, then by the field zero setting of described oldest exception access instruction information；No
Then, the content keeping oldest exception access instruction information in described field is constant.
Preferably, by using comparator by the basic block number at described transfer instruction place with described
The basic block number at oldest exception access instruction place compares.
Preferably, the step of the preceding exception in position access instruction information in program sequence it is saved in described in
Suddenly include: by described new exception access instruction position in program sequence and described oldest exception
Access instruction position in program sequence compares, if described new exception access instruction exists
Position in program sequence before the position of described oldest exception access instruction, then use described newly
Exception access instruction information cover original described oldest exception access instruction information；No
Then, the content keeping oldest exception access instruction information in described field is constant.
Preferably, by using comparator by described new exception access instruction in program sequence
Position compares with described oldest exception access instruction position in program sequence.
Owing to the present invention has only to the instruction occurring to make an exception oldest in save routine sequence virtually
Location, and unlike original technology needs to preserve the virtual address of multinomial instruction, save hundreds of
Depositor and the hardware logic of corresponding reading-writing port and depositor keep power consumption, the most greatly
Save hardware resource, also reduce the power consumption of processor simultaneously.
By include in accompanying drawing herein and subsequently together with accompanying drawing for some of the present invention is described
The detailed description of the invention of principle, further feature and advantage that the method for the present invention is had will become
Understand or more specifically illustrated.
Accompanying drawing explanation
By with reference to below in conjunction with the accompanying drawing detailed description to the embodiment of the present invention, the present invention's is upper
State purpose, advantage and feature to will become clear from, wherein:
Fig. 1 shows the virtual address for preserving access instruction according to embodiments of the present invention
The flow chart of method；
Fig. 2 shows the letter for preserving oldest exception access instruction according to embodiments of the present invention
The field of breath；
Fig. 3 shows the letter for preserving oldest exception access instruction according to embodiments of the present invention
The structural representation of breath.
Fig. 4 shows that cancellation transfer after branch prediction failure according to embodiments of the present invention refers to
The structural representation of order instruction below.
Detailed description of the invention
Will be detailed with reference to various embodiments of the present invention, its example shows at accompanying drawing and hereafter retouches
In stating.Although describing the present invention in conjunction with exemplary embodiment, it is to be understood that this specification
It is not intended to limit the invention to these exemplary embodiments.On the contrary, the present invention is not intended only to
Cover these exemplary embodiments, and cover to be included in and be defined by the appended claims
Various substitutes, amendment, equivalent and other embodiments in the spirit and scope of the invention.
A kind of method that the invention provides virtual address for preserving access instruction, it is only necessary to
The virtual address of the instruction that exception occurs oldest in save routine sequence, reaches to be greatly saved
Hardware resource and reduce the purpose of power consumption of processor.
Because it is also that follow procedure sequence generates exception bus signals that the instruction of exception occurs, and
Exception bus can empty whole streamline, therefore the information of access instruction of exception occurs below also
Nonsensical.Based on this, the method for the present invention only preserves oldest in streamline exception
The virtual address of access instruction, first arrange one in order to preserve in streamline at access queue
The virtual address of the oldest access instruction that exception occurs, enters memory access when there being new access instruction
During queue, with the comparison that the access instruction preserved carries out program sequence, see the program of which bar instruction
Sequence above, is then saved in the virtual address of that access instruction above, so can protect
Demonstrate,proving per moment all preserves the virtual address of access instruction oldest in streamline.When access instruction is sent out
During raw exception, then give Exception handling circuit the virtual address that this is oldest, be greatly saved
Hardware resource, also reduces the power consumption of processor simultaneously.
The method of the described virtual address for preserving access instruction includes: set in access queue
Putting the field for preserving oldest exception access instruction information, the initial value of described field is 0；When
When having new exception access instruction to enter access queue, it is saved in the preceding example in position in program sequence
Outer memory access command information；When receiving exception bus, described being used for is preserved oldest exception visit
Deposit the field zero setting of the information of instruction.
Wherein, the field of the exception access instruction information for preserving oldest exception includes: exception
Significance bit valid, it represents that this access instruction there occurs exception；The void of oldest exception access instruction
Intend address vaddr；Oldest exception access instruction position robid in program sequence；Oldest exception
The basic block bbid at access instruction place, it is used for out-of order processor after branch prediction failure
Cancel transfer instruction instruction below to re-execute.
Described it be saved in the step of the preceding exception in position access instruction information in program sequence and include:
By described new exception access instruction position in program sequence and described oldest exception access instruction
Position in program sequence compares, if described new exception access instruction is in program sequence
Position before the position of described oldest exception access instruction, then use described new exception to visit
The information depositing instruction covers the information of original described oldest exception access instruction；Otherwise, keep
The content of the oldest exception access instruction information in described field is constant.Preferably, by using
Comparator is by described new exception access instruction position in program sequence and described oldest exception visit
Deposit instruction position in program sequence to compare.
The method of the described virtual address for preserving access instruction also includes when transfer instruction occurs
During conjecture mistake, the basic block number at described transfer instruction place is visited with the oldest exception preserved
The basic block number depositing instruction place compares, if the basic block number at described transfer instruction place
Before the basic block number at described oldest exception access instruction place, then described oldest exception is visited
Deposit the field zero setting of command information；Otherwise, the oldest exception access instruction in described field is kept
The content of information is constant.Preferably, by using comparator by the base at described transfer instruction place
This block number compares with the basic block number at described oldest exception access instruction place.
When receiving exception bus, owing to exception bus can empty whole streamline, because of hereafter
Face occurs the information of the access instruction of exception also can be cleared, and therefore, is preserved by described being used for
The field zero setting of the information of oldest exception access instruction.
Therefore, the method for the virtual address for preserving access instruction of the present invention only preserves oldest
There is the virtual address of the access instruction of exception, when submitting the access instruction that exception occurs to, only
Need to be sent to carry by virtual address vaddr of the oldest exception access instruction preserved in access queue
Hand over queue, allow submission queue send exception bus to empty whole streamline.
Accompanying drawing is below coordinated to illustrate embodiment of the present utility model.
Fig. 1 shows the virtual address for preserving access instruction according to embodiments of the present invention
The flow chart of method.As it is shown in figure 1, the method 100 of the virtual address for preserving access instruction
From the beginning of step 101, first, in access queue, it is provided for preserving oldest exception memory access refer to
Make the field of information.
Fig. 2 shows the letter for preserving oldest exception access instruction according to embodiments of the present invention
The field 200 of breath.The content of described field 200 includes: exception significance bit valid, and it represents
This access instruction there occurs exception；Virtual address vaddr of oldest exception access instruction；Old practice
Outer access instruction position robid in program sequence；The basic block at oldest exception access instruction place
Number bbid, it is canceled after transfer instruction after branch prediction failure for out-of order processor
Instruction re-executes.
Then in step 102, access queue receives the instruction of event.Contingent
Event include event 1, described event 1 indicate new exception access instruction enter access queue,
Event 2, described event 2 represents generation transfer instruction conjecture mistake and event 3, shown thing
Part 3, the expression of described event 3 receives exception bus.
If this event is for event 1, have new exception access instruction to enter access queue, then before
Proceed to step 103, in step 103, be saved in position preceding exception memory access in program sequence and refer to
Make information, i.e. judge that whether new exception access instruction position robid in program sequence is in institute
State before the position robid in program sequence of the oldest exception access instruction in field 200.
Fig. 3 shows the letter for preserving oldest exception access instruction according to embodiments of the present invention
The structural representation of breath.In figure 3, when there being new exception access instruction to enter access queue 305
Time, by comparator 303 by the robid in the information 302 of new exception access instruction and field
Robid in the information 301 of the oldest exception access instruction in 200 compares, if new
The value of the robid in the information 302 of exception access instruction is less than the information of oldest exception access instruction
Value (that is, the new exception access instruction position robid in program sequence of the robid in 301
Before the oldest exception access instruction in described field position robid in program sequence), then
Entering step 104, step 104 uses the information 302 of described new exception access instruction to cover word
The information 301 of the oldest exception access instruction in section 200；Otherwise, step 105 is entered, in step
By field 200 zero setting in rapid 105, will exception significance bit valid in field 200, oldest
Exception virtual address vaddr of access instruction, oldest exception access instruction position in program sequence
The basic block bbid at robid and oldest exception access instruction place is set to zero.
If this event is event 2, there is transfer instruction conjecture mistake, then advance to step 106,
Judge the basic block number at transfer instruction place whether oldest in field 200 in step 106
Before the basic block number at exception access instruction place.
Fig. 4 shows that cancellation transfer after branch prediction failure according to embodiments of the present invention refers to
The structural representation of order instruction below.In the diagram, when there is transfer instruction conjecture mistake
That is, transfer instruction enters access queue 405, by comparator 404 by the information of transfer instruction
Bbid in the 402 and bbid in the information 401 of the oldest exception access instruction in field 200
Compare, if the value of the bbid in the information of transfer instruction 402 is less than in field 200
Value (that is, the base at transfer instruction place of the bbid in the information 403 of oldest exception access instruction
Before the basic block number at this block number oldest exception access instruction place in field 200), then
Enter step 107 by field 200 zero setting；Otherwise, enter step 105 to keep in field 200
The information 401 of oldest exception access instruction constant.
If this event is for event 3, receive exception bus, then enter step 106 by field
200 zero setting.
Above for the purpose described and describe, present the certain exemplary embodiments of the present invention.
These exemplary embodiments are not exhaustive, or limit the invention to disclosed precise forms,
It is apparent that be all feasible according to many modifications and variations of above-mentioned teaching.Select and describe this
A little exemplary embodiments are to explain the certain principles of the present invention and actual application thereof, so that
Those skilled in the art manufacture and use each exemplary embodiment of the present invention, and various replace
For thing and amendment.In fact the scope of the present invention is limited by appending claims and equivalent thereof
Fixed.
Claims (4)
1. the method being used for preserving the virtual address of access instruction, it is characterised in that described
Method includes:
In access queue, it is provided for preserving the field of oldest exception access instruction information, described
The initial value of the field of oldest exception access instruction information is zero；
When there being new exception access instruction to enter access queue, it is saved in position in program sequence and exists
Front exception access instruction information；
When receiving exception bus, described being used for is preserved oldest exception access instruction information
Field zero setting；
Wherein, the field of described exception access instruction information includes: exception significance bit, exception are visited
Deposit the virtual address of instruction, the oldest exception access instruction position in program sequence and oldest exception
The basic block number at access instruction place；
Described method also includes, when there is transfer instruction conjecture mistake, by described transfer instruction
The basic block number at place compares with the basic block number at described oldest exception access instruction place,
If the basic block number at described transfer instruction place is at the base at described oldest exception access instruction place
Before this block number, then by the field zero setting of described oldest exception access instruction information；Otherwise, protect
The content holding oldest exception access instruction information in described field is constant.
The method of the virtual address for preserving access instruction the most according to claim 1,
It is characterized in that, by using comparator by the basic block number at described transfer instruction place with described
The basic block number at oldest exception access instruction place compares.
The method of the virtual address for preserving access instruction the most according to claim 1,
It is characterized in that, described in be saved in the step of the preceding exception in position access instruction information in program sequence
Suddenly include: by described new exception access instruction position in program sequence and described oldest exception
Access instruction position in program sequence compares, if described new exception access instruction exists
Position in program sequence before the position of described oldest exception access instruction, then use described newly
Exception access instruction information cover original described oldest exception access instruction information；Otherwise,
The content keeping oldest exception access instruction information in described field is constant.
The method of the virtual address for preserving access instruction the most according to claim 3,
It is characterized in that, by using comparator by described new exception access instruction in program sequence
Position compares with described oldest exception access instruction position in program sequence.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1410886A (en) * | 2001-09-27 | 2003-04-16 | 中国科学院计算技术研究所 | Treatment method of realizing access accuracy exception in command pipeline |
| CN101114218A (en) * | 2006-07-27 | 2008-01-30 | 中国科学院计算技术研究所 | A Depth-First Exception Handling Method in Complex Instruction Set Architecture |
| CN101826000A (en) * | 2010-01-29 | 2010-09-08 | 北京龙芯中科技术服务中心有限公司 | Interrupt response determining method, device and microprocessor core for pipeline microprocessor |
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| GB2369464B (en) * | 2000-11-27 | 2005-01-05 | Advanced Risc Mach Ltd | A data processing apparatus and method for saving return state |
| CN102819419B (en) * | 2012-07-25 | 2016-05-18 | 龙芯中科技术有限公司 | Stream information treatment system and device and method are carried out in instruction |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1410886A (en) * | 2001-09-27 | 2003-04-16 | 中国科学院计算技术研究所 | Treatment method of realizing access accuracy exception in command pipeline |
| CN101114218A (en) * | 2006-07-27 | 2008-01-30 | 中国科学院计算技术研究所 | A Depth-First Exception Handling Method in Complex Instruction Set Architecture |
| CN101826000A (en) * | 2010-01-29 | 2010-09-08 | 北京龙芯中科技术服务中心有限公司 | Interrupt response determining method, device and microprocessor core for pipeline microprocessor |
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