CN103257850A - Instruction cache memory based on access trace of zone bit - Google Patents

Abstract

The invention relates to an instruction cache memory (an instruction Cache) based on an access trace of a zone bit. The instruction cache memory comprises a trace information table, a trace information maintenance circuit and a control circuit, wherein the depth of the trace information table is equal to the line number of the instruction Cache, each line is used for storing a trace information bit which expresses whether the access trace of a corresponding line to a mark memorizer exists or not, the trace information maintenance circuit outputs an overflow control signal according to an input branch direction, an input branch target address, an instruction taking address and a program segment address range in the trace information maintenance circuit, the overflow control signal expresses whether the instruction taking address or the branch target address is in the program segment address range or not, and the control circuit is used for controlling the reading for the mark memorizer according to the trace information bit and conducting maintenance on the trace information table according to the overflow control signal. According to the instruction Cache, recorded mark bit access information is utilized to conduct hit detection on the instruction Cache in advance in a program executing process, unnecessary mark memorizer access is eliminated, and power consumption of the instruction Cache is effectively reduced.

Description

An Instruction Cache Memory Based on Flag Bit Access Trace

technical field

The invention relates to an instruction cache memory based on flag bit access trace.

Background technique

With the rapid development of semiconductor process technology, the performance and integration of embedded processor chips have been greatly improved, and the resulting power consumption problem has become increasingly serious. As an important part to bridge the speed gap between the processor core and the main memory, the instruction cache memory (instruction cache) consumes a lot of power because of its high access frequency. Therefore, effectively reducing the power consumption of the instruction cache is of great significance for the design of low-power embedded processors.

The structure of the traditional direct-mapped instruction cache is shown in Figure 1. It mainly consists of a tag memory, a data memory and a state. When the processor core accesses the instruction cache, the tag memory reads out the tag bit tag according to the index bit (Index) in the fetch address as the address, and compares it with the Tag bit in the fetch address: if the comparison result is equal, then Indicates a Cache hit, and the processor core directly reads the instruction from the data memory of the instruction Cache; if the comparison result is not equal, it indicates that the Cache is missing, and an operation of accessing the main memory will be initiated at this time. In the process of fetching instructions, the processor core needs to perform a large number of read flag memory operations and comparison operations, and these operations consume a lot of energy. If the times of accessing the flag memory can be reduced, the power consumption of the instruction cache can be effectively reduced.

At the Low-Power Electronics and Design (ISLPED) Conference on August 12-14, 2002, the article "A History-Based I-Cache for Low-Energy Multimedia Applications" published by KojiInoue et al. proposed a program-based execution A low-power instruction cache design method for historical information, which is closely combined with branch prediction technology. Its working principle is: if the branch target instruction has been executed, and there is no instruction cache miss between the execution of this branch target instruction and the last execution of this branch target instruction, then the access to the flag memory can be stopped.

However, the low-power instruction Cache design method based on program execution history information proposed by Koji Inoue et al. has the following disadvantages:

(1) This technology is closely combined with the branch target buffer. When the branch prediction and the update of the program execution history information occur at the same time, the processor pipeline will stall, resulting in a decrease in processor performance;

(2) When the instruction cache is missing, all the program execution history information needs to be cleared, resulting in the processor being unable to use the already recorded effective history information to eliminate unnecessary flag memory access during program execution, thereby reducing the program execution history. Efficiency in the use of information;

(3) For an embedded processor that does not use a branch prediction mechanism, building a branch predictor needs to increase a lot of hardware costs, and the branch predictor itself also needs to consume a part of energy.

Contents of the invention

The object of the present invention is to provide an instruction cache memory based on flag bit access trace which can solve the above defects.

The present invention provides an instruction cache memory accessing traces based on flag bits, including a trace information maintenance circuit, a trace information table, a control circuit, a flag memory, and a data memory, wherein: the number of rows of the trace information table is respectively the same as the The number of rows of the flag memory and the data memory is equal, and each row of the trace information table is used to store a trace information bit, and whether the trace information bit is valid or not indicates whether there is a corresponding row of the flag memory. Access trace; the trace information maintenance circuit is used to output an overflow control signal according to the input branch direction, branch target address, fetch address and program segment address range in the trace information maintenance circuit, and the effective of the overflow control signal Whether or not respectively indicates whether the instruction fetch address or the branch target address is within the address range of the program segment; the control circuit is used to control the reading of the flag memory according to the trace information bit, and use and maintaining the trace information table according to the overflow control signal.

Preferably, the trace information maintenance circuit includes: a control register for storing the segment head address and segment tail address of the program segment address range; a comparison unit for according to the branch direction, the branch target address, the Said instruction fetch address and said program segment address range output branch overflow signal, branch underflow signal and sequence underflow signal; OR gate, for outputting according to said branch overflow signal, branch underflow signal and sequence underflow signal The overflow control signal.

Preferably, the control registers include: a first register for storing the segment start address of the program segment address range; a second register for storing the segment end address of the program segment address range.

Preferably, the comparison unit includes: a first comparison unit, which outputs the branch overflow signal by comparing the branch target address with the segment head address; a second comparison unit, which outputs the branch overflow signal by comparing the branch The target address is compared with the segment end address to output the branch underflow signal; the third comparison unit compares the instruction fetch address with the segment end address to output the sequence underflow signal.

Preferably, the trace information bit is valid, and the control circuit is configured to: prohibit reading from the flag memory, and use the instruction fetch address to read instructions from the data memory.

Preferably, the overflow control signal is valid, and the control circuit is further configured to: clear the content in the trace information table when the branch overflow signal or the branch underflow signal is valid, and storing the branch target address in the first register as the segment head address, and simultaneously storing the sum of the branch target address and the capacity value of the instruction cache memory in the second register as the segment tail address In the register, the capacity value is expressed in bytes; when the sequence underflow signal is valid, clear the contents in the trace information table, and clear the first register and the second register zero.

Preferably, the branch direction is used to indicate whether the branch instruction is a backward branch instruction or a forward branch instruction. When the branch direction indicates that the branch instruction is a backward branch instruction, the first comparison unit works, and the The control circuit closes the third comparison unit; when the branch direction indicates that the branch instruction is a forward branch instruction, the second comparison unit works; when the branch direction indicates that the branch instruction is a forward branch instruction or the branch instruction is executed In case of failure, the control circuit activates the third comparison unit.

Preferably, the trace information bit is invalid, and the control circuit is further configured to: read an instruction from the data memory or the main memory and return it to the processor core; return the read instruction to the processor When the kernel is used, the trace information bit of the corresponding row in the trace information table is set to valid.

Preferably, the trace information bit is invalid, and the control circuit is further configured to: use the instruction fetch address to read the flag bit from the flag memory; judge the read flag bit from the instruction fetch address Whether the flag bits match; in the case of a match, use the instruction fetch address to read instructions from the corresponding row of the data memory; in the case of a mismatch, use the instruction fetch address to read from the main memory instruction, and write the read instruction into the corresponding row of the data memory.

Preferably, the control circuit is further configured to: read the trace information bit from the corresponding row of the trace information table according to the instruction fetch address to determine whether there is a corresponding row of the flag memory Access trail.

The instruction Cache based on the flag bit access trace of the present invention uses the recorded flag bit access trace information to perform hit detection on the instruction Cache in advance during program execution, eliminates unnecessary flag memory access, and effectively reduces the power consumption of the instruction Cache.

Description of drawings

Fig. 1 is a schematic structural diagram of a traditional instruction cache using direct mapping;

FIG. 2 is a schematic structural diagram of an instruction cache based on flag bit access traces according to an embodiment of the present invention;

Fig. 3 is the working flow diagram of the instruction cache based on the flag bit access trace according to an embodiment of the present invention; and

Fig. 4 is a schematic diagram of a specific instruction code.

Detailed ways

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

FIG. 2 is a schematic structural diagram of an instruction cache based on flag bit access traces according to an embodiment of the present invention.

Fig. 3 is a working flow chart of the instruction cache based on the flag bit access trace according to the embodiment of the present invention.

Next, with reference to FIG. 2 and FIG. 3 , the working principle of the instruction cache based on the access trace of the flag bit according to the embodiment of the present invention will be introduced.

As shown in Figure 2, the instruction Cache is mainly composed of trace information maintenance circuit, trace information table, flag memory, data memory and control circuit (not shown in the figure).

The trace information maintenance circuit mainly includes a control register, a comparison unit and an OR gate, which are used to accept the branch direction, branch target address, and instruction fetch address input by the processor core, and according to these inputs and the trace information in the maintenance circuit The address range of the program segment is used to output the overflow control signal, and whether the overflow control signal is valid or not indicates whether the input instruction fetch address or branch target address is within the address range of the program segment.

The control register includes a first register and a second register, which are respectively used to store the segment head address and the segment end address of the address range of the program segment. The comparing unit includes a first comparing unit, a second comparing unit and a third comparing unit. The first comparison unit compares the input branch target address with the segment header address in the first register, and outputs a branch underflow signal; the second comparison unit compares the input branch target address with the segment tail address in the second register, Outputting a branch underflow signal; the third comparison unit compares the input instruction fetch address with the end-of-segment address in the second register, and outputs a sequence underflow signal. The OR gate outputs an overflow control signal according to the branch overflow signal, the branch underflow signal and the sequential underflow signal.

The number of rows of the trace information table is equal to the row number of the flag memory and the row number of the data memory, and each row is used to store a trace information bit. The access trace of the corresponding row.

The control circuit is used for controlling the reading of the flag memory according to the trace information bit, and for maintaining the trace information table according to the overflow control signal. The control circuit can exist independently of each part in the instruction cache, and can also be integrated into the trace information maintenance circuit. Those skilled in the art should understand that there are various implementation methods of the control circuit used to implement the control function according to various control signals. Here, only the function of the control circuit is described without repeating its specific implementation, so as not to obscure the subject of the present invention.

In addition, the flag memory and the data memory are no different from the traditional instruction cache, and will not be repeated here.

Those skilled in the art should understand that for a direct mapping instruction cache with a capacity of N bytes, if a program segment whose first and last addresses are X and Y respectively in the main memory is already in the instruction cache and Y-X<N, then when fetching It means that when the address PC satisfies X≤PC<X+N, the instructions in this block will not be replaced.

The working process of the instruction cache according to the embodiment of the present invention will be described below with reference to the flowchart of FIG. 3 .

During program execution, when the first branch instruction is encountered, the trace information maintenance circuit will write the branch target address of the branch instruction as the first address of the segment into the first register of the control register, and simultaneously compare the branch target address with The sum of the capacity values of the instruction cache (the capacity of the cache is expressed in bytes) is written into the second register of the control register as the end address of the segment. A program segment address range is established through the segment head address and segment end address, which means that the program segment whose address is within the program segment address range is now started to be executed.

Since the branch instruction is executed for the first time, a cache miss occurs when the processor core reads the target instruction of the branch instruction, so that the target instruction of the branch instruction needs to be read from the main memory. When the target instruction of the branch instruction returned from the main memory is written into the instruction cache, the trace information bit of the corresponding row in the trace information table is set to be valid.

In the following program execution process, it is necessary to judge the input instruction fetch address, and adopt different processing methods according to the judgment result, as described below.

On the one hand, in the case where the instruction fetch address is within the address range of the program segment in the trace information maintenance circuit:

If the trace information bit read by the control circuit according to the index bit in the fetch address is valid (the disable signal is valid), it means that the instruction cache hits, and under the control of the control circuit, the processor core directly reads the instruction from the data memory There is no need to access the flag memory; if the trace information bit read by the control circuit according to the index bit in the fetch address is invalid (the disable signal is invalid), it is necessary to access the flag memory under the control of the control circuit to determine whether the instruction Cache hits .

In the case of invalid trace information bits: if the instruction Cache hits, the control circuit will read the instruction from the data memory, return the read instruction to the processor core and set the trace information bit of the corresponding row in the trace information table is valid; if the command cache is missing, the control circuit will read the command from the main memory, write the read command into the data memory and simultaneously set the trace information bit of the corresponding row in the trace information table to valid.

On the other hand, if the input fetch address is not within the address range of the program segment in the trace information maintenance circuit (in the case of overflow of the fetch address), it is necessary to control the first register and the second register under the control of the control circuit. Modify or clear, and clear the trace information table at the same time, to ensure that the program segment address range in the trace information maintenance circuit always maintains a correct correspondence with the trace information table.

In the process of program execution, there are the following three situations where the instruction fetch address overflow occurs:

First of all, those skilled in the art should understand that branch instructions include backward branch instructions and forward branch instructions: the branch offset sign bit of the backward branch instruction is negative, and its corresponding branch direction is "1"; the forward branch instruction The branch offset sign bit of is positive, and its corresponding branch direction is "0".

(1) The overflow of the instruction fetch address caused by the branch instruction occurs when a backward branch instruction is encountered and the branch target address of the backward branch instruction is smaller than the value of the first register (segment header address). When this happens, the branch overflow signal output by the first comparison unit is valid, and the overflow control signal output by the OR gate is valid. At this time, the control circuit clears the trace information table according to the effective overflow control signal, writes the branch target address of the backward branch instruction into the first register, and simultaneously writes the sum of the branch target address and the capacity value of the instruction Cache into into the second register.

(2) The underflow of the instruction fetch address caused by the branch instruction occurs when a forward branch instruction is encountered and the branch target address of the forward branch instruction is greater than or equal to the value of the second register (segment end address) . When this happens, the branch underflow signal output by the second comparison unit is valid, and the overflow control signal output by the OR gate is valid. At this time, the control circuit clears the trace information table according to the effective overflow control signal, writes the branch target address of the forward branch instruction into the first register, and simultaneously writes the sum of the branch target address and the capacity value of the instruction Cache into the second register.

(3) The underflow of the instruction fetch address caused by the sequential instruction occurs when a sequential instruction is encountered and the instruction fetch address of the sequential instruction is equal to the value of the second register. When this happens, the sequential underflow signal output by the third comparison unit is valid, and the overflow control signal output by the OR gate is valid. At this time, the control circuit clears the trace information table and clears the first register and the second register according to the effective overflow control signal. Next, when a branch instruction is encountered again, the branch target address of the branch instruction is written into the first register, and at the same time, the sum of the branch target address and the capacity value of the instruction cache is written into the second register.

According to the branch direction and the signal indicating whether the execution of the branch instruction is successful or not, the control circuit can control the first, second and third comparison units. Specifically, the first comparison unit works when executing a backward branch instruction, and the control circuit closes the third comparison unit when encountering a backward branch instruction; the second comparison unit works when executing a forward branch instruction; Indicating that the branch instruction is a forward branch instruction or in case the execution of the branch instruction fails, the third comparison unit is activated.

Fig. 4 is a schematic diagram of a specific instruction code.

The following describes the specific execution process of the instruction cache based on the flag access trace according to the embodiment of the present invention through the instruction code in FIG. 4 .

Assume that the instruction cache capacity is 8KB, the block size is 16B, and the direct mapping method is adopted. The depth of the trace information table is 512, which is equal to the number of lines of the instruction cache; the bit width of the trace information table is 1 bit, and its value "1" means that the trace information bit of the corresponding line is valid, and its value of "0" means the trace information bit of the corresponding line invalid. The specific instruction code is shown in Figure 4.

The initial values of the first register and the second register in the trace information maintenance circuit are both 0, and the initial value of the trace information table is all 0.

When the program executes to the branch instruction at 0x00000080, due to the value address overflow, the trace information maintenance circuit will write the branch target address 0x00000090 of the branch instruction into the first register, and at the same time combine the branch target address with the capacity value of the instruction cache The sum (0x00000090+0x2000=0x00002090) is written into the second register. The values of the first register and the second register are the segment head address and the segment end address respectively, which means that the program segment whose address is between 0x00000090 and 0x00002090 is started to be executed now. Since this branch instruction is executed for the first time, a cache miss will occur when the processor core reads the instruction at 0x00000090, and the control circuit reads the instruction from the main memory according to the instruction fetch address, and writes the instruction returned from the main memory to Enter the instruction Cache, and set the trace information bit of the corresponding row to 1. In the next instruction fetching process, if the trace information bit read according to the index bit in the instruction fetch address is 1, the control circuit closes the flag memory and reads the instruction directly from the data memory; If the trace information bit read by the index bit is 0, it is necessary to access the flag memory to determine whether the instruction Cache hits. If the instruction cache hits, the control circuit reads the instruction from the data memory, and the trace information bit of the corresponding line is set to 1 when the read instruction returns to the processor core; if the instruction cache misses, the control circuit reads the instruction from the main The instruction is read from the memory, and the read instruction is written into the instruction cache, and at the same time, the trace information bit of the corresponding row is set to 1.

When the program executes to the instruction at 0x00002090, the fetch address of the instruction is equal to the value of the second register. At this time, the sequence underflow signal output by the third comparison unit is 1, and the overflow control signal output by the OR gate is 1. The control circuit clears the trace information table according to the valid overflow control signal, and clears the first register and the second register to zero.

When the program executes to the branch instruction at 0x00002190, due to overflow of the instruction fetch address, the trace information maintenance circuit will write the branch target address 0x00004100 of the branch instruction into the first register, and at the same time combine the branch target address with the capacity value of the instruction cache The sum (0x00004100+0x2000=0x00006100) is written into the second register. In the next instruction fetching process, if the trace information bit read according to the index bit in the instruction fetch address is 1, the control circuit closes the flag memory and reads the instruction directly from the data memory; If the trace information bit read by the index bit is 0, it is necessary to access the flag memory to determine whether the instruction Cache hits. If the instruction cache hits, the control circuit reads the instruction from the data memory, and the trace information bit of the corresponding line is set to 1 when the read instruction returns to the processor core; if the instruction cache misses, the control circuit reads the instruction from the main The instruction is read from the memory, and the read instruction is written into the instruction cache, and at the same time, the trace information bit of the corresponding line is set to 1.

When the program executes to the branch instruction at 0x00004200, the branch target address 0x00006200 of the branch instruction is greater than the value of the second register. At this time, the branch underflow signal output by the second comparison unit is 1, and the overflow control signal output by the OR gate is 1. The control circuit clears the trace information table according to the effective overflow control signal, writes 0x00006200 into the first register, and simultaneously writes (0x00006200+0x2000=0x00008200) into the second register. In the next instruction fetching process, if the trace information bit read according to the index bit in the instruction fetch address is 1, the control circuit closes the flag memory and reads the instruction directly from the data memory; If the trace information bit read by the index bit is 0, it is necessary to access the flag memory to determine whether the instruction Cache hits. If the instruction cache hits, the control circuit reads the instruction from the data memory, and the trace information bit of the corresponding line is set to 1 when the read instruction returns to the processor core; if the instruction cache misses, the control circuit reads the instruction from the main The instruction is read from the memory, and the read instruction is written into the instruction cache, and at the same time, the trace information bit of the corresponding row is set to 1.

When the program executes to the branch instruction at 0x00006260, the branch target address 0x00004100 of the branch instruction is smaller than the value of the first register. At this time, the overflow signal output by the first comparison unit is 1, and the overflow control signal output by the OR gate is 1, and the control circuit clears the trace information table according to the effective overflow control signal, and writes 0x00004100 into the first register, and simultaneously (0x00004100+0x2000=0x00006100) is written into the second register. In the next instruction fetching process, if the trace information bit read according to the index bit in the instruction fetch address is 1, the control circuit closes the flag memory and reads the instruction directly from the data memory; If the trace information bit read by the index bit is 0, it is necessary to access the flag memory to determine whether the instruction Cache hits. If the instruction cache hits, the control circuit reads the instruction from the data memory, and the trace information bit of the corresponding line is set to 1 when the read instruction returns to the processor core; if the instruction cache misses, the control circuit reads the instruction from the main The instruction is read from the memory, and the read instruction is written into the instruction cache, and at the same time, the trace information bit of the corresponding row is set to 1. Next, when the instruction fetch address is not within the address range of the program segment in the trace information maintenance circuit, the control circuit clears the trace information table according to the overflow control signal, and modifies the values of the first register and the second register to ensure that the trace information Maintain a correct correspondence between the program segment address range in the maintenance circuit and the trace information table.

From the above example, it can be found that the present invention uses the trace information bit to perform hit detection on the instruction cache in advance, reducing unnecessary flag memory access, thereby effectively reducing the power consumption of the instruction cache.

Professionals should further realize that the units and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the relationship between hardware and software Interchangeability. In the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (10)

1. A kind of instruction cache memory based on flag bit access trace, comprises trace information maintenance circuit, trace information table, control circuit, flag memory and data memory, wherein: The number of rows of the trace information table is respectively equal to the number of rows of the flag memory and the data memory, and each row of the trace information table is used to store a trace information bit, and the validity of the trace information bit is respectively Indicates whether there is an access trace to the corresponding row of the flag memory; The trace information maintenance circuit is used to output the overflow control signal according to the input branch direction, branch target address, instruction fetch address and program segment address range in the trace information maintenance circuit, and whether the overflow control signal is valid or not is respectively Indicates whether the instruction fetch address or the branch target address is within the address range of the program segment; A control circuit, configured to control reading of the flag memory according to the trace information bit, and to maintain the trace information table according to the overflow control signal. 2. The instruction cache based on the flag bit access trace according to claim 1, wherein the trace information maintenance circuit comprises: The control register is used to store the segment head address and segment tail address of the address range of the program segment; a comparison unit, configured to output a branch overflow signal, a branch underflow signal and a sequence underflow signal according to the branch direction, the branch target address, the instruction fetch address and the address range of the program segment; The OR gate is used for outputting the overflow control signal according to the branch overflow signal, the branch underflow signal and the sequence underflow signal. 3. The instruction cache based on the flag bit access trace according to claim 2, wherein the control register comprises: The first register is used to store the segment head address of the address range of the program segment; The second register is used for storing the end address of the address range of the program segment. 4. The instruction cache memory based on the flag bit access trace according to claim 2, wherein the comparison unit comprises: a first comparison unit that outputs the branch overflow signal by comparing the branch target address with the segment head address; a second comparison unit that outputs the branch underflow signal by comparing the branch target address with the segment tail address; A third comparing unit, which compares the instruction fetch address with the end-of-segment address, and outputs the sequence underflow signal. 5. The instruction cache based on flag bit access trace according to claim 1, wherein the trace information bit is effective, and the control circuit is configured to: Reading of the flag memory is prohibited, and an instruction is read from the data memory by using the instruction fetch address. 6. The instruction cache memory based on the flag bit access trace according to claim 2, wherein the overflow control signal is effective, and the control circuit is also configured to: When the branch overflow signal or the branch underflow signal is valid, clear the content in the trace information table, and store the branch target address in the first register as the segment header address , simultaneously storing the sum of the branch target address and the capacity value of the instruction cache memory as the segment tail address into the second register, the capacity value expressed in bytes; When the sequential underflow signal is valid, clear the content in the trace information table, and clear the first register and the second register to zero. 7. The instruction cache memory based on the flag bit access trace according to claim 4, wherein the branch direction is used to indicate whether the branch instruction is a backward branch instruction or a forward branch instruction, When the branch direction indicates that the branch instruction is a backward branch instruction, the first comparison unit works, and the control circuit turns off the third comparison unit; In the case where the branch direction indicates that the branch instruction is a forward branch instruction, the second comparison unit works; If the branch direction indicates that the branch instruction is a forward branch instruction or the execution of the branch instruction fails, the control circuit activates the third comparison unit. 8. The instruction cache based on flag bit access trace according to claim 1, wherein the trace information bit is invalid, and the control circuit is further configured to: reading instructions from said data store or main memory and returning them to a processor core; When the read instruction is returned to the processor core, the trace information bit of the corresponding row in the trace information table is set to valid. 9. The instruction cache memory based on flag bit access trace according to claim 1, wherein the trace information bit is invalid, and the control circuit is further configured to: reading a flag bit from the flag memory by using the instruction fetch address; judging whether the flag bit read matches the flag bit in the fetch address; In the case of a match, using the instruction fetch address to read an instruction from a corresponding row of the data memory; In the case of a mismatch, an instruction is read from the main memory using the instruction fetch address, and the read instruction is written into a corresponding row of the data memory. 10. The instruction cache memory based on flag bit access trace according to claim 1, wherein the control circuit is further configured to: Reading the trace information bit from a corresponding row of the trace information table according to the instruction fetch address to determine whether there is an access trace to the corresponding row of the flag memory.

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