CN103249243A

CN103249243A - Circuit structure of circuit laminates

Info

Publication number: CN103249243A
Application number: CN2012100238769A
Authority: CN
Inventors: 徐润忠; 林祈明; 叶佐鸿; 陈亚详
Original assignee: Kinsus Interconnect Technology Corp
Current assignee: Kinsus Interconnect Technology Corp
Priority date: 2012-02-03
Filing date: 2012-02-03
Publication date: 2013-08-14

Abstract

A circuit structure of a circuit laminate, the circuit structure comprising: the nano-plating layer is a flat plating layer with the thickness of 5-40 nm and is formed on the outer surface of the circuit metal layer, the circuit metal layer and the nano-plating layer can be formed on the preformed plate at first, then the substrate and the preformed plate with the circuit metal layer and the nano-plating layer are pressed together, finally the preformed plate is removed, and the circuit structure of the circuit layer and the nano-plating layer embedded in the substrate is formed.

Description

The line construction of circuit laminated plates

Technical field

The present invention relates to a kind of line construction of circuit laminated plates, especially utilize the chemical bonded refractory power of nanometer coating layer and cover layer or substrate to improve the interface effect, do not need circuit layer on surface of metal roughening.

Background technology

With reference to figure 1, the generalized section of the line construction of prior art circuit laminated plates.The line construction 1 of prior art circuit laminated plates comprises substrate 10, circuit metal level 20 and cover layer 30.The upper surface of substrate 10 is a rough surface; circuit metal level 20 is formed on the upper surface of substrate 10; usually by copper, aluminium, silver, gold one of them is made at least; cover layer 30 is for cohering glue or welding resisting layer; circuit metal level 20 is covered; because circuit metal level 20 is different with the material of cover layer 30; for fear of delamination; usually the surface of circuit metal level 20 can be utilized mode roughenings such as chemistry, machinery or electricity slurry; increase skin-friction coefficient; and improve interfacial property, and make outer surface 25 form a rough surface.

Yet, prior art has some shortcomings with the surface roughening of circuit metal level 20, when making circuit metal level 20, for the surface roughening with circuit metal level 20, need to reserve width usually, with the compensation width that roughening was reduced, yet present line density is more and more higher, feasible limited tangible restriction in design, therefore, need a kind of line build-out that reduces to increase line construction and the manufacture method of line density.

Summary of the invention

Main purpose of the present invention provides a kind of line construction of circuit laminated plates, and this line construction comprises: a substrate, the upper surface of this substrate are a rough surface; One circuit metal level is formed on the upper surface of this substrate; One nanometer coating layer, be formed on the outer surface of this circuit metal level, thickness with 5～40nm, and after this nanometer coating layer forms, the roughness of this outer surface is Ra＜0.35 μ m, Rz＜3 μ m, and the outer surface of this circuit metal level and this nanometer coating layer are a tabular surface, can't be under 1000 times of light microscopes inspect with section and judge roughness; And a cover layer, be to cohere glue or a welding resisting layer, this circuit metal level and this nanometer coating layer are covered.

Main purpose of the present invention provides a kind of line construction of circuit laminated plates, this line construction comprises: a substrate, have a plurality of die cavitys, one nanometer coating layer, be arranged in the hole wall of described die cavity of this substrate, have the thickness of 5～40nm, and the roughness of this nanometer plating be Ra＜0.35 μ m, Rz＜3 μ m, and this nanometer coating layer is a tabular surface, can't be under 1000 times of light microscopes inspects with section and judges roughness; An and circuit metal level, be formed in the described die cavity of this substrate, and be positioned on this nanometer coating layer, form an embedded line construction, wherein a surface of this circuit metal level exposes at the upper surface of this substrate, and be positioned at same level with the upper surface of this substrate, the upper surface that makes substrate is that roughness levels off to a smooth surface of zero, surface roughness Ra＜0.35 μ m for example, Rz＜0.3 μ m, above-mentioned line construction is earlier circuit metal level and nanometer coating layer to be formed on the preformed board, with substrate and the preformed board pressing with circuit metal level and nanometer coating layer, at last preformed board is removed and formed again.

The line construction of circuit laminated plates of the present invention, chemical bonded refractory power by nanometer coating layer and cover layer or substrate, and significantly improved the interface effect, and improved existing in order to improve the interface effect with circuit layer on surface of metal roughening, carry out the side effect of dimension compensation and need to reserve line width, because the surfacing of the line construction of circuit laminated plates of the present invention, do not need to reserve line width and carry out dimension compensation, can increase line density, can be at the more intensive circuit of the making of same area.

Description of drawings

Fig. 1 is the generalized section of the line construction of prior art circuit laminated plates.

Fig. 2 is the generalized section of line construction first embodiment of circuit laminated plates of the present invention.

Fig. 3 is the generalized section of line construction second embodiment of circuit laminated plates of the present invention.

Embodiment

Following conjunction with figs. is done more detailed description to embodiments of the present invention, so that those skilled in the art can implement after studying this specification carefully according to this.

With reference to figure 2, the generalized section of line construction first embodiment of circuit laminated plates of the present invention.As shown in Figure 2, the line construction 2 of circuit laminated plates of the present invention comprises substrate 10, circuit metal level 20, nanometer coating layer 40 and cover layer 30.Substrate 10 by FR4 glass fibre or bismaleimides-cyanate resin (namely, the BT resin) made, the upper surface of substrate 10 is a rough surface, circuit metal level 20 is formed on the upper surface of substrate 10, usually by copper, aluminium, silver, gold one of them is made at least, nanometer coating layer 40 is formed on the outer surface of circuit metal level 20, thickness with 5～40nm, by copper, tin, aluminium, nickel, silver, at least two kinds of gold are made, and roughness is Ra＜0.35 μ m, Rz＜3 μ m, the outer surface of nanometer coating layer 40 and circuit metal level 20 is a tabular surface, can't be under 1000 times of light microscopes inspects with section and judges roughness.Cover layer 30 covers circuit metal level 20 and Nanoalloy coating layer 40 for cohering glue or welding resisting layer (that is, green lacquer).

Wherein, circuit metal level 20 is to form by traditional image transfer mode, nanometer coating layer 40 is to utilize electroless plating (namely, chemical plating), evaporation, sputter or ald (Atomic Layer Deposition, ALD) mode is formed on the outer surface of circuit metal level 20, circuit metal level 20 is formed have the structure on three smooth surfaces.

With reference to figure 3, the generalized section of line construction second embodiment of circuit laminated plates of the present invention.As shown in Figure 3, the line construction 3 of circuit laminated plates of the present invention comprises substrate 10, circuit metal level 20 and nanometer coating layer 40, nanometer coating layer 40 is arranged in the hole wall of die cavity 12 of substrate 10, circuit metal level 20 is formed in the die cavity 12 of substrate 10, and be positioned on the nanometer coating layer 40, form an embedded line construction, one surface of circuit metal level 20 exposes at the upper surface of substrate 10, and be positioned at same level with the upper surface of substrate 10, and the upper surface that makes substrate 10 is a smooth surface, surface roughness Ra＜0.35 μ m, Rz＜3 μ m, and can't be under 1000 times of light microscopes inspect with section and judge roughness.

The line construction 3 of second embodiment of the invention circuit laminated plates is the production method that utilizes similar first embodiment, earlier circuit metal level 20 and nanometer coating layer 40 are formed on the preformed board 100, again with substrate 10 and preformed board 100 pressings with circuit metal level 20 and nanometer coating layer 40, at last preformed board 100 is removed and formed, preformed board 100 can be Ra＜0.35 μ m for roughness, Rz＜3 μ m, and can't be under 1000 times of light microscopes inspect with section and judge roughness, preformed board 100 can be for having the polished surface metallic plate, for example, steel plate, aluminium sheet, copper coin etc., or comprise the insulated substrate of the metal level of polishing, the FR4 substrate that for example comprises the copper layer of polishing, or comprise the BT substrate etc. of aluminium lamination, at this only as example, as restriction.So can make circuit metal level 20 form the structure with smooth surface, four sides.

The line construction of circuit laminated plates of the present invention, by the chemical bonded refractory power of nanometer coating layer 40 with cover layer 30 or substrate 10, and significantly improved the interface effect, and improved existing in order to improve the interface effect with circuit metal level 20 surface roughenings, carry out the side effect of dimension compensation and need to reserve line width, because the surfacing of the line construction of circuit laminated plates of the present invention, do not need to reserve line width and carry out dimension compensation, can increase line density, can be at the more intensive circuit of the making of same area.

The above person only is in order to explain preferred embodiment of the present invention, be not that attempt is done any pro forma restriction to the present invention according to this, therefore, all have in that identical invention spirit is following do relevant any modification of the present invention or change, all must be included in the category of claim of the present invention.

Claims

1. A circuit structure of a circuit laminate, characterized in that, the circuit structure of the circuit laminate comprises:

A substrate, an upper surface of the substrate is a rough surface;

a circuit metal layer formed on the upper surface of the substrate;

A nano-coating layer, formed on the outer surface of the circuit metal layer, has a thickness of 5-40 nm, and a roughness of Ra<0.35 μm and Rz<3 μm; and

A covering layer, which is an adhesive or a solder resist layer, covers the circuit metal layer and the nano-plating layer,

The roughness of the outer surface of the circuit metal layer and the nano-coating layer cannot be judged by section inspection under a 1000 times optical microscope.

2. the circuit structure of circuit laminates as claimed in claim 1, is characterized in that, this substrate is made of FR4 glass fiber or bismaleimide-triazine resin, and this circuit metal layer is made of copper, aluminum , silver, and gold, and the nano-coating layer is made of at least two of copper, tin, aluminum, nickel, silver, and gold.

3. The circuit structure of the circuit laminate according to claim 1, wherein the nano-coating layer is formed on the outside of the circuit metal layer by means of electroless plating, evaporation, sputtering or atomic layer deposition. surface.

4. A circuit structure of a circuit laminate, characterized in that the circuit structure of the circuit laminate comprises:

A substrate with multiple mold cavities;

A nano-coating layer, disposed in the hole wall of the mold cavity of the substrate, has a thickness of 5-40 nm, and has a roughness of Ra<0.35 μm and Rz<3 μm; and

a circuit metal layer formed in the mold cavity of the substrate and located on the nano-plating layer to form an embedded circuit structure,

Wherein one surface of the circuit metal layer is exposed on the upper surface of the substrate and is at the same level as the upper surface of the substrate, so that the upper surface of the substrate is smooth with a surface roughness of Ra<0.35 μm and Rz<3 μm The roughness of the surface, the nano-plated layer, the upper surface of the substrate and the surface of the circuit metal layer cannot be judged by section inspection under a 1000 times optical microscope.

5. the circuit structure of circuit laminates as claimed in claim 4, is characterized in that, this substrate is made of FR4 glass fiber or bismaleimide-triazine resin, and this circuit metal layer is made of copper, aluminum , silver, and gold, and the nano-coating layer is made of at least two of copper, tin, aluminum, nickel, silver, and gold.

6. The circuit structure of the circuit laminated board as claimed in claim 4, wherein the circuit metal layer is formed on a preformed board in an image transfer mode, and the nano-coating layer is formed by electroless plating, vapor deposition, Sputtering or atomic layer deposition is formed on the outer surface of the circuit metal layer, and then the substrate is pressed with the preformed plate with the circuit metal layer and the nano-coating layer, and finally the preformed plate is removed And the embedded circuit structure is formed.

7. The circuit structure of the circuit laminated board according to claim 5, wherein the preformed board has a surface roughness of Ra<0.35 μm and Rz<3 μm, and the surface of the preformed substrate is examined under a 1000 times optical microscope The roughness cannot be judged by cross-sectional inspection, and the preformed plate is a metal plate with a polished surface or an insulating substrate with a polished metal layer.

8. The circuit structure of the circuit laminate as claimed in claim 7, wherein the metal plate is a steel plate, an aluminum plate, or a copper plate, the polished metal layer is a copper layer or an aluminum layer, and the insulating substrate is made of FR4 glass fiber or It is made of bismaleimide-triazine resin.