CN103229158A - Control circuit and control method for inter-integrated circuit bus - Google Patents

Abstract

The present invention relates to an I2C bus control circuit and a control method. The circuit includes: an I2C master device and a plurality of I2C device groups; the I2C device group includes an I2C driver device and a plurality of I2C slave devices; the I2C interface of the I2C master device is connected to the I2C driver device ; Its IO interface is connected to the enable end of the I2C drive device; one end of the I2C drive device is connected to multiple I2C slave devices; the I2C master device sends an enable signal to the I2C drive device; To send data, the I2C driver device processes the data and sends it to each I2C slave device; if the device address of the I2C slave device is the same as the address code, the I2C slave device communicates with the I2C master device. Therefore, the present invention realizes that the I2C master device controls the opening or closing state of each I2C driver, and improves the reliability of the I2C bus control circuit.

Description

Internal integrated circuit bus control circuit and control method

technical field

The invention relates to the communication field, in particular to an internal integrated circuit bus control circuit and a control method.

Background technique

The Inter-Integrated Circuit (I2C) bus is one of the most widely used serial buses in today's electronic design. It is mainly used for voltage and temperature monitoring, and electrically erasable programmable read-only memory, EEPROM) data reading and writing, optical module management, etc. Wherein, multiple I2C devices can be connected to one I2C bus.

In the prior art, when there are too many devices on the I2C bus, an I2C driver is often used to enhance the driving capability of the I2C bus. Each I2C device has a unique device address, and its length is generally 7 bits. The first 4 bits of the I2C device address are determined by the type of the I2C device. For example, the first 4 bits of the EEPROM device address are 1010, the first 4 bits of the temperature sensor device address are 1001, and the input/output (Input/Output, I/O ) The first 4 bits of the device address of the interface device are 0100; the last 3 bits of the I2C device address are generally realized by setting the high and low levels of the address pins A2, A1, and A0 of the I2C device. For example, there are 4 EEPROM devices on the I2C bus whose device addresses are 1010100, 1010101, 1010110, and 1010111 respectively. Among them, the last 3 bits of the device address of each EEPROM device are pulled up by connecting the address pins A2, A1, and A0 of the device. Resistor or pull-down resistor to control the high and low state of A2, A1, A0.

However, if the pull-up resistors or pull-down resistors connected to the address pins A2, A1, and A0 fail, the device address of the I2C device will change, and may conflict with device addresses of other I2C devices. When the I2C master device operates to read and write the I2C device, other I2C devices that conflict with the device address of the I2C device will also respond to the operation of the I2C master device, thereby causing the I2C master device to read and write data conflicts, reducing the I2C bus control. circuit reliability.

Contents of the invention

The present invention provides an I2C bus control circuit and control method, which solves the problem in the prior art that when the I2C master device operates to read and write the I2C device, other devices that conflict with the device address of the device will also respond to the I2C master device. operation, thus causing the I2C main device to read and write data conflicts, using the input/output interface of the I2C main device to control the enable terminal of the I2C driver, thereby realizing the I2C main device to control the open or close state of each I2C driver, and improving This ensures the reliability of the I2C bus control circuit.

In a first aspect, the present invention provides an I2C bus control circuit, the circuit includes: an I2C master device, a plurality of I2C device groups; the I2C device group includes an I2C driver device and a plurality of I2C slave devices; the I2C The I2C interface of the main device is connected to the first end of each I2C driving device in the plurality of I2C device groups; the input and output IO interfaces assigned by the I2C main device to each I2C driving device are respectively connected to the corresponding The enabling end of the I2C driving device is connected; the second end of each I2C driving device is connected to a plurality of I2C slave devices in the I2C device group where each I2C driving device is located; when the When the I2C master device needs to communicate with the I2C slave device of any one of the I2C device groups, the I2C master device distributes the input and output IO interface for the I2C driver device of the I2C device group to the I2C The driving device sends an enable signal so that the I2C driving device is in an enabled state; the I2C master device sends data to the I2C driving device in the enabled state through the I2C interface of the I2C master device, and the enabled state The I2C driver device processes the data, and sends the processed data to each of the I2C slave devices in the I2C device group; each of the I2C slave devices communicates its own device address with the processed The address code in the subsequent data is compared, and if the device address of the I2C slave device is the same as the address code, the I2C slave device communicates with the I2C master device.

In a first possible implementation manner of the first aspect, each I2C slave device in the plurality of I2C device groups is of a different type.

With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner, each I2C slave device in the I2C device group has a 7-bit device address, and the device addresses are different.

In combination with the first aspect, the first possible implementation of the first aspect, or the second possible implementation of the first aspect, in a third possible implementation, the I2C master device is specifically configured to provide The I2C driving device of any one of the multiple I2C device groups sends an enabling signal, so that the I2C driving device is in an enabled state; the I2C driving devices of other I2C device groups are in an off state.

In a second aspect, the present invention provides an I2C bus control method, the method comprising: when the I2C master device needs to communicate with any of the I2C slave devices of the I2C device group, through the I2C The main device sends an enabling signal to the I2C driving device for the input and output IO interface assigned to the I2C driving device of the I2C device group, so that the I2C driving device is in an enabled state; the I2C main device passes through the The I2C interface of the I2C master device sends data to the I2C driver device in the enabled state, and the I2C driver device in the enabled state processes the data and sends the processed data to the I2C device group Each of the I2C slave devices sends; when each of the I2C slave devices compares its own device address with the address code in the processed data, if the device address of the I2C slave device is consistent with the address The code is the same, and the I2C slave device communicates with the I2C master device.

In a first possible implementation manner of the second aspect, the sending an enabling signal to the I2C driving device of the I2C device group so that the I2C driving device is in an enabled state is specifically: through the I2C The master device sends an enabling signal to the I2C driving device for the input/output I/O interface assigned to the driving device of the I2C device group, so that the I2C driving device is in an enabled state; when the I2C driving device When the low-level trigger is enabled, the I2C master device sets the input and output IO interface corresponding to the drive device to a low level, and the enable end of the I2C drive device is also low, so that The I2C driving device is in an enabled state; when the high level trigger of the I2C driving device is enabled, the I2C master device sets the input and output IO interface corresponding to the driving device to a high level, and the The enabling terminal of the I2C driving device is also at a high level, so that the I2C driving device is in an enabled state.

With reference to the second aspect or the first possible implementation of the second aspect, in a second possible implementation, the sending an enable signal to the I2C driving device of the I2C device group, so that the I2C The enabling state of the driving device further includes: the I2C master device controlling the I2C driving devices of other I2C device groups other than the I2C device group where the I2C driving device in the enabled state is in the off state.

With reference to the second aspect or the first possible implementation manner of the second aspect, in a third possible implementation manner, level conversion and buffering are performed on the data.

By applying the above-mentioned I2C bus control circuit and I2C bus control method, the input and output interfaces of the I2C master device are used to control the enable end of the I2C driver, so that the I2C master device controls the on or off state of each I2C driver, improving the performance of the I2C master device. The reliability of the I2C bus control circuit.

Description of drawings

FIG. 1 is a schematic diagram of an I2C bus control circuit provided by Embodiment 1 of the present invention;

FIG. 2 is a flow chart of an I2C bus control method provided by Embodiment 2 of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

The I2C bus control circuit and control method provided by the embodiments of the present invention send an enabling signal to the I2C driving device through the input and output IO interface assigned by the I2C master device to the I2C driving device of the I2C device group, so that the I2C driving device is in an enabled state, While other I2C driving devices are in the off state, they send data to the I2C driving device in the enabled state through the I2C interface of the I2C master device. After the I2C driving device in the enabled state processes the data, it sends the processed data to the I2C device group. Each different type of I2C slave device sends; after each I2C slave device receives the processed data, it compares the device address of the I2C slave device with the address code in the processed data; when the device address of the I2C slave device and When the address codes are the same, the I2C slave device communicates with the I2C master device, thereby realizing the isolation of the I2C master device and the I2C slave device by using the I2C drive device, improving the driving capability of the I2C bus, and realizing the use of One IO interface controls the enable terminal of one I2C driving device, and one I2C driving device drives different kinds of I2C slave devices, thereby greatly improving the reliability of the I2C bus control circuit.

FIG. 1 is a schematic diagram of an I2C bus control circuit provided by Embodiment 1 of the present invention. As shown in the figure, the embodiment of the present invention specifically includes: an I2C master device 11 and a plurality of I2C device groups 12 . Wherein, each I2C device group includes an I2C driving device and a plurality of I2C slave devices. Wherein, the types of the respective I2C slave devices in each I2C device group 12 are different. Each I2C slave device has a 7-bit device address, which is different from each other. For example, the first 4 bits of some slave devices represent the type of the I2C slave device, and the first 4 bits of the device address of each I2C slave device in the same I2C device group 12 are different.

Taking the I2C device group 12 where the I2C driving device 121 is located as an example to illustrate the composition of the I2C device group 12, the I2C device group 12 includes: an I2C driving device 121 and a number of I2C slave devices. The a I2C slaves are respectively I2C slave 11, I2C slave 12, I2C slave 13, . . . and I2C slave 1a. In addition, the composition of the rest of the I2C device group 12 is the same as that of the I2C device group 12 where the I2C driving device 1 is located, and will not be repeated here.

In the I2C device group 12 where the I2C driving device 121 is located, the types of the I2C slave device 11, the I2C slave device 12, the I2C slave device 13, ... and the I2C slave device 1a are different, that is, the I2C slave device 11, the I2C slave device 12 , I2C slave 13, ... and the first 4 bits of the device address of the I2C slave 1a are different. However, the I2C slave devices between different I2C device groups 12 may be the same. For example, the I2C slave device 11 , the I2C slave device 21 , the I2C slave device 31 , . . . , the I2C slave device 31 may all be EEPROM devices.

First, the I2C bus controls the connection relationship between various parts of the circuit.

The I2C interface of the I2C master device is connected to the first end 1 of the I2C driving device in each I2C device group 12, that is, the first end 1 of the I2C driving device 121, the I2C driving device 122, the I2C driving device 123, ..., the I2C driving device 12n. 1-phase connection at one end. Wherein, the I2C interface specifically includes two signal lines: a bidirectional data line SDA and a clock line SCL. In addition, between the I2C interface of the I2C master device and the I2C driving device in each I2C device group 12 further includes: an I2C bus resistor R13.

The I2C master device allocates an input/output I/O interface for each I2C driver device in the I2C device group 12, that is, the I2C driver device 121, the I2C driver device 122, the I2C driver device 123, ..., the I2C driver device 12n, And the I2C main device is an I2C driving device 121, an I2C driving device 122, an I2C driving device 123, ..., and the input and output IO interfaces allocated by the I2C driving device 12n are respectively the I2C driving device 121, the I2C driving device 122, the I2C driving device 123, . . . and the enable terminal EN of the I2C driving device 12n is connected. In FIG. 1, the I2C main device IO_1 interface is connected to the enabling terminal EN of the I2C driving device 121, the I2C main device IO_2 interface is connected to the enabling terminal EN of the I2C driving device 122, and the I2C main device IO_3 interface is connected to the I2C driving device. The enable terminal EN of 123 is connected, and the I2C master device IO_4 interface is connected with the enable terminal EN of the I2C driving device 12n. In addition, the I2C master device may also allocate other IO interfaces to the I2C driving device 121 , the I2C driving device 122 , the I2C driving device 123 and the I2C driving device 12n. In the embodiment of the present invention, as long as it is ensured that the enabling terminal EN of the I2C driving device in each I2C device group 12 is connected to an IO interface, and is connected with the enabling terminal EN of the I2C driving device in each I2C device group 12 The connected IO interfaces are all different, so that the I2C master device can use its IO interface to control the on or off state of the I2C driving device in each I2C device group 12 respectively.

The second end 2 of the I2C driving device in each I2C device group 12 is connected to one end of each I2C slave device in the I2C device group 12 . The I2C device group 12 where the I2C driving device 121 is located is taken as an example to illustrate the internal connections of the I2C device group 12 . The output terminals 2 of the I2C driving device 121 are all connected to one end of the I2C slave device 11 , the I2C slave device 12 , the I2C slave device 13 , . . . and the I2C slave device 1a.

Second, the I2C bus controls the functions of various parts of the circuit.

When the I2C master device 11 needs to communicate with the I2C slave device of any I2C device group 12, the input and output IO interface allocated by the I2C master device 11 for the driver device of the I2C device group 12 sends an enabling signal to the I2C driver device, so that The I2C driver device is enabled.

The I2C master device sends data to the I2C driver device in the enabled state through the I2C interface of the I2C master device, and the I2C driver device in the enabled state processes the data and sends the processed data to each I2C slave device in the I2C device group. Wherein, the I2C driving device processes data including level shifting and buffering.

When each I2C slave receives the processed data, it compares the address code in the processed data with its own device address; only when the device address of the I2C slave is the same as the received address code, the I2C slave The device communicates with the I2C master.

The function of each part of the I2C bus control circuit will be specifically described below by taking the I2C master device 11 needing to communicate with the I2C slave device 11 in the I2C device group 12 where the I2C driving device 121 is located as an example.

First, the I2C master device 11 sends an enabling signal to the I2C driving device 121 through the IO_1 interface connected to the enabling terminal EN of the I2C driving device 121, so that the I2C driving device is in an enabled state. But the I2C driving devices in the other I2C device group 12 , the I2C driving device 121 , the I2C driving device 122 , the I2C driving device 123 , . . . , the I2C driving device 12n are in the off state. In the embodiment of the present invention, the I2C master device 11 can only send an enabling signal to one I2C driving device, and cannot send enabling signals to more than two I2C driving devices at the same time. That is to say, only one I2C driving device receiving the enable signal is in the enabled state, while other I2C driving devices are in the off state.

When the I2C driving device 121 is enabled with a low-level trigger, the I2C master device 11 sets the input and output IO interface corresponding to the I2C driving device 121, that is, the IO_1 interface, to a low level, and the enabling terminal of the I2C driving device 121 is also Low level, so that the I2C driving device 121 is in an enabled state; when the I2C driving device 121 is triggered by a high level to enable, the I2C master device sets the input and output IO interface corresponding to the driving device, that is, IO_1, to If the level is high, the enable terminal of the I2C driving device 121 is also at a high level, so that the I2C driving device 121 is in an enabled state.

Then, the I2C master device 11 sends data to the I2C driver device 121 in the enabled state through the I2C interface of the I2C master device. The data includes an address code. After the I2C driver device in the enabled state processes the data, the processed data is sent To each of the I2C slaves connected to the output of the I2C driver, ie I2C slave 11, I2C slave 12, I2C slave 13, . . . and I2C slave 1a.

Finally, when each I2C slave device, that is, I2C slave device 11, I2C slave device 12, I2C slave device 13, ... and I2C slave device 1a receives the processed data, the address code in the processed data Compare with own device address. When the device address of one of the I2C slave devices is the same as the address code, the I2C slave device communicates with the I2C master device. For example, if the device address of the I2C slave device 11 is the same as the received address code, the I2C master device performs a read operation or a write operation on the I2C slave device 11 .

In addition, when the I2C master device 11 needs to communicate with other I2C slave devices in the I2C device group 12, the I2C master device 11 needs to communicate with the I2C slave device 11 in the I2C device group 12 where the I2C driver device 121 is located. It is roughly the same, except that the IO of the I2C driving device is different, so I won’t repeat them here.

Therefore, the internal integrated circuit I2C bus control circuit provided by the embodiment of the present invention sends an enabling signal to the I2C driving device through the I2C master device for the input and output IO interface allocated by the I2C driving device of the I2C device group, so that the I2C driving device is enabled state, while other I2C driving devices are in the off state, send data to the I2C driving device in the enabled state through the I2C interface of the I2C master device, and after the I2C driving device in the enabled state processes the data, it sends the processed data to the I2C device Each different type of I2C slave device in the group sends; after each I2C slave device receives the processed data, it compares the device address of the I2C slave device with the address code in the processed data; when the device of the I2C slave device When the address is the same as the address code, the I2C slave device communicates with the I2C master device, thereby realizing the isolation of the I2C master device and the I2C slave device by using the I2C driver device, improving the driving capability of the I2C bus, and realizing In order to use one IO interface to control the enabling terminal of one I2C driving device, and one I2C driving device drives different kinds of I2C slave devices, thereby greatly improving the reliability of the I2C bus control circuit.

FIG. 2 is a flow chart of an I2C bus control method provided by Embodiment 2 of the present invention. This method is used in the I2C bus control circuit provided in Embodiment 1 of the present invention. As shown in the figure, the embodiment of the present invention specifically includes:

Step 210, when the I2C master device needs to communicate with any I2C slave device of the I2C device group, the I2C master device sends an enable signal to the I2C driver device through the input and output IO interface allocated by the I2C master device for the I2C driver device of the I2C device group, Make the I2C drive device in an enabled state. The I2C driving devices of other I2C device groups other than the I2C device group are in the off state.

Specifically, an enable signal is sent to the I2C drive device through the input and output IO interface assigned by the I2C master device to the drive device of the I2C device group, so that the I2C drive device is in an enabled state;

When the low-level trigger of the I2C drive device is enabled, the I2C master device will set the input and output IO interfaces corresponding to the drive device to low level, and the enable terminal of the I2C drive device will also be low level, so that the I2C drive The device is in the enable state; when the I2C drive device triggers the enable at a high level, the I2C master device sets the input and output IO interface corresponding to the drive device to a high level, and the enable terminal of the I2C drive device is also at a high level. Level, so that the I2C drive device is enabled.

Step 220, the I2C master device sends data to the I2C driver device in the enabled state through the I2C interface of the I2C master device, and after the I2C driver device in the enabled state processes the data, it sends the processed data to each I2C driver device in the I2C device group. sent from the device. Wherein, the types of each I2C slave device are different. Wherein, the processing of the data by the I2C driving device specifically includes level conversion and buffering of the data.

Specifically, each I2C slave device has a 7-bit device address, and the device addresses of each I2C slave device belonging to the same I2C slave device group are different. For example, the first 4 bits of the device address of each I2C slave device represent the type of the I2C slave device, and the first 4 bits of the device address of each I2C slave device belonging to the same I2C device group are different.

Step 230, after each I2C slave device receives the processed data, after comparing the device address of each I2C slave device with the address code in the processed data, if the device address of the I2C slave device is the same as the address code , the I2C slave communicates with the I2C master.

Therefore, the internal integrated circuit I2C bus control method provided by the embodiment of the present invention sends an enabling signal to the I2C driving device through the input and output IO interface allocated by the I2C master device to the I2C driving device of the I2C device group, so that the I2C driving device is enabled state, while other I2C driving devices are in the off state, send data to the I2C driving device in the enabled state through the I2C interface of the I2C master device, and after the I2C driving device in the enabled state processes the data, it sends the processed data to the I2C device Each different type of I2C slave device in the group sends; after each I2C slave device receives the processed data, it compares the device address of the I2C slave device with the address code in the processed data; when the device of the I2C slave device When the address is the same as the address code, the I2C slave device communicates with the I2C master device, thereby realizing the isolation of the I2C master device and the I2C slave device by using the I2C driver device, improving the driving capability of the I2C bus, and realizing In order to use one IO interface to control the enabling terminal of one I2C driving device, and one I2C driving device drives different kinds of I2C slave devices, thereby greatly improving the reliability of the I2C bus control circuit.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the scope of the technical solution of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (10)

1. A kind of internal integrated circuit I2C bus control circuit, it is characterized in that, described circuit comprises: I2C master device, a plurality of I2C device groups; Described I2C device group comprises I2C driving device and a plurality of I2C slave devices; The I2C interface of the I2C main device is connected to the first end of each I2C driving device in the plurality of I2C device groups; the input and output IO interfaces assigned by the I2C main device to each I2C driving device are respectively connected to The enabling end of the corresponding I2C driving device is connected; The second end of each I2C driving device is connected to a plurality of I2C slave devices in the I2C device group where each I2C driving device is located; When the I2C master device needs to communicate with the I2C slave device of any one of the I2C device groups, the input and output IO interface assigned to the I2C driver device of the I2C device group by the I2C master device is sent to The I2C driving device sends an enable signal, so that the I2C driving device is in an enabled state; The I2C main device sends data to the I2C driving device in the enabled state through the I2C interface of the I2C main device, and the I2C driving device in the enabled state processes the data, and the processed data sending to each of the I2C slave devices in the I2C device group; Each of the I2C slave devices compares its own device address with the address code in the processed data, and if the device address of the I2C slave device is the same as the address code, the I2C slave device is identical to the address code. The I2C master communicates. 2 . The I2C control circuit according to claim 1 , wherein the types of each I2C slave device in the plurality of I2C device groups are different. 3. The I2C control circuit according to claim 2, wherein each I2C slave device in the I2C device group has a 7-bit device address, and the device addresses are different. 4. The I2C control circuit according to any one of claims 1 to 3, wherein the I2C master device is specifically used to drive the I2C device to any I2C device group in the plurality of I2C device groups An enabling signal is sent to make the I2C driving device in an enabled state; the I2C driving devices of other I2C device groups are in an off state. 5. An internal integrated circuit I2C bus control method is characterized in that, the method comprises: When the I2C master device needs to communicate with the I2C slave device of any one of the I2C device groups, the input and output IO interface assigned to the I2C driver device of the I2C device group by the I2C master device is sent to The I2C driving device sends an enable signal, so that the I2C driving device is in an enabled state; The I2C main device sends data to the I2C driving device in the enabled state through the I2C interface of the I2C main device, and the I2C driving device in the enabled state processes the data and sends the processed sending data to each of the I2C slave devices in the I2C device group; After each I2C slave device compares its own device address with the address code in the processed data, if the device address of the I2C slave device is the same as the address code, the I2C slave device and The I2C master communicates. 6. The I2C bus control method according to claim 5, wherein the sending an enable signal to the I2C driver device of the I2C device group so that the I2C driver device is in an enabled state is specifically: sending an enabling signal to the I2C driving device through the input/output I/O interface assigned by the I2C master device to the driving device of the I2C device group, so that the I2C driving device is in an enabled state; When the low-level trigger of the I2C driving device is enabled, the I2C master device sets the input and output IO interface corresponding to the driving device to a low level, and the enabling terminal of the I2C driving device is also low level, so that the I2C driving device is in an enabled state; when the I2C driving device is enabled with a high level trigger, the I2C master device sets the input and output IO interface corresponding to the driving device to If the level is high, the enabling terminal of the I2C driving device is also at high level, so that the I2C driving device is in an enabled state. 7. The I2C bus control method according to claim 5 or 6, characterized in that, sending an enable signal to the I2C driver device of the I2C device group, so that the I2C driver device is in an enabled state or not include: The I2C master device controls the I2C driving devices of other I2C device groups other than the I2C device group in which the enabled I2C driving device is located to be in an off state. 8. The I2C bus control method according to claim 5 or 6, wherein the I2C drive device in the enable state processes the data as follows: The data is level shifted and buffered. 9. The I2C control method according to claim 5 or 6, wherein each I2C slave device in the I2C device group is of a different type. 10. The I2C control method according to claim 9, wherein each I2C slave device in the I2C device group has a 7-bit device address, and the device addresses are different.

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