CN103226526A - Memorizer access control device - Google Patents
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Abstract
The invention discloses a memorizer access control device for connecting a plurality of first memorizers and a plurality of second memorizers. The memorizer access control device comprises a plurality of access request generation modules, a plurality of access request execution modules and a plurality of arbitration selection modules, wherein each arbitration selection module comprises an ID sizer, an arbiter, a first multi-way selector and a second multi-way selector; the ID sizers receive access request signals from the access request generation modules, screen valid access request signals, send the valid access request signals to the arbiters for arbitration treatment to generate a priority-contained arbitration result, and finally form a plurality of two-way data transmission channels among the access request execution modules, the arbitration selection modules and the access request generation modules according to the arbitration result. According to the memorizer access control device, the ID sizers screen valid access request signals, and respond to high-priority access request signals according to the arbitration result of the arbiters, so that scramble of data for a system bus is reduced, and high-speed two-way transmission of data is realized.
Description
Technical field
The present invention relates to technical field of data storage, relate in particular to a kind of memory access control apparatus that between volatile memory and nonvolatile memory, carries out Data Transmission Controlling.
Background technology
Replace the mechanical type hard disk gradually based on the NAND of flash memory (Flash Memory) technology and becoming the storage medium of Large Volume Data.It has nearly 100,000 times the access life-span, has advantages such as size is little, anti-seismic performance is good simultaneously.
Data among the NAND are that unit carries out accessing operation with page or leaf (Page) when carrying out read usually.A page data is generally 2KB or 4KB; A blocks of data (Block) generally includes 64,128 or 256 page datas.
Join of the prior art a kind of memory access control apparatus 200 shown in Figure 1, it generally includes a CPU207 and dma controller 202 and temporary storage cell 2021 thereof by linking to each other with system bus 205.This dma controller 202 links to each other with system bus 205, in order under the control of main frame (not shown), the data among the DRAM2041 is conducted interviews, and is carrying out data transmission under the control of CPU simultaneously between DRAM2041 and NAND2031.
Memory access control apparatus 200 of the prior art needs by system bus 205 couples of DRAM2041, NAND2031 usually to realize the mutual transmission of data.But along with people are more and more higher to the bandwidth (Band Width) and the requirement of transmission speed of data transmission, therefore increase of the contention of DRAM2041 and the NAND2031 data in can causing undoubtedly transmitting simply to system bus 205, thereby cause the obstruction of system bus 205, cause the efficient of data transmission and speed not satisfactory.
Simultaneously, in the prior art, moderator (not shown) is set usually in system bus 205 in order to a plurality of access request signals are arbitrated.But this prior art still can cause the burden to system bus 205, causes the decline of system running speed.
At last, because memory access control apparatus of the prior art need be provided with CPU207, so its manufacturing cost is also than higher.
In view of this, be necessary memory access control apparatus of the prior art is improved, to solve above-mentioned technological deficiency.
Summary of the invention
Goal of the invention of the present invention is to provide a kind of and significantly improves data rate, reduces the obstruction of data in system bus and effectively improves data transmission efficiency and lower-cost memory access control apparatus.
For achieving the above object, the invention discloses a kind of memory access control apparatus, connect some first memories and some second memories, comprising:
Module is selected in some access request generation modules, some access request execution modules and some arbitrations; Described arbitration selects module to comprise: ID screening washer, moderator, first MUX and second MUX;
Be sent to moderator after described ID screening washer is received from the access request signal of access request generation module and filters out the valid memory access request signal and carry out arbitration process, comprise the arbitration result of priority with generation, and select to form between module and the access request generation module some two-way data transmission channels in access request execution module, arbitration according to arbitration result.
As a further improvement on the present invention, described access request execution module coupling connects a first memory, and described access request generation module coupling connects a second memory.
As a further improvement on the present invention, described access request signal comprises data source address, datum target address, data transfer direction, data label and access request destination ID.
As a further improvement on the present invention, whether contain the corresponding access request of the first memory destination ID that is connected with access request execution module coupling in some access request signals that described ID screening washer is generated by comparison access request generation module, in order to filter out the valid memory access request signal.
As a further improvement on the present invention, moderator carries out arbitration process according to the equal rights rules of arbitration to the valid memory access request signal, the arbitration result that comprises priority with generation, and send arbitration result to the first MUX, in order to set up the transmission channel of at least one access request signal between access request execution module, first MUX and the access request generation module.
As a further improvement on the present invention, when data when second memory transfers to first memory, described moderator only is sent to arbitration result first MUX, to set up the plurality of data transmission channel at access request execution module, first MUX and access request generation module.
As a further improvement on the present invention, when data when first memory transfers to second memory, described moderator also is sent to arbitration result second MUX, to set up the plurality of data transmission channel at access request execution module, second MUX and access request generation module.
As a further improvement on the present invention, described first MUX is that unit transfers to the access request execution module from the access request generation module with the page or leaf with data according to arbitration result successively; Described second MUX is that unit transfers to the access request generation module from the access request execution module with the page or leaf with data according to arbitration result successively.
As a further improvement on the present invention, described arbitration selects the module coupling to connect an access request execution module, and lotus root connects some access request generation modules.
As a further improvement on the present invention, described memory access control apparatus does not comprise CPU.
Compared with prior art, the invention has the beneficial effects as follows: in the present invention, filter out the valid memory access request signal by the ID screening washer, and the access request signal of the response of the arbitration result by moderator high priority and set up data transmission channel with the transmission data, reduced the contention of data, realized the high-speed bidirectional transmission of data system bus; Simultaneously, owing to do not need to be provided with CPU, can reduce the manufacturing cost of memory access control apparatus.
Description of drawings
Fig. 1 is the structured flowchart of a kind of memory access control apparatus of the prior art;
Fig. 2 is the structured flowchart of a kind of memory accessing controller of the present invention among the embodiment one;
Fig. 3 transfers to the data of first memory and the transmission synoptic diagram of signal for data among the embodiment one from second memory;
Fig. 4 transfers to the data of second memory and the transmission synoptic diagram of signal for data among the embodiment one from first memory;
Fig. 5 is the exemplary embodiment with the moderator in the example shown in the timing diagram form one;
Fig. 6 is the structured flowchart of a kind of memory accessing controller of the present invention in the example two;
Fig. 7 carries out the synoptic diagram of access destination ID screening to two access request signals for ID screening washer among the embodiment two;
Fig. 8 is with the exemplary embodiment of the moderator in the example shown in the timing diagram form two;
Fig. 9 is the structured flowchart of a kind of memory accessing controller of the present invention among the embodiment three;
Figure 10 is the detailed block diagram of a kind of memory accessing controller shown in Figure 9;
Figure 11 illustrates the exemplary embodiment of the moderator in the example three with timing diagram form;
Figure 12 illustrates the exemplary embodiment of the moderator in the example three with timing diagram form;
Figure 13 among the embodiment four based on a kind of structural representation that mixes memory storage of a kind of memory access control apparatus of the present invention.
Wherein, description of reference numerals is as follows:
Memory access control apparatus: 100;
System bus: 60;
Main frame: 70;
Module is selected in arbitration: 10,110,111;
ID screening washer: 101,1011,1012;
Moderator: 102,1021,1022;
First MUX: 103,1031,1032;
Second MUX: 104,1041,1042;
Access request generation module: 20,210,211;
Access request execution module: 30,310,311;
Mix memory storage: 300;
First memory: 40;
Second memory: 50;
DRAM：401、402；
NAND：501、502。
Embodiment
The present invention is described in detail below in conjunction with each embodiment shown in the drawings; but should be noted that; these embodiments are not limitation of the present invention; the function that those of ordinary skills do according to these embodiments, method or structural equivalent transformation or alternative all belong within protection scope of the present invention.
Embodiment one
Please join the first kind embodiment of Fig. 2 to a kind of memory access control apparatus 100 of the present invention shown in Figure 5.
In the present embodiment, a kind of memory access control apparatus 100 connects first memory 40 and second memory 50.As preferred embodiment, described first memory 40 is a volatile memory, and DRAM (dynamic RAM) more preferably; Described second memory 50 is a nonvolatile memory, and NAND more preferably.
As shown in Figure 2, this memory access control apparatus 100 comprises:
Described access request execution module 30 couplings connect a first memory 40, and described access request generation module 20 couplings connect a second memory 50.Simultaneously, this access request generation module 20 links to each other with system bus 60.Main frame 70 can send CMD (order) signal to access request generation module 20 by system bus 60, and sends access request signal 201 by access request generation module 20 to ID screening washer 101 under the control of cmd signal.
Described ID screening washer 101 is received from the access request signal 201 of access request generation module 20, and filter out and be sent to moderator 102 behind the valid memory access request signal (Valid REQ) and carry out arbitration process, comprise the arbitration result of priority with generation, and select to form between module 10 and the access request generation module 20 two-way data transmission channel in access request execution module 30, arbitration according to arbitration result.
Concrete, in the present embodiment, because 100 couplings of this memory access control apparatus connect a first memory 40 and a second memory 50.So the access request destination ID in the access request signal 201 that access request module 20 is generated is all corresponding with the ID in the first memory 40.To in other embodiment of this instructions, release bright so how ID screening washer 101 and moderator 102 specifically realize the technical scheme of screening and arbitrating.
When data from first memory 40 transfer to second memory 50 also or data when second memory 50 transfers to first memory 40, be the access request generation module 20 that is connected with second memory 50 couplings to access request execution module 30 transmission access request signals 201.This access request signal 201 comprises data source address, datum target address, data transfer direction, data label and access request destination ID.
Cooperate with reference to shown in Figure 3, when data Data-1 when second memory 50 transfers to first memory 40, between second memory 50, access request generation module 20, first MUX 103, access request execution module 30 and first memory 40, set up a unidirectional data transmission channel (delivering path of the Data-1 that dotted line constituted among ginseng Fig. 3) respectively.
In the present embodiment, moderator 102 only is sent to arbitration result first MUX 103, to set up a unidirectional data transmission channel at access request execution module 30, first MUX 103 and access request generation module 20.
Described first MUX 103 is that unit transfers to access request execution module 30 from access request generation module 20 with data Data-1 with page or leaf (Page) successively, and finally writes in the first memory 40 according to arbitration result.
Cooperate with reference to shown in Figure 4, when data Data-2 when first memory 40 transfers to second memory 50.The arbitration result that described moderator 102 also will include priority is sent to second MUX 104, in order to set up the transmission channel of data Data-2 between access request execution module 30 and access request generation module 20 by this second MUX 104.Thereby be implemented in and set up a unidirectional data transmission channel (delivering path of the Data-2 that dotted line constituted among ginseng Fig. 4) between first memory 40, access request execution module 30, second MUX 104, access request generation module 20 and the second memory 50.
In the present embodiment, second MUX 104 is that unit transfers to access request generation module 20 from access request execution module 30 with data Data-2 with page or leaf (Page) successively, and finally writes in the second memory 50 according to arbitration result.
Concrete, second memory 50 is by Flash interface (not shown) and access request generation module 20 transmission data.First memory 40 is by DRAM interface (not shown) and access request execution module 30 transmission data.Because Flash interface and DRAM interface are very ripe prior aries, do not repeat them here.
In conjunction with Fig. 3 and shown in Figure 4, in the present embodiment, can select to generate between module 10 and the access request generation module 20 a two-way data transmission channel in access request execution module 30, arbitration.
As shown in Figure 5, wherein, the clock signal of CLK representative system bus 60.In the present embodiment, send access request signals 201 to ID screening washer 101 when access request generation module 20.When comprising the ID identical in these access request signals 201 of ID screening washer 101 contrast with first memory 40, judge that then this access request signal 201 is valid memory access request signal (Valid REQ), and this valid memory access request signal (Valid REQ) is sent to moderator 102 to carry out arbitration process.
Wherein, T1 is the response time of 102 pairs of access request signals 201 of moderator, and to be Date-1 transfer to the transmission time of first memory 40 or transfer to transmission time of second memory 50 for Data-2 from first memory 40 from second memory 50 T11.
When data Data-1 or Data-2 between first memory 40 and second memory 50 after the end of transmission, access request generation module 20 is answered the request of second memory 50, discharges access request signal 201.
In the present embodiment, this memory access control apparatus 100 does not comprise CPU (central processing unit), can further reduce the manufacturing cost of this memory access control apparatus 100 like this.
Concrete, in the present embodiment, this second memory 50 is NAND, certainly also can be the nonvolatile memory of other types, for example: phase transition storage (FCM), strong dielectric body storer (FeRAM), magnetic recording formula write readout memory (MRAM), two-way storage and uniform device (OUM) or resistance R AM (RRAM) at any time.This first memory 40 also can be SRAM (static RAM).
Embodiment two
Ginseng Fig. 6 is to second kind of embodiment of a kind of memory access control apparatus of the present invention shown in Figure 8.
In the present embodiment, this memory access control apparatus 100 comprises that an arbitration selects module 10, access request execution module 30 and two access request generation modules 210,211.
Join shown in Figure 6ly, this access request generation module 210 couplings connect NAND501, and access request generation module 211 couplings connect NAND502.Arbitration selection module 10 is mated successively with access request execution module 30 and DRAM401 and is connected; And this arbitration selects module 10 to couple two access request generation modules 210,211.
Certainly, but this arbitration selection module 10 also lotus root connects more access request generation module 20 (not shown), and by a plurality of NAND of access request generation module 20 coupling connections, thereby form more data transmission channel (not shown), write NAND or write the efficient of DRAM from DAND from DRAM to improve data.
Cooperate with reference to shown in Figure 2, in the present embodiment, the access request destination ID that access request generation module 210,211 comprises in the access request signal 2101,2111 that arbitration selects module 10 to send is corresponding with the ID of DRAM401, then this arbitration selects module 10 access request signal 2101,2111 can be arbitrated, and can be preferential selects module 10 to set up data transmission channel (being the sequencing that passage 1 and passage 2 among Fig. 6 are set up) with arbitration in order to which to be determined in the access request generation module 210,211.
Shown in Figure 7 in conjunction with ginseng, in the present embodiment, ID screening washer 101 is sent to and carries out arbitration process in the moderator 102 after judging that access request signal 2101,2111 is valid memory access request signal (Valid REQ).This moderator 102 carries out arbitration process according to the equal rights rules of arbitration to access request signal 2101,2111.
Concrete, when 102 pairs of access request signals of moderator 2101,2111 carry out the first time during arbitration process, access request signal 2101 is judged as higher priority, and access request signal 2111 is judged as lower priority.Therefore, preferentially carry out the transmission operation of 2101 corresponding datas of access request signal.When these access request signal 2101 pairing data be transmitted finish after, discharge this access request signal 2101, this moment, moderator 102 was judged to be higher priority with access request signal 2111, and began to carry out the transmission operation of 2111 corresponding datas of access request signal.When these access request signal 2111 pairing data be transmitted finish after, discharge this access request signal 2111, thereby access request signal 2101,2111 pairing all data transmission finished.
Need to prove, select module 10 lotus roots when this arbitration and connect three or more access request generation module 20, and when the access request signal 201 that all access request generation modules 20 are generated is valid memory access request signal (Valid REQ), arbitration selects the moderator 102 in the module 10 at first to judge the access request signal of higher priority in a plurality of valid memory access request signals, and preferentially begins to carry out data transfer operation.When the pairing data of the access request signal of this higher priority be transmitted finish after, discharge this access request signal.Then, moderator 102 is judged the access request signal of higher priority again in remaining valid memory access request signal, and begins to carry out data transfer operation.Thereby carry out data transfer operation successively, up to all access request signal 201 pairing all data transmission are finished.
Cooperation is with reference to Fig. 2 and shown in Figure 6, in the present embodiment, arbitration selects the moderator 102 in the module 10 according to the equal rights rules of arbitration access request signal 2101,2111 to be carried out arbitration process, the arbitration result that comprises priority with generation, and send arbitration result to the first MUX 103, between access request execution module 30, first MUX 103 and access request generation module 210,211, set up the transmission channel (being the transmission channel of access request signal 2101,2111 among Fig. 6) of two access request signals then.
Further, after moderator 102 carries out the arbitration process first time, the access request signal 2101 of module 10 according to higher priority selected in this arbitration, selects to set up a two-way data transmission channel (being the passage 1 among Fig. 6) between module 10, access request generation module 210, the NAND501 in DRAM401, access request execution module 30, arbitration.Next, the access request signal 2111 of module 10 according to lower priority selected in arbitration, selects to set up a two-way data transmission channel (being the passage 2 among Fig. 6) between module 10, access request generation module 211, the NAND502 in DRAM401, access request execution module 30, arbitration.
For further improving the transmission speed of data, memory buffer (not shown) can be set in access request generation module 210,211 and/or access request execution module 30.This memory buffer can be made up of a plurality of FIFO storeies.
Thereby select between module 10, the access request generation module 30 in access request module 210 and arbitration; And select to form between module 10, the access request generation module 30 two two-way data transmission channels (being the passage 1 and passage 2 among Fig. 6) in access request module 211 and arbitration.
In the present embodiment, data transfer to NAND501,502 from DRAM401, and perhaps the specific implementation process ginseng embodiment one of data when NAND501,502 transfers to DRAM401 do not repeat them here.
In conjunction with reference to Fig. 2 and shown in Figure 8, in the present embodiment, access request signal 2101,2111 is valid memory access request signal (Valid REQ).In Fig. 8, T2 is the response time of 102 pairs of access request signals 2101 of moderator; T3 is the response time of 102 pairs of access request signals 2111 of moderator.
Concrete, in the present embodiment because access request signal 2101 is judged as higher priority, thus passage 1 at first be established, in order between DRAM401 and NAND501, to carry out two-way data transfer operation.When passage 1 was set up, access request signal 2111 was in waiting status, and kept high level state.
When access request signal 2101 pairing data be transmitted finish after (be T21 finish), access request module 201 is answered the request of NAND501, discharge access request signal 2101, and the moderator 102 in the module 10 is selected in the notice arbitration, in order to access request signal 2111 is judged to be higher priority by moderator 102, thereby set up passage 2, in order between DRAM401 and NAND502, to carry out two-way data transfer operation.In like manner, finish when access request signal 2111 pairing data are transmitted after (being that T31 finishes), access request module 211 is answered the request of NAND502, discharges access request signal 2111.
In Fig. 8, T21 is the time that passage 1 foundation back DRAM401 and NAND501 carry out data transmission, and T31 is the time that passage 2 foundation back DRAM401 and NAND502 carry out data transmission.Priority by above-mentioned data transmission channel (being the passage 1 and passage 2 among Fig. 6) is set up, and a certain size data are transferred to DRAM401 from NAND501,502.
Need to prove, when a certain size data when DRAM401 transfers to the situation of NAND501 or NAND502, its concrete implementation is identical from the specific implementation process that NAND501,502 transfers to DRAM401 with data, does not repeat them here.
Embodiment three
Please join a kind of embodiment of Fig. 9 to a kind of memory access control apparatus of the present invention shown in Figure 12.
As shown in Figure 9, the key distinction of present embodiment and preceding two kinds of embodiments is, this memory access control apparatus 100 comprises two arbitration selection modules 110,111, and arbitration selects module 110 couplings to connect access request execution module 310, and arbitration selects module 111 couplings to connect access request execution module 311.Described arbitration selects module 10 lotus roots to connect access request generation module 210,211.
Cooperate ginseng shown in Figure 10, this access request generation module 210 can be sent to access request signal 2101 ID screening washer 1011 and ID screening washer 1012 simultaneously; Access request generation module 211 also can be sent to access request signal 2111 ID screening washer 1011 and ID screening washer 1012 simultaneously.
Then, judge in ID screening washer 1011 and ID screening washer 1012 respectively whether this access request signal 2101,2111 contains DRAM401, the 402 corresponding access request destination ID that are connected with this access request execution module 310,311 couplings, in order to filter out valid memory access request signal (Valid REQ).
Wherein, the screening process of 1012 pairs of access request signals of ID screening washer 1011 and ID screening washer 2101,2111 ginseng embodiment two.
In the present embodiment, access request generation module 210,211 links to each other with main frame 70 by system bus 60, and can select module 110,111 to send access request signal to any one arbitration.
If comprise in a certain access request signal with arbitration and select module 110 or 111 DRAM401 or the 402 identical ID that link to each other, judge that then this access request signal is the valid memory access request signal, and select the moderator (102 among ginseng Fig. 2) in the module 110 or 111 to carry out arbitration process according to arbitration, have higher priority in order to definite which access request signal, thereby set up two two-way data transmission channels.
Concrete, join shown in Figure 10, in the present embodiment, access request destination ID in the access request signal 2101 that access request generation module 210 generates is for pointing to DRAM401, and the access request destination ID in the access request signal 2111 that access request generation module 211 generates is for pointing to DRAM402.
In the present embodiment, access request generation module 210 can be sent to access request signal 2101 ID screening washer 1011 and screening washer 1012 simultaneously.At this moment, ID screening washer 1011 judges that the access request signal 2101 that access request generation module 210 generates is the valid memory access request signal, and judges that the access request signal 2111 that access request generation module 211 generates is invalid access request signal.
Access request generation module 211 also can be sent to access request signal 2111 ID screening washer 1011 and screening washer 1012 simultaneously.At this moment, ID screening washer 1012 judges that the access request signal 2101 that access request generation module 210 generates is invalid access request signal, and judges that the access request signal 2111 that access request generation module 211 generates is the valid memory access request signal.
Then, ID screening washer 1011 is sent to the valid memory access request signal moderator 1021 and carries out arbitration process, ID screening washer 1012 is sent to the valid memory access request signal moderator 1022 and carries out arbitration process, the arbitration result that comprises priority with generation, and select between module 110, the access request generation module 210 in access request execution module 310, arbitration, and select to form between module 111, the access request generation module 211 two two-way data transmission channels in access request execution module 311, arbitration according to arbitration result.Wherein, the specific implementation process of the data transmission channel that each bar is two-way ginseng embodiment one repeats no more in the present embodiment.
Shown in Figure 11 in conjunction with ginseng, in the time of T41, begin to carry out data transfer operation between NAND501 and the DRAM401.After data transmission finished, access request generation module 210 was answered the request of NAND501, discharged access request signal 2101.Wherein, T4 is the response time of 1021 pairs of access request signals 2101 of moderator, and T41 is the time of carrying out data transmission between NAND501 and the DRAM401.
Simultaneously, module 110 is selected in arbitration, access request destination ID that comprises in the access request signal 2111 and the ID of DRAM401 do not match, selected the ID screening washer 1011 in the module 110 to be judged to be invalid access request signal by arbitration, so 1021 pairs of access request signals 2111 of moderator are not done any response.So the rising edge signal can not occur all the time in the arbitration result of 1021 pairs of access request signals 2111 of moderator.
Shown in Figure 12 in conjunction with ginseng, in the time of T51, begin to carry out data transfer operation between NAND502 and the DRAM402.After data transmission finished, access request generation module 211 was answered the request of NAND502, discharged access request signal 2111.Wherein, T5 is the response time of 1022 pairs of access request signals 2111 of moderator, and T51 is the time of carrying out data transmission between NAND502 and the DRAM402.
Simultaneously, module 111 is selected in arbitration, access request destination ID that comprises in the access request signal 2101 and the ID of DRAM402 do not match, selected the ID screening washer 1012 in the module 111 to be judged to be invalid access request signal by arbitration, so 1022 pairs of access request signals 2101 of moderator are not done any response.So the rising edge signal can not occur all the time in the arbitration result of 1022 pairs of access request signals 2101 of moderator.
In the present embodiment, NAND501 can pass through access request execution module 310, second MUX 1041, access request generation module 210 with DRAM401, and get request execution module 310, first MUX 1031, access request generation module 210, form two data transmission channels (i.e. two-way data transmission channel).Simultaneously, access request execution module 311, arbitration are selected then can not form two-way data transmission channel between module 111 and the access request generation module 210.
Simultaneously, NAND502 can pass through access request execution module 311, second MUX 1042, access request generation module 211 with DRAM402, and get request execution module 311, first MUX 1032, access request generation module 211, form two data transmission channels (i.e. two-way data transmission channel).Simultaneously, access request execution module 310, arbitration are selected then can not form two-way data transmission channel between module 110 and the access request generation module 211.
In the present embodiment, select between module 110, the access request generation module 210 at access request execution module 310 and arbitration, and select to form between module 111, the access request generation module 211 two in access request execution module 311 and arbitration and be parallel to each other and be two-way data transmission channel.
Need to prove, the access request destination ID that comprises in the access request signal 2101 that access request generation module 210 answers NAND501 to generate is for pointing to DRAM402, and the access request destination ID that comprises in the access request signal 2111 that access request generation module 211 answers NAND502 to generate is under the situation of pointing to DRAM401, select module 110 in access request execution module 310 and arbitration, between the access request generation module 211, and in access request execution module 311 and arbitration selection module 111, then can form two mutual intersections between the access request generation module 210 and be two-way data transmission channel.
In sum, in the present embodiment, access request execution module 310,311 and arbitration are selected can form two two-way data transmission channels between module 110,111 and the access request generation module 210,211.
Embodiment four
Please join a kind of a kind of embodiment that mixes memory storage 300 of the present invention shown in Figure 13.Figure 13 among the embodiment four based on a kind of structural representation that mixes memory storage of a kind of memory access control apparatus of the present invention.
In the present embodiment, a kind of mixing memory storage 300 comprises:
Some first memories 40, some second memories 50, and the some memory access control apparatus 100 that connect first memory 40 and second memory 50 respectively.
In the present embodiment, this first memory 40 is selected from DRAM (stochastic and dynamic access memory), and this second memory 50 is selected from NAND.DRAM has higher access speed and bigger bandwidth (Band Width), and NAND then has lower cost, bigger memory capacity, but its bandwidth and access speed are relatively low.
Shown in Figure 2 in conjunction with ginseng, in the present embodiment, each memory access control apparatus 100 comprises:
Described ID screening washer 101 is received from the access request signal 201 of access request generation module 20, and filter out and be sent to moderator 102 behind the valid memory access request signal (Valid REQ) and carry out arbitration process, comprise the arbitration result of priority with generation, and select to form between module 10 and the access request generation module 20 a two-way data transmission channel in access request execution module 30, arbitration according to arbitration result.
Described access request execution module 30 couplings connect a first memory 40; Described access request generation module 20 couplings connect a second memory 50.
In the present embodiment, each memory access control apparatus 100 is used to control the Data Transmission Controlling between first memory 40 and the second memory 50.The specific implementation process ginseng embodiment one of the transmitted in both directions of these memory access control apparatus 100 specific implementation data between first memory 40 and second memory 50 does not repeat them here.
Concrete, all the capacity of second memory 50 is greater than or equal to the capacity of whole first memories 40, and the capacity that is preferably equates.Second memory 50 equates with the quantity of first memory 40, also the quantity of second memory 50 can be arranged to the quantity (not shown) greater than first memory 40 certainly.
Preferably, this mixes memory access control apparatus a plurality of in the memory storage 300 100 parallel settings; And described memory access control apparatus 100 does not comprise CPU, can reduce the manufacturing cost of this mixing memory storage 300 like this.
In the present embodiment, a plurality of NAND and one or two DRAM setting that cooperatively interacts can be set, thereby form the mixing memory storage 300 of a kind of hyperchannel, two-way, high-speed transfer.
Each embodiment described above only is that schematically the application can be used in numerous general or special-purpose computingasystem environment or configuration or communication system environment or the equipment.For example: personal computer, server computer, handheld device or portable set, plate equipment, multiprocessing system, system, programmable consumer-elcetronics devices, small-size computer, mainframe computer based on microprocessor, the distributed computing environment that perhaps comprises above any system or equipment, and switch, router etc.
Above listed a series of detailed description only is specifying at feasibility embodiment of the present invention; they are not in order to restriction protection scope of the present invention, allly do not break away from equivalent embodiment or the change that skill spirit of the present invention done and all should be included within protection scope of the present invention.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and under the situation that does not deviate from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims rather than above-mentioned explanation, therefore is intended to include in the present invention dropping on the implication that is equal to important document of claim and all changes in the scope.Any Reference numeral in the claim should be considered as limit related claim.
In addition, be to be understood that, though this instructions is described according to embodiment, but be not that each embodiment only comprises an independently technical scheme, this narrating mode of instructions only is for clarity sake, those skilled in the art should make instructions as a whole, and the technical scheme among each embodiment also can form other embodiments that it will be appreciated by those skilled in the art that through appropriate combination.
Claims (10)
1. a memory access control apparatus connects some first memories and some second memories, it is characterized in that, comprising:
Module is selected in some access request generation modules, some access request execution modules and some arbitrations; Described arbitration selects module to comprise: ID screening washer, moderator, first MUX and second MUX;
Be sent to moderator after described ID screening washer is received from the access request signal of access request generation module and filters out the valid memory access request signal and carry out arbitration process, comprise the arbitration result of priority with generation, and select to form between module and the access request generation module some two-way data transmission channels in access request execution module, arbitration according to arbitration result.
2. memory access control apparatus according to claim 1 is characterized in that, described access request execution module coupling connects a first memory, and described access request generation module coupling connects a second memory.
3. memory access control apparatus according to claim 1 is characterized in that, described access request signal comprises data source address, datum target address, data transfer direction, data label and access request destination ID.
4. according to each described memory access control apparatus in the claim 1 to 3, it is characterized in that, whether contain the corresponding access request of the first memory destination ID that is connected with access request execution module coupling in some access request signals that described ID screening washer is generated by comparison access request generation module, in order to filter out the valid memory access request signal.
5. according to claim 1 or 4 described memory access control apparatus, it is characterized in that, moderator carries out arbitration process according to the equal rights rules of arbitration to the valid memory access request signal, the arbitration result that comprises priority with generation, and send arbitration result to the first MUX, in order to set up the transmission channel of at least one access request signal between access request execution module, first MUX and the access request generation module.
6. memory access control apparatus according to claim 1 or 5, it is characterized in that, when data when second memory transfers to first memory, described moderator only is sent to arbitration result first MUX, to set up the plurality of data transmission channel at access request execution module, first MUX and access request generation module.
7. memory access control apparatus according to claim 1 or 5, it is characterized in that, when data when first memory transfers to second memory, described moderator also is sent to arbitration result second MUX, to set up the plurality of data transmission channel at access request execution module, second MUX and access request generation module.
8. according to claim 6 or 7 described memory access control apparatus, it is characterized in that described first MUX is that unit transfers to the access request execution module from the access request generation module with the page or leaf with data according to arbitration result successively; Described second MUX is that unit transfers to the access request generation module from the access request execution module with the page or leaf with data according to arbitration result successively.
9. memory access control apparatus according to claim 1 is characterized in that, described arbitration selects the module coupling to connect an access request execution module, and lotus root connects some access request generation modules.
10. memory access control apparatus according to claim 1 is characterized in that described memory access control apparatus does not comprise CPU.
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