CN103219302B - Perforated interposer - Google Patents
Perforated interposer Download PDFInfo
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- CN103219302B CN103219302B CN201210018108.4A CN201210018108A CN103219302B CN 103219302 B CN103219302 B CN 103219302B CN 201210018108 A CN201210018108 A CN 201210018108A CN 103219302 B CN103219302 B CN 103219302B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
技术领域 technical field
本发明有关一种中介板,尤指一种具有穿孔的中介板。The invention relates to an intermediary board, especially an intermediary board with perforations.
背景技术 Background technique
自从IBM公司在1960年早期引入倒装芯片封装(FlipChipPackage)技术以来,相比于打线接合(WireBond)技术,倒装芯片技术的特征在于半导体芯片与基板间的电性连接通过焊锡凸块而非一般的金线。而该种倒装芯片技术的优点在于该技术可提升封装密度以降低封装组件尺寸,同时,该种倒装芯片技术不需使用长度较长的金线,所以可提升电性性能。有鉴于此,业界在陶瓷基板上使用高温焊锡,即所谓控制崩解的芯片连接技术(Control-CollapseChipConnection,C4),已有多年。近年来,由于高密度、高速度以及低成本的半导体组件需求的增加,同时因应电子产品的体积逐渐缩小的趋势,将倒装芯片组件设置于低成本的有机电路板(例如,印刷电路板或基板),并以环氧树脂底胶(Underfillresin)填充于芯片下方以减少硅芯片与有机电路板的架构间因热膨胀差异所产生的热应力,已呈现爆炸性的成长。Since IBM introduced flip chip packaging (FlipChipPackage) technology in the early 1960s, compared to wire bonding (WireBond) technology, flip chip technology is characterized by the electrical connection between the semiconductor chip and the substrate through solder bumps. No ordinary gold thread. The advantage of the flip chip technology is that the technology can increase the packaging density to reduce the size of the package components. At the same time, the flip chip technology does not need to use longer gold wires, so the electrical performance can be improved. In view of this, the industry has been using high-temperature solder on ceramic substrates, the so-called Control-Collapse Chip Connection (C4), for many years. In recent years, due to the increase in demand for high-density, high-speed and low-cost semiconductor components, and in response to the trend of shrinking electronic products, flip-chip components are placed on low-cost organic circuit boards (such as printed circuit boards or Substrate), and epoxy underfill resin (Underfillresin) is used to fill the bottom of the chip to reduce the thermal stress caused by the difference in thermal expansion between the silicon chip and the structure of the organic circuit board, which has shown explosive growth.
在现行倒装芯片技术中,半导体集成电路(IC)芯片的表面上配置有电极垫(electronicpad),而封装基板也具有相对应的倒装芯片焊垫,在该芯片以及封装基板之间可以适当地设置焊锡凸块或其它导电焊锡材料,使该芯片是以作用面朝下的模式设置于该封装基板上,其中,该焊锡凸块或导电粘着材料提供该芯片以及封装基板间的电性输入/输出(I/O)以及机械性的连接。后续将该封装基板与半导体芯片等进行封装工艺时,为提供该封装基板得以与外界电子装置(如电路板)电性连接,通常必须于该封装基板底面植设多个焊球。In the current flip-chip technology, the surface of the semiconductor integrated circuit (IC) chip is provided with electrode pads (electronic pads), and the packaging substrate also has corresponding flip-chip bonding pads, which can be properly connected between the chip and the packaging substrate. Solder bumps or other conductive solder materials are placed so that the chip is placed on the package substrate in an active face-down mode, wherein the solder bumps or conductive adhesive material provide electrical input between the chip and the package substrate /Output (I/O) and mechanical connections. When the encapsulation substrate and the semiconductor chip etc. are subsequently packaged, in order to provide the encapsulation substrate to be electrically connected to an external electronic device (such as a circuit board), it is usually necessary to plant a plurality of solder balls on the bottom surface of the encapsulation substrate.
随着电子产品更趋于轻薄短小及功能不断提升的需求,该半导体芯片的布线密度愈来愈高,以纳米尺寸作单位,因而该封装基板的各倒装芯片焊垫之间的间距更小。As electronic products tend to be thinner, lighter and smaller, and their functions are constantly improved, the wiring density of the semiconductor chip is getting higher and higher, with nanometers as the unit, so the spacing between the flip chip pads of the packaging substrate is smaller .
目前封装基板的倒装芯片焊垫的间距以微米尺寸作单位,而无法有效缩小至对应该芯片的各电极垫的间距的大小,导致虽有高线路密度的半导体芯片,却未有可配合的封装基板,以致于无法有效生产电子产品。At present, the pitch of the flip-chip bonding pads on the package substrate is in microns, which cannot be effectively reduced to the size corresponding to the pitch of the electrode pads of the chip. As a result, although there are semiconductor chips with high circuit density, there is no compatible chip. Encapsulate the substrate so that it cannot effectively produce electronic products.
为克服上述的问题,所以于该封装基板9与半导体芯片8之间增设一硅中介板(Siliconinterposer)1,如图1A所示,该硅中介板1具有硅本体10、穿设于该硅本体10中的硅穿孔(Through-siliconvia,TSV)14及设于该硅本体10与硅穿孔14顶端上的线路重布层(Redistributionlayer,RDL)13,令该硅穿孔14的底端借由导电凸块92电性结合间距较大的封装基板9的倒装芯片焊垫90,而该线路重布层13的最上层线路具有电性连接垫,以借由焊锡凸块81电性结合间距较小的半导体芯片8的电极垫80,再形成封装胶体7。In order to overcome the above-mentioned problems, a silicon interposer (Silicon interposer) 1 is added between the packaging substrate 9 and the semiconductor chip 8. As shown in FIG. Through-silicon via (Through-siliconvia, TSV) 14 in 10 and the circuit redistribution layer (Redistribution layer, RDL) 13 on the top of the silicon body 10 and the through-silicon via 14 make the bottom of the through-silicon via 14 via the conductive bump The block 92 is electrically connected to the flip-chip pad 90 of the packaging substrate 9 with a large spacing, and the uppermost circuit of the circuit redistribution layer 13 has an electrical connection pad, so as to be electrically connected with a small spacing through the solder bump 81 The electrode pads 80 of the semiconductor chip 8 are formed into the encapsulation compound 7 .
借此,使该封装基板9可结合具有高布线密度电极垫80的半导体芯片8,而达到整合高布线密度的半导体芯片8的目的。所以借由该硅中介板1,不仅可解决缺乏可配合的封装基板的问题,且不会改变IC产业原本的供应链(supplychain)及基础设备(infrastructure)。Thereby, the packaging substrate 9 can be combined with the semiconductor chip 8 having the electrode pads 80 with high wiring density, so as to achieve the purpose of integrating the semiconductor chip 8 with high wiring density. Therefore, the silicon interposer 1 not only solves the problem of lack of compatible packaging substrates, but also does not change the original supply chain and infrastructure of the IC industry.
目前在硅穿孔14的制作中,于该硅穿孔14的孔壁上会形成绝缘层(isolationlayer)11,如图1B所示,其材质普遍使用SiNX、聚合物、高温炉或化学气相沉积(CVD)产生的SiO2。At present, in the manufacture of TSV 14, an isolation layer (isolation layer) 11 is formed on the hole wall of the TSV 14, as shown in FIG. CVD) produced SiO 2 .
但是,制作该绝缘层11的工艺中,均有些缺失,例如:化学气相沉积的工艺有漏电的可能、聚合物会有介电的问题、高温炉的工艺其温度过高,且产生的SiO2材料过硬、或者绝缘层11仅具单一种材质,会有可靠度及绝缘性的问题。However, there are some deficiencies in the process of making the insulating layer 11, for example: the chemical vapor deposition process has the possibility of electric leakage, the polymer has a dielectric problem, the temperature of the high-temperature furnace process is too high, and the produced SiO 2 If the material is too hard, or the insulating layer 11 has only a single material, there will be problems of reliability and insulation.
因此,如何克服上述现有技术中的种种问题,实已成目前亟欲解决的课题。Therefore, how to overcome various problems in the above-mentioned prior art has become an urgent problem to be solved at present.
发明内容 Contents of the invention
鉴于上述现有技术的种种缺失,本发明的主要目的在于提供一种穿孔中介板,借由在导电穿孔的孔壁上形成两种材质的绝缘层,以具有更佳防漏电与耐高电压特性。In view of the above-mentioned deficiencies in the prior art, the main purpose of the present invention is to provide a perforated interposer, which has better anti-leakage and high-voltage resistance characteristics by forming an insulating layer of two materials on the hole wall of the conductive perforated hole. .
本发明所提供的穿孔中介板,其导电穿孔的孔壁上具有第一绝缘层、形成于该第一绝缘层上的第二绝缘层、及形成于该第二绝缘层上的金属材,且该第一与第二绝缘层的材质不相同。The perforated interposer provided by the present invention has a first insulating layer, a second insulating layer formed on the first insulating layer, and a metal material formed on the second insulating layer on the wall of the conductive through hole, and The materials of the first and second insulating layers are different.
前述的穿孔中介板中,该第一与第二绝缘层可延伸至穿孔中介板的基板上。或者,该基板上可形成第一电性隔离层。In the aforementioned perforated interposer, the first and second insulating layers may extend to the substrate of the perforated interposer. Alternatively, a first electrical isolation layer can be formed on the substrate.
由上可知,本发明的穿孔中介板,通过于导电穿孔的孔壁上形成两种材质的绝缘层,相比于现有技术的单一材质绝缘层,具有更佳防漏电与耐高电压特性,且能提高绝缘性及提升电性传导的可靠度。It can be seen from the above that the perforated interposer of the present invention has better anti-leakage and high-voltage resistance characteristics than the single-material insulating layer of the prior art by forming an insulating layer of two materials on the hole wall of the conductive perforation. And it can improve the insulation and the reliability of electrical conduction.
附图说明 Description of drawings
图1A为现有封装基板、半导体芯片与硅中介板的封装剖视示意图;FIG. 1A is a schematic cross-sectional view of a packaging substrate, a semiconductor chip, and a silicon interposer;
图1B为现有硅中介板的局部放大剖视示意图;以及FIG. 1B is a partially enlarged cross-sectional schematic diagram of an existing silicon interposer; and
图2A至图2H为本发明穿孔中介板的制法的第一实施例的剖视示意图;其中,图2A’与图2D’分别为图2A与图2D的俯视图;2A to 2H are schematic cross-sectional views of the first embodiment of the manufacturing method of the perforated interposer of the present invention; wherein, FIG. 2A' and FIG. 2D' are the top views of FIG. 2A and FIG. 2D respectively;
图3A至图3C为本发明穿孔中介板的制法的第二实施例的剖视示意图;3A to 3C are schematic cross-sectional views of a second embodiment of the method for manufacturing a perforated interposer of the present invention;
图4A至图4C为本发明穿孔中介板的制法的第三实施例的剖视示意图;4A to 4C are schematic cross-sectional views of a third embodiment of the method for manufacturing a perforated interposer of the present invention;
图5A至图5H为本发明穿孔中介板的制法的第四实施例的剖视示意图;其中,图5B’为图5B的俯视图;5A to 5H are schematic cross-sectional views of a fourth embodiment of the method for manufacturing a perforated interposer of the present invention; wherein, FIG. 5B' is a top view of FIG. 5B;
图6A至图6C为本发明穿孔中介板的制法的第五实施例的剖视示意图;以及6A to 6C are schematic cross-sectional views of a fifth embodiment of the method for manufacturing a perforated interposer of the present invention; and
图7A至图7C为本发明穿孔中介板的制法的第六实施例的剖视示意图。7A to 7C are schematic cross-sectional views of a sixth embodiment of the manufacturing method of the perforated interposer of the present invention.
主要组件符号说明Explanation of main component symbols
1硅中介板1 silicon interposer
10硅本体10 silicon body
11绝缘层11 insulating layer
13线路重布层13 line redistribution layer
14硅穿孔14 TSV
2,2’,2”,3,3’,3”穿孔中介板2, 2’, 2”, 3, 3’, 3” perforated interposer
20,30基板20, 30 substrates
20a,30a第一表面20a, 30a first surface
20b,20b’,30b,30b’第二表面20b, 20b', 30b, 30b' second surface
200,300环形孔200, 300 annular holes
200a,201a,300a,301a底部200a, 201a, 300a, 301a bottom
201,301穿孔201, 301 perforation
21,31第一绝缘层21, 31 first insulating layer
22,32第二绝缘层22, 32 second insulating layer
220,360开孔220, 360 opening
23a,33a第一线路层23a, 33a first line layer
23b,33b第二线路层23b, 33b second circuit layer
24,24’,24”,34,34’,34”导电穿孔24, 24’, 24”, 34, 34’, 34” conductive through holes
24a,24a”,34a,34a”第一端面24a, 24a", 34a, 34a" first end face
24b,24b’,24b”,34b,34b’,34b”第二端面24b, 24b', 24b", 34b, 34b', 34b" second end face
240,340金属材240, 340 metal
25a,35a第一保护层25a, 35a first protective layer
25b,35b第二保护层25b, 35b second protective layer
250a,350a第一开孔250a, 350a first opening
250b,350b第二开孔250b, 350b second opening
26电性隔离层26 electrical isolation layer
36a第一电性隔离层36a first electrical isolation layer
36b第二电性隔离层36b second electrical isolation layer
7封装胶体7 Encapsulation colloid
8半导体芯片8 semiconductor chips
80电极垫80 electrode pads
81焊锡凸块81 solder bumps
9封装基板9 package substrate
90倒装芯片焊垫90 Flip Chip Bonding Pads
92导电凸块。92 conductive bumps.
具体实施方式 detailed description
以下借由特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。The implementation of the present invention will be described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,所以不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”及“一”等用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,也当视为本发明可实施的范畴。It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. Limiting conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should still fall within the scope of the present invention. The disclosed technical content must be within the scope covered. At the same time, terms such as "above" and "a" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the present invention, and the changes or adjustments of their relative relationships have no real meaning. Changes in technical content should also be regarded as the scope of the present invention that can be implemented.
请参阅图2A至图2H,其为本发明的穿孔中介板2的制法的第一实施例的剖视示意图。Please refer to FIG. 2A to FIG. 2H , which are schematic cross-sectional views of the first embodiment of the manufacturing method of the perforated interposer 2 of the present invention.
如图2A及图2A’所示,提供一具有相对的第一表面20a与第二表面20b的基板20。接着,于该基板20的第一表面20a上形成环形孔200,该环形孔200具有底部200a。As shown in FIG. 2A and FIG. 2A', a substrate 20 having opposite first surface 20a and second surface 20b is provided. Next, an annular hole 200 is formed on the first surface 20 a of the substrate 20 , and the annular hole 200 has a bottom 200 a.
于本实施例中,形成该基板20的材质可为玻璃、硅晶片、金属、Polymer。此外,该环形孔200的轮廓可为圆形或多边形,并无特别限制。In this embodiment, the material forming the substrate 20 may be glass, silicon wafer, metal, or polymer. In addition, the outline of the annular hole 200 can be circular or polygonal, and there is no special limitation.
如图2B所示,于该基板20的第一表面20a与环形孔200的孔壁上形成一第一绝缘层21。接着,于该基板20的第一表面20a上的第一绝缘层21之上形成一第二绝缘层22,且该第二绝缘层22还填满该环形孔200。As shown in FIG. 2B , a first insulating layer 21 is formed on the first surface 20 a of the substrate 20 and the wall of the annular hole 200 . Next, a second insulating layer 22 is formed on the first insulating layer 21 on the first surface 20 a of the substrate 20 , and the second insulating layer 22 also fills the annular hole 200 .
于本实施例中,所述的第一与第二绝缘层21,22的材质不相同,且该第一绝缘层21为硬质材,该第二绝缘层22是相对该第一绝缘层21为软质材。又该第一与第二绝缘层21,22的材质可为有机材或无机材,如环氧树脂、SiNX、SiO2等。In this embodiment, the materials of the first and second insulating layers 21 and 22 are different, and the first insulating layer 21 is a hard material, and the second insulating layer 22 is opposite to the first insulating layer 21. For soft material. In addition, the first and second insulating layers 21 and 22 can be made of organic or inorganic materials, such as epoxy resin, SiN x , SiO 2 and so on.
如图2C所示,于该第二绝缘层22上形成对应该环形孔200的开孔220,再移除该开孔220中的第一绝缘层21,以露出位于该环形孔200环内的基板20第一表面20a。As shown in FIG. 2C, an opening 220 corresponding to the annular hole 200 is formed on the second insulating layer 22, and then the first insulating layer 21 in the opening 220 is removed to expose the ring located in the annular hole 200. The first surface 20a of the substrate 20 .
如图2D及图2D’所示,移除该开孔220内的基板20材质,以令该环形孔200形成连通该基板20第一表面20a的穿孔201,该穿孔201具有底部201a,且该第一与第二绝缘层21,22作为该穿孔201的孔壁。As shown in FIG. 2D and FIG. 2D', the material of the substrate 20 in the opening 220 is removed, so that the annular hole 200 forms a through hole 201 communicating with the first surface 20a of the substrate 20, the through hole 201 has a bottom 201a, and the The first and second insulating layers 21 , 22 serve as walls of the through hole 201 .
如图2E所示,于该基板20的第一表面20a上的第二绝缘层22上形成一第一线路层23a,且于该穿孔201中形成一金属材240,以形成导电穿孔24。接着,于该第二绝缘层22与该第一线路层23a上形成一第一保护层25a。As shown in FIG. 2E , a first circuit layer 23 a is formed on the second insulating layer 22 on the first surface 20 a of the substrate 20 , and a metal material 240 is formed in the through hole 201 to form the conductive through hole 24 . Next, a first protective layer 25a is formed on the second insulating layer 22 and the first wiring layer 23a.
于本实施例中,是以电镀方式形成该第一线路层23a与导电穿孔24,也就是先于该基板20的第一表面20a上的第二绝缘层22与该穿孔201孔壁的第二绝缘层22上形成晶种层(seedlayer,图未示),再以该晶种层作为导通电流的路径,于该晶种层上形成该金属材240,以形成该第一线路层23a与导电穿孔24。In this embodiment, the first circuit layer 23a and the conductive through hole 24 are formed by electroplating, that is, prior to the second insulating layer 22 on the first surface 20a of the substrate 20 and the second hole wall of the through hole 201. A seed layer (seed layer, not shown) is formed on the insulating layer 22, and the metal material 240 is formed on the seed layer to form the first circuit layer 23a and Conductive vias 24 .
此外,该导电穿孔24具有对应该第一表面20a的第一端面24a与对应该第二表面20b的第二端面24b,而该导电穿孔24的第一端面24a电性连接该第一线路层23a,且该穿孔201的底部201a上具有该金属材240。In addition, the conductive through hole 24 has a first end surface 24a corresponding to the first surface 20a and a second end surface 24b corresponding to the second surface 20b, and the first end surface 24a of the conductive through hole 24 is electrically connected to the first circuit layer 23a , and the bottom 201a of the through hole 201 has the metal material 240 on it.
同时,该导电穿孔24的材质包含该金属材240、第一及第二绝缘层21,22。另外,该导电穿孔24为中空状,令该第一保护层25a填充于该导电穿孔24中。Meanwhile, the material of the conductive through hole 24 includes the metal material 240 , the first and the second insulating layers 21 , 22 . In addition, the conductive through hole 24 is hollow, so that the first protection layer 25 a is filled in the conductive through hole 24 .
如图2F所示,移除该基板20的第二表面20b的部分材质与该穿孔201底部201a的金属材240,以令该基板20的第二表面20b’与该导电穿孔24的第二端面24b齐平,而使该导电穿孔24的第二端面24b外露。As shown in FIG. 2F , part of the material of the second surface 20 b of the substrate 20 and the metal material 240 of the bottom 201 a of the through hole 201 are removed, so that the second surface 20 b ′ of the substrate 20 and the second end surface of the conductive through hole 24 24b, so that the second end surface 24b of the conductive through hole 24 is exposed.
如图2G所示,于该基板20的第二表面20b’上形成一电性隔离层26,以覆盖该导电穿孔24中的第一与第二绝缘层21,22,使该电性隔离层26露出该导电穿孔24的部分第二端面24b。As shown in FIG. 2G, an electrical isolation layer 26 is formed on the second surface 20b' of the substrate 20 to cover the first and second insulating layers 21, 22 in the conductive through hole 24, so that the electrical isolation layer 26 exposes part of the second end surface 24b of the conductive through hole 24 .
如图2H所示,于该电性隔离层26上形成一第二线路层23b,且该第二线路层23b电性连接该导电穿孔24的第二端面24b。最后,于该电性隔离层26与该第二线路层23b上形成一第二保护层25b,并于该第一与第二保护层25a,25b上形成多个第一与第二开孔250a,250b,以令该第一与第二线路层23a,23b的部分表面外露于该些第一与第二开孔250a,250b。As shown in FIG. 2H , a second circuit layer 23 b is formed on the electrical isolation layer 26 , and the second circuit layer 23 b is electrically connected to the second end surface 24 b of the conductive through hole 24 . Finally, a second protection layer 25b is formed on the electrical isolation layer 26 and the second circuit layer 23b, and a plurality of first and second openings 250a are formed on the first and second protection layers 25a, 25b , 250b, so that part of the surface of the first and second circuit layer 23a, 23b is exposed to the first and second openings 250a, 250b.
请参阅图3A至图3C,其为本发明的穿孔中介板2’的制法的第二实施例的剖视示意图。本实施例与第一实施例的差异仅在于保留该穿孔201底部201a的金属材240,其它相关工艺均相同,所以相同部分在此不再赘述。Please refer to FIG. 3A to FIG. 3C , which are schematic cross-sectional views of the second embodiment of the manufacturing method of the perforated interposer 2' of the present invention. The difference between this embodiment and the first embodiment is only that the metal material 240 at the bottom 201a of the through hole 201 is retained, and other related processes are the same, so the same parts will not be repeated here.
如图3A所示,其为图2E的工艺,于该基板20的第一表面20a上的第二绝缘层22上形成一第一线路层23a,且形成中空状的导电穿孔24’,该穿孔201的底部201a具有该金属材240。接着,于该第二绝缘层22与该第一线路层23a上形成一第一保护层25a,且该第一保护层25a填充于该导电穿孔24’中。As shown in FIG. 3A, which is the process of FIG. 2E, a first circuit layer 23a is formed on the second insulating layer 22 on the first surface 20a of the substrate 20, and a hollow conductive through hole 24' is formed. The through hole The bottom 201a of 201 has the metal material 240 . Next, a first protective layer 25a is formed on the second insulating layer 22 and the first wiring layer 23a, and the first protective layer 25a is filled in the conductive through hole 24'.
如图3B所示,移除该基板20的第二表面20b的部分材质与该穿孔201底部201a的第一绝缘层21,并保留该穿孔201底部201a的金属材240,使该导电穿孔24’的第二端面24b’外露,而使该金属材240封盖该导电穿孔24’的第二端面24b’的中空处。As shown in FIG. 3B, part of the material of the second surface 20b of the substrate 20 and the first insulating layer 21 at the bottom 201a of the through hole 201 are removed, and the metal material 240 at the bottom 201a of the through hole 201 is retained, so that the conductive through hole 24' The second end surface 24b' of the conductive through hole 24' is exposed, so that the metal material 240 covers the hollow of the second end surface 24b' of the conductive through hole 24'.
如图3C所示,于该基板20的第二表面20b’上形成一电性隔离层26,且于该电性隔离层26上形成一电性连接该导电穿孔24’的第二端面24b’的第二线路层23b。最后,于该电性隔离层26与该第二线路层23b上形成一第二保护层25b。As shown in FIG. 3C, an electrical isolation layer 26 is formed on the second surface 20b' of the substrate 20, and a second end surface 24b' electrically connected to the conductive through hole 24' is formed on the electrical isolation layer 26. The second circuit layer 23b. Finally, a second protection layer 25b is formed on the electrical isolation layer 26 and the second wiring layer 23b.
请参阅图4A至图4C,其为本发明的穿孔中介板2”的制法的第三实施例的剖视示意图。本实施例与第一实施例的差异仅在于导电穿孔24”的结构,其它相关工艺均相同,所以相同部分在此不再赘述。Please refer to FIG. 4A to FIG. 4C , which are cross-sectional schematic diagrams of the third embodiment of the manufacturing method of the perforated interposer 2 ″ of the present invention. The difference between this embodiment and the first embodiment lies in the structure of the conductive through hole 24 ″, Other related processes are the same, so the same parts will not be repeated here.
如图4A所示,其于图2E的工艺中,于该第二绝缘层22上形成一第一线路层23a,且于该穿孔201中填满该金属材240以形成导电穿孔24”,使该第一绝缘层21、第二绝缘层22及金属材240填满该导电穿孔24”。As shown in FIG. 4A, in the process of FIG. 2E, a first circuit layer 23a is formed on the second insulating layer 22, and the metal material 240 is filled in the through hole 201 to form a conductive through hole 24", so that The first insulating layer 21, the second insulating layer 22 and the metal material 240 fill the conductive through hole 24".
如图4B所示,移除该基板20的第二表面20b的部分材质,令该导电穿孔24”的第二端面24b”与该基板20的第二表面20b’齐平。As shown in FIG. 4B , part of the material of the second surface 20b of the substrate 20 is removed, so that the second end surface 24b ″ of the conductive through hole 24 ″ is flush with the second surface 20b′ of the substrate 20 .
如图4C所示,于该基板20的第二表面20b’上形成一电性隔离层26,且于该电性隔离层26上形成一电性连接该导电穿孔24”的第二端面24b”的第二线路层23b。最后,于该电性隔离层26与该第二线路层23b上形成一第二保护层25b。As shown in FIG. 4C, an electrical isolation layer 26 is formed on the second surface 20b' of the substrate 20, and a second end surface 24b" electrically connected to the conductive through hole 24" is formed on the electrical isolation layer 26. The second circuit layer 23b. Finally, a second protection layer 25b is formed on the electrical isolation layer 26 and the second wiring layer 23b.
因此,本发明提供一种穿孔中介板2,2’,2”,其包括:具有相对的第一表面20a与第二表面20b’的基板20、设于该基板20中的导电穿孔24,24’,24”、设于该基板20的第一表面20a上的第一线路层23a、设于该基板20的第一表面20a与该第一线路层23a上的第一保护层25a、设于该基板20的第二表面20b’上的电性隔离层26、设于该电性隔离层26上的第二线路层23b、以及设于该电性隔离层26与第二线路层23b上的第二保护层25b。Therefore, the present invention provides a perforated interposer 2, 2', 2", which includes: a substrate 20 having an opposite first surface 20a and a second surface 20b', conductive through holes 24, 24 disposed in the substrate 20 ', 24", the first circuit layer 23a provided on the first surface 20a of the substrate 20, the first protection layer 25a provided on the first surface 20a of the substrate 20 and the first circuit layer 23a, provided on The electrical isolation layer 26 on the second surface 20b' of the substrate 20, the second circuit layer 23b disposed on the electrical isolation layer 26, and the electrical isolation layer 26 and the second circuit layer 23b. The second protective layer 25b.
所述的基板20为硅基板,其具有由该环形孔200与穿孔201构成的穿孔结构,且该第一表面20a上具有一第一绝缘层21与形成于该第一绝缘层21上的一第二绝缘层22,其中,该第一与第二绝缘层21,22的材质不相同,如该第一绝缘层21为硬质材,而该第二绝缘层22为软质材。The substrate 20 is a silicon substrate, which has a perforation structure composed of the annular hole 200 and the through hole 201, and the first surface 20a has a first insulating layer 21 and a layer formed on the first insulating layer 21. The second insulating layer 22, wherein the materials of the first and second insulating layers 21 and 22 are different, for example, the first insulating layer 21 is made of hard material, while the second insulating layer 22 is made of soft material.
所述的导电穿孔24,24’,24”形成于该穿孔结构中且连通该基板20的第一及第二表面20a,20b’,并具有对应该第一表面20a的第一端面24a,24a”与对应该第二表面20b’的第二端面24b,24b’,24b”,又该第一与第二绝缘层21,22还延伸至该穿孔结构中以作为该导电穿孔24,24’,24”的孔壁结构,令一金属材240设于该穿孔结构中的第二绝缘层22上。The conductive through holes 24, 24', 24" are formed in the through hole structure and communicate with the first and second surfaces 20a, 20b' of the substrate 20, and have first end surfaces 24a, 24a corresponding to the first surface 20a "and corresponding to the second end surface 24b, 24b', 24b" of the second surface 20b', and the first and second insulating layers 21, 22 also extend into the through-hole structure as the conductive through-hole 24, 24', 24" hole wall structure, so that a metal material 240 is disposed on the second insulating layer 22 in the through hole structure.
所述的第一线路层23a设于该基板20的第一表面20a上的第二绝缘层22上,且电性连接该导电穿孔24,24’,24”的第一端面24a,24a”。The first circuit layer 23a is disposed on the second insulating layer 22 on the first surface 20a of the substrate 20, and is electrically connected to the first end surfaces 24a, 24a" of the conductive through holes 24, 24', 24".
所述的第一保护层25a还设于该基板20的第一表面20a上的第二绝缘层22上。The first protective layer 25 a is also disposed on the second insulating layer 22 on the first surface 20 a of the substrate 20 .
所述的电性隔离层26覆盖该导电穿孔24,24’,24”中的第一与第二绝缘层21,22,以露出该导电穿孔24,24’,24”的部分第二端面24b,24b’,24b”。The electrical isolation layer 26 covers the first and second insulating layers 21, 22 in the conductive through holes 24, 24', 24", so as to expose part of the second end surface 24b of the conductive through holes 24, 24', 24". , 24b', 24b".
所述的第二线路层23b电性连接该导电穿孔24,24’,24”的第二端面24b,24b’,24b”。The second circuit layer 23b is electrically connected to the second end surfaces 24b, 24b', 24b" of the conductive through holes 24, 24', 24".
此外,于第一与第二实施例中,所述的导电穿孔24,24’为中空状,使该第一保护层25a填充于该导电穿孔24,24’中。例如,于第一实施例中,该第一保护层25a连通该导电穿孔24的第一端面24a与第二端面24b,而于第二实施例中,该金属材240封盖该导电穿孔24’的第二端面24b’的中空处。In addition, in the first and second embodiments, the conductive through holes 24, 24' are hollow, so that the first protective layer 25a is filled in the conductive through holes 24, 24'. For example, in the first embodiment, the first protective layer 25a connects the first end surface 24a and the second end surface 24b of the conductive through hole 24, and in the second embodiment, the metal material 240 covers the conductive through hole 24' The hollow of the second end face 24b'.
另外,于第三实施例中,该第一绝缘层21、第二绝缘层22及金属材240填满该导电穿孔24”。In addition, in the third embodiment, the first insulating layer 21, the second insulating layer 22 and the metal material 240 fill up the conductive through hole 24".
请参阅图5A至图5H,其为本发明的穿孔中介板3的制法的第四实施例的剖视示意图。本实施例与第一实施例的差异仅在于基板30的第一表面30a上的结构,其它相关工艺均相同,所以相同部分在此不再赘述。Please refer to FIG. 5A to FIG. 5H , which are schematic cross-sectional views of a fourth embodiment of the manufacturing method of the perforated interposer 3 of the present invention. The difference between this embodiment and the first embodiment lies only in the structure on the first surface 30 a of the substrate 30 , and other related processes are the same, so the same parts will not be repeated here.
如图5A所示,提供一如图2B的结构,即于一具有相对的第一表面30a与第二表面30b的基板30上形成环形孔300,该环形孔300具有底部300a,且该基板30的第一表面30a与该环形孔300的孔壁上形成一第一绝缘层31,并于该第一绝缘层31上与该环形孔300中形成一第二绝缘层32。As shown in FIG. 5A, a structure as in FIG. 2B is provided, that is, an annular hole 300 is formed on a substrate 30 with opposite first surfaces 30a and second surfaces 30b, the annular hole 300 has a bottom 300a, and the substrate 30 A first insulating layer 31 is formed on the first surface 30 a of the annular hole 300 and a hole wall of the annular hole 300 , and a second insulating layer 32 is formed on the first insulating layer 31 and in the annular hole 300 .
如图5B及图5B’所示,移除该基板30的第一表面30a上的第一绝缘层31与第二绝缘层32,仅保留该环形孔300中的第一绝缘层31与第二绝缘层32。As shown in FIG. 5B and FIG. 5B', the first insulating layer 31 and the second insulating layer 32 on the first surface 30a of the substrate 30 are removed, and only the first insulating layer 31 and the second insulating layer in the annular hole 300 remain. insulating layer 32 .
如图5C所示,于该基板30的第一表面30a上形成一第一电性隔离层36a,且该第一电性隔离层36a具有对应该环形孔300的开孔360,以露出该环形孔300的环内的基板30第一表面30a。As shown in FIG. 5C, a first electrical isolation layer 36a is formed on the first surface 30a of the substrate 30, and the first electrical isolation layer 36a has an opening 360 corresponding to the annular hole 300 to expose the annular The first surface 30a of the substrate 30 within the ring of holes 300 .
如图5D所示,移除该开孔360内的基板30材质,以令该环形孔300形成连通该基板30第一表面30a的穿孔301,该穿孔301具有底部301a,且该第一与第二绝缘层31,32作为该穿孔301的孔壁。As shown in FIG. 5D, the material of the substrate 30 in the opening 360 is removed, so that the annular hole 300 forms a through hole 301 communicating with the first surface 30a of the substrate 30, the through hole 301 has a bottom 301a, and the first and second The two insulating layers 31 and 32 serve as the walls of the through hole 301 .
如图5E所示,于该第一电性隔离层36a上形成一第一线路层33a,且于该穿孔301中电镀金属材340以形成导电穿孔34。接着,于该第一电性隔离层36a与该第一线路层33a上形成一第一保护层35a。As shown in FIG. 5E , a first circuit layer 33 a is formed on the first electrical isolation layer 36 a, and a metal material 340 is plated in the through hole 301 to form a conductive through hole 34 . Next, a first protective layer 35a is formed on the first electrical isolation layer 36a and the first wiring layer 33a.
于本实施例中,该导电穿孔34具有对应该第一表面30a的第一端面34a与对应该第二表面30b的第二端面34b,而该导电穿孔34的第一端面34a电性连接该第一线路层33a,且该穿孔301的底部301a具有该金属材340。In this embodiment, the conductive through hole 34 has a first end surface 34a corresponding to the first surface 30a and a second end surface 34b corresponding to the second surface 30b, and the first end surface 34a of the conductive through hole 34 is electrically connected to the first end surface 34b. A circuit layer 33 a, and the bottom 301 a of the through hole 301 has the metal material 340 .
此外,该导电穿孔34包含有该金属材340、第一及第二绝缘层31,32,且该导电穿孔34为中空状,令该第一保护层35a填充于该导电穿孔34中。In addition, the conductive through hole 34 includes the metal material 340 , the first and second insulating layers 31 , 32 , and the conductive through hole 34 is hollow, so that the first protection layer 35 a is filled in the conductive through hole 34 .
如图5F所示,移除该基板30的第二表面30b的部分材质与该穿孔301底部301a的金属材340,令该基板30的第二表面30b’与该导电穿孔34的第二端面34b齐平,以露出该导电穿孔34的第二端面34b。As shown in FIG. 5F, part of the material of the second surface 30b of the substrate 30 and the metal material 340 of the bottom 301a of the through hole 301 are removed, so that the second surface 30b' of the substrate 30 and the second end surface 34b of the conductive through hole 34 flush with each other to expose the second end surface 34b of the conductive through hole 34 .
如图5G所示,于该基板30的第二表面30b’上形成一第二电性隔离层36b,并覆盖该导电穿孔34的第一与第二绝缘层31,32,使该第二电性隔离层36b露出该导电穿孔34的部分第二端面34b。As shown in FIG. 5G, a second electrical isolation layer 36b is formed on the second surface 30b' of the substrate 30, and covers the first and second insulating layers 31, 32 of the conductive through hole 34, so that the second electrical isolation layer 36b The isolation layer 36b exposes part of the second end surface 34b of the conductive through hole 34 .
如图5H所示,于该第二电性隔离层36b上形成一第二线路层33b,且该第二线路层33b电性连接该导电穿孔34的第二端面34b。最后,于该第二电性隔离层36b与该第二线路层33b上形成一第二保护层35b,并于该第一与第二保护层35a,35b上形成多个第一与第二开孔350a,350b,以令该第一与第二线路层33a,33b的部分表面外露于该些第一与第二开孔350a,350b。As shown in FIG. 5H , a second circuit layer 33 b is formed on the second electrical isolation layer 36 b, and the second circuit layer 33 b is electrically connected to the second end surface 34 b of the conductive through hole 34 . Finally, a second protection layer 35b is formed on the second electrical isolation layer 36b and the second circuit layer 33b, and a plurality of first and second openings are formed on the first and second protection layers 35a, 35b. The holes 350a, 350b are used to expose part of the surface of the first and second wiring layers 33a, 33b to the first and second openings 350a, 350b.
请参阅图6A至图6C,为本发明的穿孔中介板3’的制法的第五实施例的剖视示意图。本实施例与第四实施例的差异仅在于保留该穿孔301底部301a的金属材340,其它相关工艺均相同,所以相同部分在此不再赘述。Please refer to FIG. 6A to FIG. 6C , which are schematic cross-sectional views of a fifth embodiment of the manufacturing method of the perforated interposer 3' of the present invention. The difference between this embodiment and the fourth embodiment is only that the metal material 340 at the bottom 301a of the through hole 301 is retained, and other related processes are the same, so the same parts will not be repeated here.
如图6A所示,其为图5E的工艺,于该第一电性隔离层36a上形成一第一线路层33a,且形成该中空状的导电穿孔34’,该穿孔301的底部301a上具有该金属材340。接着,于该第一电性隔离层36a与第一线路层33a上形成一第一保护层35a,且该第一保护层35a填充于该导电穿孔34’中。As shown in FIG. 6A, which is the process of FIG. 5E, a first circuit layer 33a is formed on the first electrical isolation layer 36a, and the hollow conductive through hole 34' is formed, and the bottom 301a of the through hole 301 has a The metal material 340 . Next, a first protective layer 35a is formed on the first electrical isolation layer 36a and the first circuit layer 33a, and the first protective layer 35a is filled in the conductive through hole 34'.
如图6B所示,移除该基板30的第二表面30b的部分材质与该穿孔301底部301a的第一绝缘层31,并保留该穿孔301底部301a的金属材340,使该导电穿孔34’的第二端面34b’外露,而使该金属材340封盖该导电穿孔34’的第二端面34b’的中空处。As shown in FIG. 6B, part of the material of the second surface 30b of the substrate 30 and the first insulating layer 31 at the bottom 301a of the through hole 301 are removed, and the metal material 340 at the bottom 301a of the through hole 301 is retained, so that the conductive through hole 34' The second end surface 34b' of the conductive through hole 34' is exposed, so that the metal material 340 covers the hollow of the second end surface 34b' of the conductive through hole 34'.
如图6C所示,于该基板30的第二表面30b’上形成一第二电性隔离层36b,且于该第二电性隔离层36b上形成一电性连接该导电穿孔34’的第二端面34b’的第二线路层33b。最后,于该第二电性隔离层36b与第二线路层33b上形成一第二保护层35b。As shown in FIG. 6C, a second electrical isolation layer 36b is formed on the second surface 30b' of the substrate 30, and a second electrical isolation layer 36b electrically connected to the conductive through hole 34' is formed on the second electrical isolation layer 36b. The second circuit layer 33b of the two end faces 34b'. Finally, a second protection layer 35b is formed on the second electrical isolation layer 36b and the second wiring layer 33b.
请参阅图7A至图7C,其为本发明的穿孔中介板3”的制法的第六实施例的剖视示意图。本实施例与第四实施例的差异仅在于导电穿孔34”的结构,其它相关工艺均相同,所以相同部分在此不再赘述。Please refer to FIG. 7A to FIG. 7C , which are cross-sectional schematic diagrams of the sixth embodiment of the manufacturing method of the perforated interposer 3 ″ of the present invention. The difference between this embodiment and the fourth embodiment lies in the structure of the conductive through hole 34 ″, Other related processes are the same, so the same parts will not be repeated here.
如图7A所示,其于图5E的工艺中,于该第一电性隔离层36a上形成一第一线路层33a,且于该穿孔301中填满该金属材340以形成导电穿孔34”,使该第一绝缘层31、第二绝缘层32及金属材340填满该导电穿孔34”。As shown in FIG. 7A, in the process of FIG. 5E, a first circuit layer 33a is formed on the first electrical isolation layer 36a, and the metal material 340 is filled in the through hole 301 to form a conductive through hole 34". , so that the first insulating layer 31, the second insulating layer 32 and the metal material 340 fill the conductive through hole 34".
如图7B所示,移除该基板30的第二表面30b的部分材质与该穿孔301底部301a的第一绝缘层31,令该导电穿孔34”的第二端面34b”与该基板30的第二表面30b’齐平。As shown in FIG. 7B, part of the material of the second surface 30b of the substrate 30 and the first insulating layer 31 of the bottom 301a of the through hole 301 are removed, so that the second end surface 34b" of the conductive through hole 34" is connected to the second end surface 34b" of the substrate 30. The two surfaces 30b' are flush with each other.
如图7C所示,于该基板30的第二表面30b’上形成一第二电性隔离层36b,且于该第二电性隔离层36b上形成一电性连接该导电穿孔34”的第二端面34b”的第二线路层33b。最后,于该第二电性隔离层36b与第二线路层33b上形成一第二保护层35b。As shown in FIG. 7C, a second electrical isolation layer 36b is formed on the second surface 30b' of the substrate 30, and a first electrically connected conductive through hole 34" is formed on the second electrical isolation layer 36b. The second circuit layer 33b on the two end faces 34b". Finally, a second protection layer 35b is formed on the second electrical isolation layer 36b and the second wiring layer 33b.
因此,本发明提供另一种穿孔中介板3,3’,3”,其包括:具有相对的第一表面30a与第二表面30b’的基板30、设于该基板30中的导电穿孔34,34’,34”、设于该基板30的第一表面30a上的第一电性隔离层36a、设于该第一电性隔离层36a上的第一线路层33a、设于该第一电性隔离层36a与第一线路层33a上的第一保护层35a、设于该基板30的第二表面30b’上的第二电性隔离层36b、设于该第二电性隔离层36b上的第二线路层33b、以及设于该第二电性隔离层36b与第二线路层33b上的第二保护层35b。Therefore, the present invention provides another perforated interposer 3, 3', 3", which includes: a substrate 30 having opposite first surfaces 30a and second surfaces 30b', conductive through holes 34 disposed in the substrate 30, 34', 34", the first electrical isolation layer 36a disposed on the first surface 30a of the substrate 30, the first circuit layer 33a disposed on the first electrical isolation layer 36a, the first electrical isolation layer 33a disposed on the first electrical isolation layer The isolation layer 36a and the first protective layer 35a on the first wiring layer 33a, the second electrical isolation layer 36b on the second surface 30b' of the substrate 30, the second electrical isolation layer 36b on the second surface The second circuit layer 33b, and the second protection layer 35b disposed on the second electrical isolation layer 36b and the second circuit layer 33b.
所述的基板30为硅基板,且具有由该环形孔300与穿孔301构成的穿孔结构。The substrate 30 is a silicon substrate and has a perforation structure composed of the annular hole 300 and the through hole 301 .
所述的导电穿孔34,34’,34”形成于该穿孔结构中且连通该基板30的第一及第二表面30a,30b’,并具有对应该第一表面30a的第一端面34a,34a”与对应该第二表面30b’的第二端面34b,34b’,34b”,且该穿孔结构的孔壁上依序具有一第一绝缘层31、一第二绝缘层32及一金属材340。其中,该第一与第二绝缘层31,32的材质并不相同,如该第一绝缘层31为硬质材,而该第二绝缘层32为软质材。The conductive through holes 34, 34', 34" are formed in the through hole structure and communicate with the first and second surfaces 30a, 30b' of the substrate 30, and have first end faces 34a, 34a corresponding to the first surface 30a "and the second end surface 34b, 34b', 34b" corresponding to the second surface 30b', and the hole wall of the perforated structure has a first insulating layer 31, a second insulating layer 32 and a metal material 340 in sequence Wherein, the materials of the first and second insulating layers 31 and 32 are different, for example, the first insulating layer 31 is made of hard material, while the second insulating layer 32 is made of soft material.
所述的第一电性隔离层36a覆盖该导电穿孔34,34’,34”的第一与第二绝缘层31,32,以露出该导电穿孔34,34’,34”的第一端面34a,34a”。The first electrical isolation layer 36a covers the first and second insulating layers 31, 32 of the conductive through holes 34, 34', 34", so as to expose the first end faces 34a of the conductive through holes 34, 34', 34". , 34a".
所述的第一线路层33a电性连接该导电穿孔34,34’,34”的第一端面34a,34a”。The first circuit layer 33a is electrically connected to the first end faces 34a, 34a" of the conductive through holes 34, 34', 34".
所述的第二电性隔离层36b覆盖该导电穿孔34,34’,34”的第一与第二绝缘层31,32,以露出该导电穿孔34,34’,34”的部分第二端面34b,34b’,34b”。The second electrical isolation layer 36b covers the first and second insulating layers 31, 32 of the conductive through holes 34, 34', 34", so as to expose part of the second end surface of the conductive through holes 34, 34', 34". 34b, 34b', 34b".
所述的第二线路层33b电性连接该导电穿孔34,34’,34”的第二端面34b,34b’,34b”。The second circuit layer 33b is electrically connected to the second end surfaces 34b, 34b', 34b" of the conductive through holes 34, 34', 34".
此外,于第四与第五实施例中,所述的导电穿孔34,34’为中空状,使该第一保护层35a填充于该导电穿孔34,34’中。例如:于第四实施例中,该第一保护层35a连通该导电穿孔34的第一端面34a与第二端面34b,而于第五实施例中,该金属材340封盖该导电穿孔34’的第二端面34b’的中空处。In addition, in the fourth and fifth embodiments, the conductive through holes 34, 34' are hollow, so that the first protection layer 35a is filled in the conductive through holes 34, 34'. For example: in the fourth embodiment, the first protective layer 35a connects the first end surface 34a and the second end surface 34b of the conductive through hole 34, and in the fifth embodiment, the metal material 340 covers the conductive through hole 34' The hollow of the second end surface 34b' of the.
另外,于第六实施例中,该第一绝缘层31、第二绝缘层32及金属材340填满该导电穿孔34”。In addition, in the sixth embodiment, the first insulating layer 31 , the second insulating layer 32 and the metal material 340 fill up the conductive through hole 34 ″.
综上所述,本发明的穿孔中介板,主要借由该导电穿孔的孔壁上具有两种绝缘材,以具有更佳防漏电与耐高电压特性,且提高绝缘性及提升电性传导的可靠度。To sum up, the perforated interposer of the present invention mainly has two kinds of insulating materials on the hole wall of the conductive perforation, so as to have better leakage prevention and high voltage resistance characteristics, and improve insulation and electrical conductivity. reliability.
此外,本发明的穿孔中介板为低成本的制作技术,所以利于量产。In addition, the perforated interposer of the present invention is a low-cost manufacturing technology, so it is beneficial to mass production.
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。The above-mentioned embodiments are only used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.
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