CN103218207A - Microprocessor instruction processing method and system based on single/dual transmitting instruction set - Google Patents
Microprocessor instruction processing method and system based on single/dual transmitting instruction set Download PDFInfo
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Abstract
The invention relates to a microprocessor instruction processing method and system based on a single/dual transmitting instruction set. The processing method comprises the following steps of reading an instruction from a memory according to the address of the instruction, and the instruction comprises a marking position indicating the instruction to be a single transmitting instruction or a dual transmitting instruction; carrying out decoding on the read instruction, obtaining a decoding result of the marking position, an operating code and an operating number, and according to the marking position, determining the instruction to be the single transmitting instruction or the dual transmitting instruction; if the instruction is determined to be the single transmitting instruction, finishing the operation of the single transmitting instruction in a first assembly line, if the instruction is determined to be the dual transmitting instruction, finishing the first operation in the dual transmitting instruction in the first assembly line, finishing the second operation of the dual transmitting instruction in a second assembly line, and the first assembly line and the second assembly line operate in parallel in the same manner; and writing the operation results of the first assembly line and the second assembly line back to a register.
Description
Technical field
The present invention relates to the command processing method and the system of microprocessor, particularly based on microprocessor instruction disposal route and the system of mixing single transmit/pair firing order collection.
Background technology
In the basic framework of microprocessor, the instruction process process of carrying out in an instruction cycle mainly comprises steps such as instruction addressing, instruction are read, instruction decode, read operation number, computing, result write back.Traditional microprocessor based on the single transmit instruction is only carried out once-through operation in the process of handling an instruction.Though in fact a lot of computings can parallel processing, but because arithmetic unit ALU is only carried out the restriction of once-through operation and can't be realized in one-period, therefore ALU becomes the bottleneck of conventional microprocessor efficient, makes that the work efficiency of this traditional microprocessor based on the single transmit instruction is lower.
In order to improve the work efficiency of microprocessor, two firing order technology have been proposed at present.The notion of two emissions is, each bar instruction can be read four operands, carries out the computing of two differences (also may be identical), and present high-end processor is generally all supported pair firing orders, even pilosity penetrates finger, makes microprocessor work efficient improve greatly.
The instruction process mode of existing microprocessor based on two firing orders mainly contains following several:
First kind of mode is that every instruction still only comprises a computing, in the process of instruction process, instruction process system reads two instructions simultaneously, whether calculate these two instructions by hardware according to the dependence between two instructions can carry out temporarily simultaneously, if result calculated for carrying out simultaneously, then writes two streamlines respectively with two instructions.Put upside down owing to precedence may occur in the process that two instructions are carried out respectively in two streamlines, therefore after two streamlines are finished computing respectively, resequence, carry out writing back of result again two operation results.The problem of this processing mode is to implement more complicated, in links such as instruction calculating of dependence and rearrangements as a result, all can introduce quite huge logical complexity and hardware spending.
The second way is to realize single transmit or two emission in an instruction, that is to say, in instruction set, comprise single transmit instruction and two two kinds of instructions of firing order, distinguish this two kinds of instructions by extra state variable, that is to say that revising this state variable by program in the application of microprocessor, to indicate the current instruction of microprocessor be single transmit instruction or two firing order.In the prior art, the ARM series microprocessor is based on the typical micro-processor of this mode work, and its pair firing order is the repertoire of support microcontroller also, and purpose is in order to save the instruction space.This mode makes that the hardware configuration of microprocessor is simple relatively, but software programming is very complicated.Because between single transmit/pair firing order is not dynamic switching, thereby but need handle single transmit and two firing order with the different logic of two covers by the state of revising microprocessor, therefore next bar instruction of microprocessor is single transmit instruction or two firing order to need explicit telling, this makes the programming complexity of microprocessor increase greatly.And, promptly realize the repertoire of microprocessor respectively because single transmit instruction and two firing order all are complete or collected works, and cause two streamlines all will realize whole instructions, that is to say that all operations all will repeat twice.And, because instruction number is huge, cause order number (operational code) field very long, compressed address field, the space of other fields such as digital section immediately, this has just limited microprocessor performance in other respects.For example typical A RM microprocessor causes register field to reduce because instruction field takies than large space, makes the register degree of depth can only support 16.
This shows, be difficult to get both between performance and cost/power consumption, is the crucial limitation of conventional microprocessor.Especially in certain applications such as graphics process or multimedia processing, need a kind of high-performance, low cost, low-power consumption, low instruction process system and the method for using the novel microprocessor of complexity.
Summary of the invention
The present invention proposes a kind of based on the microprocessor instruction disposal system of mixing single transmit/pair firing order collection, problems of the prior art have been solved, reduced the instruction field space by asymmetric single transmit/pair firing order collection setting, simplify single transmit/pair firing order handover mechanism by the static state switching, greatly reduced hardware cost and programming complexity.
Utilize the microprocessor of microprocessor instruction disposal route of the present invention and device design, have low cost, low-power consumption, the advantage of high treatment efficiency is under 40nm technology, with less than 0.03mm
2Chip area, can realize surpassing the frequency of operation of 1Ghz and the instruction execution speed of about 1.5Mips/Mhz.
According to an aspect of the present invention, proposed a kind of microprocessor instruction disposal route, having comprised:
The instruction read step according to the address of instruction, reads an instruction from storer, comprise the flag that the described instruction of indication is single transmit instruction or two firing orders in the wherein said instruction;
The instruction decode step is deciphered the instruction of being read, and obtains to comprise the decode results of described flag, operational code, operand, according to described flag, determines that described instruction is single transmit instruction or two firing order;
Calculation step: be the single transmit instruction if determine this instruction, then in first-class waterline, finish the operation of this single transmit instruction, be two firing orders if determine this instruction, then in first-class waterline, finish the operation of first in this pair firing order, in second streamline, finish second operation of this pair firing order, first-class waterline and the parallel running in an identical manner of second streamline;
Write back step: the operation result of described first-class waterline and the operation result of described second streamline are write back to register.
Preferably, single transmit instruction set that constitutes by the instruction of described single transmit and the partial function of realizing microprocessor by two firing order collection that described pair of firing order constitutes respectively.
Preferably, the routine instruction of frequently using is set to both be realized by the single transmit instruction set, is realized by two firing order collection again; The unconventional instruction of non-frequent use is set to only be realized by the single transmit instruction set, or is only realized by two firing order collection.
Preferably, the described first-class waterline and second streamline can comprise the first order that reads first operand, the second level of reading second operand and the third level that first operand and second operand are carried out computing respectively.
Preferably, if the address of the operation result of the address of the operation result of first-class waterline and second streamline clashes, then two operation results are carried out inclusive-OR operation.
According to a further aspect in the invention, proposed a kind of microprocessor instruction disposal system, having comprised:
Register, storage comprises instruction, operand, the data of operation result;
The instruction reading device according to the address of instruction, reads an instruction from storer, comprise the flag that the described instruction of indication is single transmit instruction or two firing orders in the wherein said instruction;
Instruction decoding device is deciphered the instruction of being read, and obtains to comprise the decode results of described flag, operational code, operand, according to described flag, determines that described instruction is single transmit instruction or two firing order;
The instruction flow line line apparatus, comprise the first-class production line apparatus and second flow-line equipment, be the single transmit instruction if wherein determine this instruction, then in this first-class production line apparatus, finish the operation of this single transmit instruction, be two firing orders if determine this instruction, then finish the operation of first in this pair firing order in first-class waterline, finish second operation of this pair firing order in second streamline, the first-class production line apparatus and second flow-line equipment are with identical mode parallel running;
Write return device, the operation result of described first-class waterline and the operation result of described second streamline are write back to register.
Preferably, described instruction reading device is realized by programmable counter, address register and order register.
Preferably, described first-class production line apparatus comprises the first order that is made of first working storage, the second level that is made of second working storage and the third level that is made of first arithmetic device; Described second streamline comprises the first order that is made of the 3rd working storage, the second level that is made of the 4th working storage and the third level that is made of second arithmetic device.
Preferably, if determining described instruction is the single transmit instruction, the first operand of reading command in described first working storage then, the second operand of reading command in described second working storage is carried out computing to first operand and second operand in described first arithmetic device; If determining described instruction is two firing orders, then in described first working storage first of reading command the operation first operand, the second operand of first of the reading command operation in described second working storage is carried out computing to the first operand of first operation and the second operand of first operation in first arithmetic device; The first operand of second of the reading command operation in described the 3rd working storage, the second operand of second of the reading command operation in described the 4th working storage is carried out computing to the first operand of second operation and the second operand of second operation in second arithmetic device.
Preferably, the described return device of writing comprises first working storage and be connected in second working storage as a result of second arithmetic device as a result that is connected in first arithmetic device, stores the operation result of two arithmetical unit respectively, and writes back to appropriate address in the register by bus.
Description of drawings
Fig. 1 is the process flow diagram of microprocessor instruction disposal route of the present invention;
Fig. 2 a and Fig. 2 b are the order code topology examples of single transmit instruction according to an embodiment of the invention and two firing orders;
Fig. 3 is the structural drawing of a kind of microprocessor instruction disposal system of the present invention;
Fig. 4 is the structural drawing of a preferred embodiment of instruction process system of the present invention;
Fig. 5 is the structural drawing of flow-line equipment according to a preferred embodiment of the present invention.
Embodiment
The present invention proposes a kind of based on new microprocessor instruction disposal route and the system of mixing single transmit/pair firing order collection.
Fig. 1 is the process flow diagram of microprocessor instruction disposal route of the present invention, mainly comprises:
The instruction read step according to the address of instruction, reads an instruction from storer, comprise the flag that the described instruction of indication is single transmit instruction or two firing orders in the wherein said instruction;
The instruction decode step is deciphered the instruction of being read, and obtains to comprise the decode results of described flag, operational code, operand, according to described flag, determines that described instruction is single transmit instruction or two firing order;
Calculation step: be the single transmit instruction if determine this instruction, then in first-class waterline, finish the operation of this single transmit instruction, be two firing orders if determine this instruction, then in first-class waterline, finish the operation of first in this pair firing order, finish second operation of this pair firing order in second streamline, the first-class waterline and second streamline are with identical mode parallel running;
Write back step: the operation result of described first-class waterline and the operation result of described second streamline are write back to register.
Be different from traditional mixing single transmit/pair firing order mode set, asymmetrical design has been got in single transmit instruction set and two firing order centralized procurement related in the command processing method of the present invention, that is to say, single transmit instruction set and two firing order collection are not all functions of finishing microprocessor respectively, but realize the partial function of microprocessor respectively, finish all functions of microprocessor by the function summation of single transmit instruction set and two firing order collection.In a preferred embodiment of the invention, the instruction of microprocessor can be divided according to such principle:
-frequent routine the instruction of using, arithmetic operator instruction for example commonly used, logic instruction, read/write memory instruction, bit manipulation instruction etc. had both been supported by the single transmit instruction set, were supported by two firing order collection again;
The unconventional instruction that-frequency of utilization is low but necessary, for example jump instruction etc. is only supported in the single transmit instruction set, or only concentrates at two firing orders and support.
Such distribution principle, make that the quantity of two firing orders is less relatively, therefore under the prerequisite of supporting two emissions, reduced the length of opcode field, make instruction process system according to the present invention when having improved treatment effeciency, still can support very big register array, improve combination property.
In the present invention, be not to instruct by the single transmit of calculating bordering compounding as prior art to form two firing orders, neither in programming process, distinguish this two kinds of instructions by extra state variable, on the contrary, in command processing method of the present invention, make that every instruction all is an independent event, a flag (a for example time high position) is set in every instruction, independent decode results according to every instruction is discerned this flag, thereby determines that it is the still two firing orders of single transmit instruction.
Fig. 2 a and Fig. 2 b are the order code topology examples of single transmit instruction according to an embodiment of the invention and two firing orders, in Fig. 2 a, provided the order code structure of single transmit instruction, it is from left to right by flag, operational code, operand 1, operand 2, other Optional Fields etc. partly constitute, wherein flag is indicated this instruction for " 0 " and is that single transmit instructs, among Fig. 2 b, provided the order code structure of two firing orders, it is flag from left to right, first operational code, operand 1, operand 2, second operational code, operand 3, operand 4, other Optional Fields etc. partly constitute, and wherein flag is that " 1 " indicates this instruction to be two firing orders.This pair firing order can be finished first operation and second operation that is comprised simultaneously.
Angle from hardware, because the present invention does not introduce the mechanism of dynamic assignment in two or more streamlines, but according to decode results schedule of apportionment firing order and two firing orders statically, this method has been avoided extra hardware burden, make hardware cost descend greatly, angle from upper layer application, method of the present invention makes the program space in full accord, do not need special definition when to be single transmit instruction or two firing order in the programming of upper strata, switching between single transmit instruction and the two firing order is fully transparent for upper layer software (applications), and this just greatly reduces the programming complexity in the application.
Be example with the jump instruction below, the contribution of asymmetric mechanism of the present invention aspect the reduction hardware cost is described.When carrying out jump routine, need determine whether redirect according to sign FLAG, when for example realizing the program of " then redirect when a＞b ", according to the conventional process mode, in the streamline of two symmetries, all introduce FLAG, in order to distinguish produced simultaneously FLAG on two streamlines, just must the log history condition decide follow-up state transitions, logic is very complicated, this situation is very rare in the operational process of microprocessor, but, must introduce very big hardware spending in order to solve this rare problem.By contrast, the present invention only upgrades FLAG in a streamline therein, no longer needs to carry out the differentiation of two FLAG on the streamline, and this makes The pipeline design independent simple, has reduced hardware cost.
If through after the instruction decode, the flag that obtains indicates this instruction to be the single transmit instruction, then finish the operation of this single transmit instruction in first-class waterline, for example in typical micro-processor architecture, first-class waterline can comprise the first order: read first operand; The second level: read second operand; And the third level: computing obtains operation result.
If through after the instruction decode, the flag that obtains indicates this instruction to be two firing orders, then in first-class waterline, finish the operation of first in this pair firing order, finish second operation of this pair firing order in second streamline, the first-class waterline and second streamline are with identical mode parallel running.
In most situations of microprocessor work, the result's that two arithmetical unit ALU in two streamlines produce the address that writes back is different, therefore can simply two operation results be write back simultaneously in the register address separately.In a preferred embodiment of the invention, consider in particular cases at the utmost point, if the address of two operation results clashes, then two results are carried out " or " the OR computing, by this simple logical process, make that the operation in two streamlines all partly comes into force.
Fig. 3 is the structural drawing of a kind of microprocessor instruction disposal system of the present invention, mainly comprises:
Register 301, storage comprises instruction, operand, the data of operation result;
Instruction flow line line apparatus 304, comprise the first-class production line apparatus 3041 and second flow-line equipment 3042, be the single transmit instruction if wherein determine this instruction, then in this first-class production line apparatus, finish the operation of this single transmit instruction, be two firing orders if determine this instruction, then in first-class waterline, finish the operation of first in this pair firing order, finish second operation of this pair firing order in second streamline, the first-class production line apparatus and second flow-line equipment are with identical mode parallel running;
Write return device 305: the operation result of described first-class waterline and the operation result of described second streamline are write back to register.
Fig. 4 is the structural drawing of a preferred embodiment of instruction process system of the present invention, the preferred embodiment is based on typical microprocessor architecture design, wherein instruct reading device to realize by programmable counter PC, address register ITCM and order register INS, programmable counter PC is used to deposit and indicate the address of the instruction that will carry out, address register is used for preserving the address of PC, order register is used for temporarily depositing the instruction of taking out according to the address, waits to be decoded.
Instruction decoding device can be realized by command decoder IND, and it is transformed into order code carries out this and instruct needed electric signal, in the present invention, comprises this instruction of indication in the decode results and is the single transmit instruction or the flag of pair firing orders.
Fig. 5 is the structural drawing of flow-line equipment according to a preferred embodiment of the present invention, and the first-class production line apparatus V-PIPE and the second flow-line equipment U-PIPE can comprise the first order S1 that is made of working storage VR1/UR1 respectively, are used to read first operand; Second level S2 by working storage VR2/UR2 constitutes is used to read second operand, and by the third level S3 that arithmetical unit ALU1/AUL2 constitutes, is used to finish computing.The progression of design flow waterline and be not limited to the mode that present embodiment provides as required.In the present invention, be the single transmit instruction if determine this instruction, then in this first-class production line apparatus, finish the operation of this single transmit instruction, be first operand to the first working storage VR1 of reading command, second operand to the second working storage VR2 of reading command, and in first arithmetic device, first and second operands are calculated, obtain operation result.Be two firing orders if determine this instruction, then in first-class waterline, finish the operation of first in this pair firing order, the first operand that promptly reads first operation is to working storage VR1, read first second operand of operating to working storage VR2, and in first arithmetic device ALU1, these two operands are carried out computing; Finish second operation of this pair firing order in second streamline, the first operand that promptly reads second operation reads second second operand of operating to working storage UR2, and in second arithmetic device ALU2 these two operands is carried out computing to working storage UR1; The first-class production line apparatus and second flow-line equipment are with identical mode parallel running.
Write return device and can comprise two working storages that are connected to first arithmetic device and second arithmetic device, it stores the result of two arithmetical unit respectively, and writes back to appropriate address in the register by bus.
The foregoing description is to be used for illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.So protection scope of the present invention, should be listed as claims of the present invention.
Claims (10)
1. microprocessor instruction disposal route comprises:
The instruction read step according to the address of instruction, reads an instruction from storer, comprise the flag that the described instruction of indication is single transmit instruction or two firing orders in the wherein said instruction;
The instruction decode step is deciphered the instruction of being read, and obtains to comprise the decode results of described flag, operational code, operand, according to described flag, determines that described instruction is single transmit instruction or two firing order;
Calculation step: be the single transmit instruction if determine this instruction, then in first-class waterline, finish the operation of this single transmit instruction, be two firing orders if determine this instruction, then in first-class waterline, finish the operation of first in this pair firing order, in second streamline, finish second operation of this pair firing order, first-class waterline and the parallel running in an identical manner of second streamline;
Write back step: the operation result of described first-class waterline and the operation result of described second streamline are write back to register.
2. microprocessor instruction disposal route according to claim 1, wherein single transmit instruction set that constitutes by the instruction of described single transmit and the partial function of realizing microprocessor by two firing order collection that described pair of firing order constitutes respectively.
3. microprocessor instruction disposal route according to claim 2, wherein,
The routine instruction of frequently using is set to both be realized by the single transmit instruction set, is realized by two firing order collection again;
The unconventional instruction of non-frequent use is set to only be realized by the single transmit instruction set, or is only realized by two firing order collection.
4. microprocessor instruction disposal route according to claim 1, the described first-class waterline and second streamline can comprise the first order that reads first operand, the second level of reading second operand and the third level that first operand and second operand are carried out computing respectively.
5. microprocessor instruction disposal route according to claim 1 if the address of the operation result of the address of the operation result of first-class waterline and second streamline clashes, is then carried out inclusive-OR operation with two operation results.
6. microprocessor instruction disposal system comprises:
Register, storage comprises instruction, operand, the data of operation result;
The instruction reading device according to the address of instruction, reads an instruction from storer, comprise the flag that the described instruction of indication is single transmit instruction or two firing orders in the wherein said instruction;
Instruction decoding device is deciphered the instruction of being read, and obtains to comprise the decode results of described flag, operational code, operand, according to described flag, determines that described instruction is single transmit instruction or two firing order;
The instruction flow line line apparatus, comprise the first-class production line apparatus and second flow-line equipment, be the single transmit instruction if wherein determine this instruction, then in this first-class production line apparatus, finish the operation of this single transmit instruction, be two firing orders if determine this instruction, then finish the operation of first in this pair firing order in first-class waterline, finish second operation of this pair firing order in second streamline, the first-class production line apparatus and second flow-line equipment are with identical mode parallel running;
Write return device, the operation result of described first-class waterline and the operation result of described second streamline are write back to register.
7. microprocessor instruction treating apparatus according to claim 6, described instruction reading device is realized by programmable counter, address register and order register.
8. microprocessor instruction treating apparatus according to claim 6, described first-class production line apparatus comprises the first order that is made of first working storage, the second level that is made of second working storage and the third level that is made of first arithmetic device; Described second streamline comprises the first order that is made of the 3rd working storage, the second level that is made of the 4th working storage and the third level that is made of second arithmetic device.
9. microprocessor instruction treating apparatus according to claim 8, wherein,
If determining described instruction is the single transmit instruction, the first operand of reading command in described first working storage then, the second operand of reading command in described second working storage is carried out computing to first operand and second operand in described first arithmetic device;
If determining described instruction is two firing orders, then in described first working storage first of reading command the operation first operand, the second operand of first of the reading command operation in described second working storage is carried out computing to the first operand of first operation and the second operand of first operation in first arithmetic device; The first operand of second of the reading command operation in described the 3rd working storage, the second operand of second of the reading command operation in described the 4th working storage is carried out computing to the first operand of second operation and the second operand of second operation in second arithmetic device.
10. microprocessor instruction treating apparatus according to claim 6, the described return device of writing comprises first working storage and be connected in second working storage as a result of second arithmetic device as a result that is connected in first arithmetic device, store the operation result of two arithmetical unit respectively, and write back to appropriate address in the register by bus.
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| WO2017016255A1 (en) * | 2015-07-29 | 2017-02-02 | 深圳市中兴微电子技术有限公司 | Parallel processing method and apparatus for multiple launch instructions of micro-engine, and storage medium |
| CN111240747A (en) * | 2020-01-13 | 2020-06-05 | Oppo广东移动通信有限公司 | Instruction generation method, apparatus, test architecture and electronic device |
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