CN103207850B - The transmission system of heterogeneous device - Google Patents

Abstract

A transmission system and method for external equipment and heterogeneous equipment, characterized in that the PCI-E equipment is connected through a USB3.0 interface. The external device includes a USB3.0 interface, a first control module and a microcontroller. The USB3.0 interface is connected to the host, and the USB3.0 interface has multiple first pins and multiple second pins; the first control module is connected to the second pin of the USB3.0 interface, and the first control module Receive the operation signal from the host side; the microcontroller is coupled to the first pin of the USB3.0 interface and the first control module, the microcontroller receives the identification request through the first pin, and the microcontroller generates according to the identification request identify the signal, and send the identification signal to the first control module, so that the external device can operate normally under the correct clock.

Description

Transmission system for heterogeneous equipment

【Technical field】

A transmission system for heterogeneous devices, in particular to a transmission system for heterogeneous devices connected to PCI-E through USB3.0.

【Background technique】

With the rapid development of integrated circuits, the size of the computer can be thinner and smaller and achieve faster computing power. For small computers, the space inside the mainframe will be limited. So minicomputers don't offer expansion with adapter cards. Therefore, if the small computer needs to add other devices, it will be expanded through external connections. Generally speaking, the Universal Serial Bus (USB for short) is an interface of a very mature external device. The characteristic of USB is that it supports hot plug (Hot-Plug) and plug and play (Plug-and-Play). And the USB3.0 interface is also compatible with the old USB2.0 and USB1.1 devices.

With the large and fast transmission requirements, the USB has also developed to the third version (hereinafter referred to as USB3.0). The transmission speed of USB3.0 is increased to 5G (Gigabps). So USB3.0 can provide faster transmission speed. Therefore, some manufacturers propose to convert other transmission interfaces into USB3.0 interfaces. Other heterogeneous devices can be connected to the host side through the USB3.0 interface, so that a single type of interface can achieve the connection of multiple different types of devices. Since the types of other transmission interfaces are different from the USB3.0 interface, they are referred to as heterogeneous devices in this specification. In the patent number M375925 of the Republic of China, an "external system with USB3.0 and PCI-E interface" (hereinafter referred to as the M375925 case) was proposed. The M375925 case allows a device with a peripheral device connection interface (Peripheral Component Interconnect Express, hereinafter referred to as PCI-E) to be connected to a computer through a USB3.0 cable.

M375925 adjusts the transmission pins in the USB3.0 connector, so that the PCI-E electronic device can be connected to the USB3.0 interface through the USB3.0 connector. Although this way can realize the connection of PCI-E device and USB3.0. However, the M375925 solution directly connects the differential voltage pins (D+, D-) of USB3.0 to the reference clock pins (REFCLK+, REFCLK-) of PCI-E. Since the signals transmitted by the clock pin and the differential voltage pin are different, the PCI-E device cannot obtain the corresponding clock. Therefore, in the absence of a correct clock, the PCI-E device will perform a corresponding operation and an erroneous operation result will occur. Therefore, the M375925 case does not actually address the operation of the two protocols at different clocks.

【Content of invention】

The invention provides a transmission system for heterogeneous equipment, which is characterized in that a corresponding type of transmission protocol is selected according to the connected equipment. The heterogeneous device transmission system of the present invention includes a PCI-E device and a host end. The PCI-E device has a first interface, a microcontroller and a first control module, the microcontroller is coupled to the first control module, the first interface has a plurality of first pins and a plurality of second pins; the host end is connected to the PCI-E device, the host end has a second interface and a second control module, and the second interface is correspondingly set on the first interface of the PCI-E device; wherein, when the PCI-E device is connected to the host end, the second The control module is coupled to the microcontroller through the first pin, the second control module is coupled to the first control module through the second pin, and the second control module drives the microcontroller through the first pin The device is used to make the microcontroller send an identification signal to the first control module, and the second control module sends an operation signal to the first control module through the second pin. The present invention also proposes an external device, which is characterized in that it is connected to a PCI-E device through a USB3.0 interface.

The external device, the transmission system of the heterogeneous device and the method thereof of the present invention can provide the correct clock pulse required for the operation of the PCI-E device, so the present invention can fully realize the purpose of hot plugging. The present invention can be connected to USB3.0 equipment through the USB3.0 interface, and can also be connected to PCI-E equipment, so the purpose of saving space can be achieved. Regarding the features and implementation of the present invention, the preferred embodiments are described in detail below in conjunction with the drawings.

【Description of drawings】

Fig. 1 is a structure diagram of the present invention.

FIG. 2 is a schematic diagram of pin configuration of the first interface of the present invention.

Fig. 3 is a schematic diagram of the operation flow of the present invention.

FIG. 4 is a schematic diagram of another operation flow of the present invention.

【detailed description】

Please refer to FIG. 1, which is a structure diagram of the present invention. The heterogeneous device transmission system 100 of the present invention includes a PCI-E device 110 and a host 120 . The PCI-E device 110 has a first interface 111 , a microcontroller 112 (MicroControlUnit, MCU for short), and a first control module 113 (PCI-EHost). The microcontroller 112 is coupled to the first interface 111 and the first control module 113 . Related information and drivers of the PCI-E device 110 can be written into the microcontroller 112 . The first interface 111 includes a plurality of first pins 114 and second pins 115 . For the purpose of backward compatibility, the USB3.0 interface includes USB2.0 pins and USB3.0 pins at the same time. Here, each pin of USB2.0 in the first interface 111 is defined as a first pin 114 , and each pin of USB3.0 is defined as a second pin 115 . The first pin 114 is coupled to the microcontroller 112 and the host 120 . The second pin 115 is coupled to the first control module 113 and the host terminal 120 . The first interface 111 adopts the USB3.0 transmission protocol. The first interface 111 may adopt a USBA type (USBA type) or a USBB type (USBB type).

For the pin configuration used in the first interface 111 of the present invention, please refer to the following, and please refer to FIG. 2 , which is a schematic diagram of the pin configuration of the first interface of the present invention. The first pin is the first pin 114 , which is connected to the power pin (VBus) of USB2.0 and the power pin (Vcc) of PCI-E. The second pin is the first pin 114, which is connected to the differential voltage pin (D-) of USB2.0. The third pin is the first pin 114, which is connected to the differential voltage pin (D+) of USB2.0. The fourth pin is the first pin 114 , which is connected to the ground pin (GND) of USB2.0 and the ground pin (GND) of PCI-E.

The fifth pin is the second pin 115 , which is the receiving pin (RX-) of USB3.0 and the PERn pin (PCIExpressReceiveNegativesignal) of PCI-E. The sixth pin is the second pin 115 , which is connected to the receiving pin (RX+) of USB3.0 and the PERp pin (PCIExpressReceivePositivesignal) of PCI-E. The seventh pin is the second pin 115 , which is connected to the ground pin of USB3.0 and the ground pin of PCI-E. The eighth pin is the second pin 115, which is connected to the USB3.0 transmission pin (TX-) and the PCI-E PETn pin (PCIExpressTransmitNegativesignal). The ninth branch pin is the second pin 115 , which is connected to the transmission pin (TX+) of USB3.0 and the PETp pin (PCIExpressTransmitPositivesignal) of PCI-E.

The host terminal 120 of the present invention may be, but not limited to, a personal computer (Personal Computer), a notebook computer (Notebook) or an all-in-one computer (AllinonePC, AIO for short). The host end 120 includes a second interface 121 and a second control module 122 . The type of the second control module 122 is determined according to the running process of the host terminal 120 . When the host terminal 120 is in the booting process, the second control module 122 is a Basic Input/Output System (BIOS for short), and the second control module 122 can drive the Platform Controller Hub (PlatformControllerHub) to perform corresponding processing. If the host terminal 120 has entered the operating system (Operation System, OS for short), then the second control module 122 is executed by the operating system instead. The second interface 121 also adopts the USB3.0 transmission protocol. Generally speaking, the type of the first interface 111 is relative to the type of the second interface 121 . Alternatively, the present invention can also be connected to the first interface 111 and the second interface 121 through a USB3.0 connection cable (Cable).

The host 120 will have different objects serving as the second control module 122 under different operating environments. In the present invention, the operating environment is divided into the booting process (Booting) and the operating environment. If the host terminal 120 is in the booting process, the control module is under the responsibility of the BIOS. After booting up, the host 120 runs the operating system. Therefore, in the operating system environment, the operating system is responsible for the related processing of the PCI-E device 110 plugging and unplugging detection.

In order to clearly illustrate the operation sequence of the present invention during the booting process, please refer to FIG. 3 , which is a schematic diagram of the operation flow of the present invention. The transmission method of heterogeneous equipment of the present invention comprises the following steps:

Step S310: Connect the expansion device to the second interface of the host;

Step S320: The BIOS determines that the type of the expansion device is a USB3.0 device or a PCI-E device;

Step S330: If the expansion device is a USB3.0 device, the BIOS operates the USB3.0 device;

Step S340: If the expansion device is a PCI-E device, the BIOS drives the microcontroller of the PCI-E device through the first pin of the first interface and generates an identification signal;

Step S350: The BIOS transmits operation signals to the first control module of the PCI-E device through a plurality of second pins of the first interface;

Step S360: Send the identification signal to the first control module; and

Step S370: The first control module performs corresponding operations according to the identification signal and the operation signal.

In order to distinguish the pre-recognition device from the post-recognition device, an unrecognized device at the time of connection is defined as an extended device. The expansion device is connected to the host end 120 through cables or connectors. Since the host terminal 120 is in the power-on state, the role of the second control module 122 is taken over by the BIOS.

The BIOS can confirm the type of expansion device by timing and querying device information. After the BIOS sends the identification request, the BIOS waits for a response from the microcontroller 112 . Since the microcontroller 112 has been loaded with the relevant information of the PCI-E device 110 or the USB3.0 device, the microcontroller 112 will generate a corresponding response signal upon receiving the identification request. If the BIOS receives a response signal from the microcontroller 112 after a predetermined period of time, the BIOS will identify the PCI-E device 110 . If no response signal is received after the preset time period, the BIOS will regard the device connected to the second interface 121 as a USB3.0 device. If it is a USB3.0 device, the BIOS can connect it through the original program.

If the connected expansion device is the PCI-E device 110, the BIOS drives the microcontroller 112 of the PCI-E device 110 through the first pin 114 of the first interface 111 to generate an identification signal. Among them, the types of identification signals include reset signal (Reset), wake-up signal (Wakeup) and sleep signal (Sleep). The identification signal generated by the microcontroller 112 cooperates with the control of the PCI-E device 110 , so the PCI-E device 110 can cooperate with the correct timing when performing operations. The BIOS transmits operation signals to the first control module 113 of the PCI-E device 110 through the plurality of second pins 115 of the first interface 111 . The execution order of steps S350 and S360 is not limited thereto, those skilled in the art may also execute these steps at the same time or exchange the order.

In addition to the aforementioned startup process, the present invention can also be applied to the running of the operating system. When the operating system is running, the BIOS will not control the peripheral hardware. Therefore, when the operating system is running, the operating system assumes the role of the second control module 122 . Please refer to FIG. 4 , which is another schematic diagram of the operation flow of the present invention. This implementation pattern includes the following steps:

Step S410: Connect the expansion device to the second interface of the host;

Step S420: the operating system determines that the type of the expansion device is a USB3.0 device or a PCI-E device;

Step S430: If the expansion device is a USB3.0 device, the operating system operates the USB3.0 device;

Step S440: If the expansion device is a PCI-E device, the operating system drives the microcontroller of the PCI-E device through the first pin of the first interface to generate an identification signal;

Step S450: the operating system transmits operation signals to the first control module of the PCI-E device through the plurality of second pins of the first interface;

Step S460: Send the identification signal to the first control module; and

Step S470: The first control module performs corresponding operations according to the identification signal and the operation signal.

Since the operating system has substantial control over the hardware of the host 120 , the operating system will be used as the second control module 122 after booting. When the operating system detects that a device is connected to the second interface 121 , the operating system will call a related interrupt program. There may be different ways of implementing the interrupt program depending on the type of operating system.

When the expansion device is connected to the host 120 , the operating system will send an identification request to the microcontroller 112 of the PCI-E device 110 through the first pin 114 . If the expansion device receives an identification request, the microcontroller 112 will return a response message to the host 120 . After the operating system receives the response message, the operating system can identify the type of the expansion device according to the response message, and call related interrupt processing to connect the device. Taking Windows OS of Microsoft Corporation as an example, the Windows OS can call a System Management Interrupt (SMI) or a driver to identify and connect the PCI-E device 110 .

Next, the operating system drives the microcontroller 112 of the PCI-E device 110 through the first pin 114 of the first interface 111 and generates an identification signal. The identification signal generated by the microcontroller 112 cooperates with the control of the PCI-E device 110 , so the PCI-E device 110 can cooperate with the correct timing when performing operations. The operating system transmits operation signals to the first control module 113 of the PCI-E device 110 through the plurality of second pins 115 of the first interface 111 . The order of execution of steps S450 and S460 is not limited thereto, those skilled in the art may also execute these steps at the same time or exchange the order.

The transmission system 100 for external devices and heterogeneous devices of the present invention and its method can provide the correct clock needed for the operation of the PCI-E device 110 , so the present invention can fully realize the purpose of hot plugging. In the present invention, the USB3.0 interface can be connected to the USB3.0 device, or the PCI-E device 110 can be connected. Therefore, in addition to achieving the purpose of saving space, the present invention also takes into account the purpose of practicality.

Although the present invention has been disclosed above with the aforementioned preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with similar skills can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of patent protection of the present invention shall be defined by the scope of patent application attached to this specification.

Claims (4)

1. A transmission system of heterogeneous equipment, characterized in that according to the connected equipment and selecting a corresponding type of transmission protocol, the transmission system of this heterogeneous equipment comprises: A PCI-E device has a first interface, a microcontroller and a first control module, the microcontroller is coupled to the first control module, the first interface has a plurality of first pins and a plurality of second pins; and A host end, connected to the PCI-E device, the host end has a second interface and a second control module, the second interface is correspondingly arranged on the first interface of the PCI-E device, and the first The pin arrangement of the interface is as follows: the first pin is the first pin, which connects the power pin of USB2.0 and the power pin of PCI-E; the second pin is the first pin, and its Connect to the differential voltage pin D- of USB2.0; the third pin is the first pin, which is connected to the differential voltage pin D+ of USB2.0; the fourth pin is the first pin, It is connected to the ground pin of USB2.0 and the ground pin of PCI-E; the fifth pin is the second pin, which is connected to the receiving pin RX- of USB3.0 and the PERn pin of PCI-E; The sixth pin is the second pin, which is connected to the receiving pin RX+ of USB3.0 and the PERp pin of PCI-E; the seventh pin is the second pin, which is connected to the ground of USB3.0 The pin and the ground pin of PCI-E; the eighth branch pin is the second pin, which connects the transmission pin TX- of USB3.0 and the PETn pin (PCIExpressTransmitNegativesignal) of PCI-E; the ninth branch pin The pin is the second pin, which is connected to the transmission pin TX+ of USB3.0 and the PETp pin of PCI-E; Wherein, when the PCI-E device is connected to the host, the second control module is coupled to the microcontroller through the first pin, and the second control module is coupled to the microcontroller through the second pin. In the first control module, the second control module drives the microcontroller through the first pins, so that the microcontroller sends an identification signal to the first control module, and the second control module The group sends an operation signal to the first control module through the second pin. 2. The transmission system of heterogeneous devices according to claim 1, wherein the second control module is a BIOS or an operating system. 3. The transmission system for heterogeneous devices as claimed in claim 2, characterized in that during the boot process of the host, the BIOS detects that the type of device connected to the second interface is a USB3.0 device or the PCI- E-equipment. 4. The transmission system for heterogeneous devices as claimed in claim 2, wherein the host runs on the operating system, and the operating system detects that the type of device connected to the second interface is a USB3.0 device or the PCI-E device.