CN103199889B - Field programmable gata array (FPGA) implementation method of iteration frequency domain anti-interference algorithm - Google Patents

Abstract

The invention provides an FPGA implementation method of an iterative frequency-domain anti-jamming algorithm, which performs AD sampling on the down-converted satellite signal to the intermediate frequency and adds a window, selects a suitable threshold optimization coefficient after performing FFT operation, and derives an adaptive iteration threshold , the frequency points whose amplitude in the frequency domain is greater than the threshold are lowered to the threshold value, and finally combined and output after performing IFFT transformation. The invention can self-adaptively set the interference detection threshold, has good dynamic interference suppression ability, avoids the need to occupy hardware resources for storage of intermediate process data due to multiple judgments, and fully utilizes the technology of exchanging FPGA time for resources, greatly reducing consumption of hardware resources.

Description

An FPGA Implementation Method of Iterative Frequency Domain Anti-jamming Algorithm

technical field

The invention relates to a hardware implementation of an anti-jamming algorithm, in particular to an FPGA implementation technology of an iterative threshold-based frequency-domain anti-jamming algorithm, which is used for judging and suppressing interference in a wireless spread spectrum communication system.

Background technique

Wireless communication technology plays an increasingly important role in the field of modern communication, but because the wireless signal is extremely weak, it is vulnerable to various natural or man-made interferences and cannot be used. Therefore, it is necessary to introduce interference suppression technology to improve the resistance of wireless communication systems. Interference ability. Since man-made interference is mostly narrow-band interference, effective narrow-band interference suppression technology can greatly improve the performance of the communication system.

In the anti-interference algorithm, the judgment and suppression of interference is the core part of the whole algorithm. Among them, the notch method is one of the commonly used algorithms. The so-called notch method is to convert the signal from the time domain to the frequency domain, compare the amplitude of the frequency domain with the threshold, and sink the amplitude of the signal frequency point greater than the threshold to complete the interference suppression work.

Document 1 "Suppression of Multiple Narrowband Interference in a Spread Spectrum Communication System [IEEE J, 2000, SAC-18(8), 1347-1356]" discloses several commonly used threshold calculation algorithms, especially the first-order distance threshold algorithm TH=Kμ , where K is the threshold optimization coefficient, and μ is the mean value of the received signal. However, this method uses a fixed threshold, which cannot suppress interference effectively in a dynamic interference environment.

Document 2 "Research on Narrowband Interference Suppression Based on Adaptive Threshold under Low SNR [Electronic Information Countermeasure Technology, pp, 51-53, 2009]" proposes that the spread spectrum signal is approximated as a narrowband Gaussian signal after DFT under the condition of no interference. Its envelope obeys the Rayleigh distribution, and the square of the envelope obeys the exponential distribution. Through the derivation of the exponential distribution probability density formula, it is proposed that when the threshold optimization coefficient K≥8 in the first-order distance threshold algorithm, the useful signal will not be lost under the condition of no interference. At the same time, a segmented interference suppression algorithm is disclosed, which selects different thresholds by calculating the power of the current signal. However, the algorithm is complex and expensive.

Document 3 "A Narrowband Interference Suppression Algorithm and Research on Overlapped and Windowed Frequency Domain [Modern Defense Technology, pp, 4-6, 2010]" proposes an overlapping and windowed narrowband frequency domain interference suppression algorithm. The conclusion of Document 2 is used. According to the characteristic that the envelope square of the narrowband Gaussian signal obeys the exponential distribution, the threshold optimization coefficient K=5 is selected, and the obtained first-order moment threshold is used as the iterative threshold to judge and suppress interference. However, in the process of interference suppression, the algorithm sinks the signal amplitude greater than the threshold to zero. This method will cause loss of useful signals under the condition of narrow-band interference with relatively high interference signal, and it is only applicable to single tone or multi-tone interference, and the specific hardware implementation of the algorithm is not given in this document.

To sum up, many existing literatures use narrow-band Gaussian models for frequency-domain anti-jamming algorithms, and select the decision threshold according to the characteristic that the square of the envelope obeys the exponential distribution. The square value is often very large and will occupy a lot of storage resources, which is undesirable in the actual implementation, and the existing literature fails to provide an FPGA implementation of iterative frequency domain anti-interference for narrowband interference.

Contents of the invention

In order to overcome the deficiencies of the prior art, the present invention proposes an FPGA implementation technology of frequency domain anti-jamming based on first-order distance iterative adaptive threshold. From the point of view that the narrowband Gaussian signal envelope obeys the Rayleigh distribution, select the appropriate threshold optimization coefficient, derive the adaptive iterative threshold, and sink the frequency points whose frequency domain amplitude is greater than the threshold to the threshold value, which can ensure that all useful signals can Through the method, at the same time, the storage resources of the hardware can be greatly reduced, and the interference suppression work can be completed.

The technical solution adopted by the present invention to solve its technical problems comprises the following steps:

(1) The satellite signal down-converted to the intermediate frequency will be AD sampled, and the obtained data will be output in two channels, and one channel will be delayed by 1/2 window length, and the two channels of data will be input to the windowing module respectively;

(2) The windowing module performs windowing operation for the input data. The window function adopts the generalized Hamming window, the window length is L, and the quantization of the 8-bit data bit width is adopted; after the windowing operation is completed, the data is input into the FFT module;

(3) In the FFT module, a RAM with a depth of L is used to check and store the input data, and then the read data is sent to the FFT core for FFT operation. FFT is set to Pipelined, Streaming I/O mode, operating frequency is _fin , and _fin is identical with AD sampling clock, and the output of its operation has two parts of real part Re and imaginary part Im, these two parts are combined by real part in the present invention The modulus R calculated jointly by the part and the imaginary part is combined into one signal according to the high, middle and low positions, namely {Re, Im, R}, and sent to the interference identification and suppression module;

(4) The working process of each interference identification and suppression module is as follows:

a. Establish two dual-port RAM cores RAM1 and RAM2 with a depth of L=512, the data input selection unit selects RAM1 to work, and the data output by FFT is stored in _RAM1 with the clock fin, and at the same time calculate the modulus R in the stored data L point cumulative sum and threshold K is the threshold optimization coefficient;

b. When RAM1 is full, the data input selection unit selects RAM2 to work, and the data output by FFT is stored in RAM2, and the work of calculating the L point accumulation and SUM and threshold value _TH1 of the stored data modulus R in step a is repeated;

c. In the process of RAM2 data storage, the data in RAM1 is read with clock f _s , f _s =N*f _in , N is the number of iterations; available, in this period of time when RAM2 data is stored, it can be The data in RAM1 is read 3 times; a flag register with the same bit width and RAM1 depth is set, and in the process of reading RAM1 for the first time, part of the read data representing the modulus value R _j and TH ₁ For comparison, j=1,2,3...L, if it is greater than TH ₁ , the corresponding position of the flag register is set to 1, that is, flag[j-1]=1 (because the bit width of flag starts from 0, it is necessary to use j-1 indicates the response position of the flag), SUM=SUM-(R _j -TH ₁ ); otherwise flag[j-1]=0, SUM remains unchanged; when the first reading is completed, the latest SUM Calculate the threshold TH ₂ and start reading RAM1 for the second time; compare the read data R _j with TH ₂ , if R _j is greater than the threshold TH ₂ , check whether the corresponding position of the flag is 1 at this time, and if it is 1, then The corresponding position of the flag remains unchanged, SUM=SUM-(TH ₁ -TH ₂ ); otherwise, the corresponding position of the flag is set to 1, SUM=SUM-(R _j -TH ₂ ); if R _j is less than the threshold TH ₂ , the flag is corresponding Both bits and SUM remain unchanged; at the moment when the second reading is completed, the threshold TH ₃ is calculated according to the latest SUM value, and the third reading is started; the third reading reaches N-1; The operation is the same as that of the second reading, until the last reading of data, that is, the Nth reading of data, and the threshold value TH _N can be obtained from the N-1 reading operation. At this time, if the read If the fetched data R _j is greater than TH _N , set the read real part Re _j to TH _N and the imaginary part Im _j to 0 for output, that is, Re _j = TH _N , Im _j =; otherwise, the read real part Part Re _j and imaginary part Im _j data are output as they are;

d. when the data judgment of RAM1 was finished, the data in RAM2 also stored and ended, and now the work of step c was repeated to the data in RAM2, and RAM1 began to store new data;

(5) Input the data output by the interference identification and suppression module to the IFFT module with the clock f _s , where the module stores it through the dual-port RAM and reads it with the clock _fin to complete the conversion of the data rate. The read data is input to the IFFT core, inversely transformed and output;

(6) The outputs of the two IFFT modules are directly added and combined, and sent to the external interface, and the anti-interference work is completed.

The beneficial effects of the present invention are: the FPGA implementation of the iterative threshold-based anti-interference algorithm proposed by the present invention can adaptively set the interference detection threshold in the algorithm, and has good dynamic interference suppression ability. In terms of implementation technology, a high-speed clock is used to realize data reading, judgment and suppression, which avoids the need to occupy hardware resources for storage of intermediate process data due to multiple judgments, and makes full use of the technology of FPGA time in exchange for resources, greatly reducing the need for Consumption of hardware resources.

Description of drawings

Fig. 1 is the FPGA implementation flowchart of the anti-jamming algorithm based on iterative threshold;

Fig. 2 is a flow chart of the interference suppression and judgment module;

Fig. 3 is a schematic diagram of the frequency spectrum and the correlation value of the spread spectrum signal when no interference is added;

Fig. 4 is the frequency spectrum and correlation value schematic diagram of the spread spectrum signal after adding interference;

Figure 5 is a Modelsim simulation diagram of the threshold iteration process;

Fig. 6 is the frequency spectrum and correlation value schematic diagram of the spread spectrum signal after anti-jamming;

Fig. 7 is the RTL diagram realized by FPGA.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

The invention proposes an FPGA implementation technology based on an iterative frequency domain anti-jamming algorithm. Improvements in the algorithm derivation of the adaptive threshold can greatly reduce the consumption of storage resources. In its core module (interference identification and suppression module), ping-pong operation is used to receive data to prevent data overflow processing, and high-speed clock is used to complete RAM data reading and subsequent threshold iterative calculation and interference judgment operations.

(1) Theoretical derivation of the first-order moment iterative threshold algorithm:

Under the condition of no interference, the signal can be expressed as S(k)+N(k), where S(k) represents the useful signal and N(k) represents the noise signal. After N-point DFT transformation, it becomes S(n)+N(n), which is a narrow-band Gaussian signal. The envelope |S(n)+N(n)| of S(n)+N(n) follows a Rayleigh distribution, while the square of the envelope |S(n)+N(n)| ² follows an exponential distribution. Many documents are derived from the probability distribution of the envelope square, and the iteration threshold is given, and the present invention is derived from the distribution of the envelope |S(n)+N(n)|.

Suppose the signal |S(n)+N(n)| obeys the Rayleigh distribution with parameter σ, and its expected value is The probability density function is Choose the first moment threshold value Wherein the threshold optimization coefficient K=1,2,3,4,5. Then the probability of |S(n)+N(n)|<TH

$\mathrm{<span\; class="notranslate">\; P</span>}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; |</span><span\; class="notranslate">\; <</span>\mathrm{<span\; class="notranslate">\; TH</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; \&Integral;</span>}_{\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; TH</span>}}\frac{\mathrm{<span\; class="notranslate">\; xexp</span>}<span\; class="notranslate">\; (</span>\frac{<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}\mathrm{<span\; class="notranslate">\; dx</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; exp</span>}<span\; class="notranslate">\; (</span>\frac{<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; x</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>{<span\; class="notranslate">\; |</span>}_{\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; TH</span>}}$

The probability of different K values can be obtained, as shown in the following table:

Table 1 Probability distribution of different K values

K=1 K=2 K=3 K=4 K=5 0.5441 0.9568 0.9991 1.0000 1.0000

The present invention finally selects K=4, which can ensure that all valid signals can pass through, and at the same time, the selected parameters are suitable for hardware implementation, and the multiplication operation can be realized only by shifting.

When there are many DFT points (N>256), the expected value The statistical mean of the signal can be used instead, i.e. $\frac{1}{N}\underset{\mathrm{no}=1}{\overset{\mathrm{no}=N}{\mathrm{\&Sigma;}}}|S\left(\mathrm{no}\right)+N\left(\mathrm{no}\right)|=\mathrm{\&sigma;}\sqrt{\frac{\mathrm{\&pi;}}{2}},$ The threshold selection work is completed.

The adaptive threshold is to calculate the statistical mean value of the signal multiple times to adaptively change the corresponding threshold value, so that the signal can pass the judgment of the iterative threshold to achieve the effect of interference suppression. For specific methods, please refer to the implementation steps below, which will not be repeated here.

(II) A kind of FPGA realization of the anti-jamming algorithm based on iterative threshold, principle as shown in Figure 1, characteristic steps are as follows:

(1) Divide the data obtained by AD sampling into two channels, one channel is delayed by 1/2 window length (the delay is 256 points in the present invention), and the two channels of data are respectively input to the windowing module.

(2) The windowing module performs windowing operation for the input data. The window function adopts the generalized Hamming window, the window length is 512 points, and the quantization of the 8-bit data bit width is adopted. After the windowing operation is completed, the data is input to the FFT module.

(3) In the FFT module, a RAM with a depth of L (L=512) is used to store the input data, and then the read data is sent to the FFT core for FFT operation. The FFT is set to the flow-type base 2 working mode, the working frequency is _fin , and the output of its operation has two parts, the real part Re and the imaginary part Im. In the present invention, the two-way signals and their modulus R are combined into one according to the high, middle and low bits. The signal, namely {Re, Im, R}, is fed to the interference identification and suppression module.

(4) The interference identification and suppression module is the key implementation part of the present invention, its flow is shown in Figure 2, and the detailed process is as follows:

a. Establish two dual-port RAM cores RAM1 and RAM2 with a depth of L (for example, L=512). The data input selection unit selects RAM1 to work, and the data output by FFT is stored in RAM1 with the clock _fin , and the stored data is calculated at the same time. L-point cumulative sum SUM of modulus R and threshold TH ₁ .

b. When RAM1 is full, the data input unit selects RAM2 to work, and the data output by FFT is stored in RAM2, and the work of calculating the L-point accumulation sum SUM and threshold value _TH1 of the stored data modulus R in step 1 is repeated.

c. In the process of RAM2 data storage, read the data in RAM1 with clock f _s . f _s can be determined according to the required number of iterations, for example, if the number of iterations is 3, then f _s =3*f _in . It can be obtained that the data in RAM1 can be read three times during the period of data storage in RAM2. Set a flag register (such as [511:0]flag) with the same bit width and RAM1 (RAM2) depth. In the process of reading RAM1 for the first time, a part of the read data representing the modulus value R _j (j=0,1,...511) is compared with TH ₁ , if it is greater than TH ₁ , the corresponding position of the flag register is set to 1, that is, flag[j]=1, SUM=SUM-(R _j -TH ₁ ) . Otherwise flag[j]=0, SUM remains unchanged. When the first reading is completed, the threshold TH ₂ is calculated through the latest SUM, and the second reading of RAM1 is started. Compare the read data R _j with TH ₂ , if R _j is greater than the threshold TH ₂ , check whether the corresponding position of the flag is 1, if it is 1, then the corresponding position of the flag remains unchanged, SUM=SUM-(TH ₁ - TH ₂ ); otherwise, the corresponding bit of the flag is set to 1, and SUM=SUM-(R _j -TH ₂ ). If R _j is smaller than the threshold TH ₂ , the corresponding bit of flag and SUM remain unchanged. When the second pass of reading is completed, the threshold TH ₃ is calculated according to the latest SUM value, and the third pass of reading is started. If the read data R _j is greater than TH ₃ , set the read real part Re _j to TH ₃ and the imaginary part Im _j to 0 and output, that is, Re _j = TH ₃ , Im _j = 0; otherwise, read The fetched real part Re _j and imaginary part Im _j data are output as they are.

d. When the data in RAM1 is judged, the data in RAM2 is also stored. At this time, the work of step 3 is repeated for the data in RAM2, and new data is stored in RAM1.

(5) Input the data output by the interference identification and suppression module to the IFFT module with the clock f _s , where the module stores it through the dual-port RAM and reads it with the clock _fin to complete the conversion of the data rate. The read data is input to the IFFT core, inversely transformed and output.

(6) Combine the outputs of the two IFFT modules and send them to the external interface, and the anti-interference work is completed.

Now in conjunction with an actual wireless spread spectrum receiver the present invention is further described:

Hardware platform for algorithm implementation: Xilinx x5v1x155 FPGA chip.

Development and simulation environment: ISE10.1 and Modelsim SE6.5c.

The bandwidth of the spread spectrum signal used is 2MHz, the interference signal is 0.2MHz, and the interference-to-signal ratio is 45dB.

The global clocks of the receiver system are 32MHz and 96MHz. The specific realization adopts three iterations. The data bit width of AD input is 4 bits. The IP core for FFT and IFFT operations adopts a fixed bit width (scaled) mode, that is, the input bit width is 8 bits, and the output real part and imaginary part width are both 8 bits. The RAM cores in the implementation all use a memory depth of 512. Among them, the RAM core bit width in the FFT module is 4 bits; the RAM bit width in the interference suppression and judgment module is 25 bits, and the upper 8 bits store the real part data output by the FFT. 8 bits store the imaginary part data output by FFT, and the lower 9 bits store the modulus value; the RAM core bit width in the IFFT module is 20 bits, the upper 12 bits store the real part data, and the lower 8 bits store the imaginary part data.

The specific steps to achieve are as follows:

(1) Output the data obtained by sampling the satellite signal AD down-converted to the intermediate frequency into two channels, one channel is delayed by 1/2 window length (the delay is 256 points in the present invention), and the two channels of data are respectively input to the windowing module.

(2) The windowing module performs windowing operation for the input data. The window function adopts the generalized Hamming window, the window length is 512 points, and the quantization of the 8-bit data bit width is adopted. After the windowing operation is completed, the data is input to the FFT module.

(3) In the FFT module, a RAM with a depth of 512 is used to check and store the input data, and then the read data is sent to the FFT core for FFT operation. FFT is set to Pipelined, Streaming I/O mode, and its operating frequency is _fin =32MHz ( _fin and AD sampling clock are identical), and the output of its operation has real part Re and imaginary part Im two parts, these two parts are used in the present invention part and the modulus calculated from the real part and the imaginary part together According to the combination of high, medium and low, one signal, namely {Re, Im, R}, is sent to the interference identification and suppression module.

(4) The working process of each interference identification and suppression module is as follows:

a. Establish two dual-port RAM cores RAM1 and RAM2 with a depth of 512, the data input selection unit selects RAM1 to work, and the data output by FFT is stored in RAM1 with a clock f _in =32MHz, and at the same time, calculate the modulus R of the stored data 512 cumulative sum $\mathrm{SUM}(\mathrm{SUM}=\underset{j=1}{\overset{512}{\mathrm{\&Sigma;}}}{R}_j)$ and threshold ${\mathrm{TH}}_1({\mathrm{TH}}_1=4*\frac{\mathrm{SUM}}{512}).$

b. When RAM1 is full, the data input selection unit selects RAM2 to work, and the data output by FFT is stored in RAM2, and the work of calculating the 512-point cumulative sum SUM and threshold value _TH1 of the stored data modulus R in step a is repeated.

c. During the data storage process of RAM2, read the data in RAM1 with the clock f _s =3*32=96MHz. Set a flag register with a bit width of 512. In the process of reading RAM1 for the first time, a part of R _j representing the modulus value in the read data, j=1, 2, 3...512, and TH ₁ for comparison, if it is greater than TH ₁ , the corresponding position of the flag register is set to 1, that is, flag[j-1]=1 (because the bit width of the flag starts from 0, it is necessary to use j-1 to represent the corresponding position of the flag bit width ), SUM=SUM-(R _j -TH ₁ ); otherwise flag[j-1]=0, SUM remains unchanged. When the first reading is completed, the threshold TH ₂ is calculated through the latest SUM (the calculation formula is shown in step a), and the second reading of RAM1 is started. Compare the read data R _j with TH ₂ , if R _j is greater than the threshold TH ₂ , check whether the corresponding position of the flag is 1, if it is 1, then the corresponding position of the flag remains unchanged, SUM=SUM-(TH ₁ - TH ₂ ); otherwise, the corresponding bit of the flag is set to 1, and SUM=SUM-(R _j −TH ₂ ); if R _j is smaller than the threshold TH ₂ , the corresponding bit of the flag and SUM remain unchanged. When the second pass of reading is completed, the threshold TH ₃ is calculated according to the latest SUM value, and the third pass of reading is started. At this time, if the read data R _j is greater than TH ₃ , set the read real part Re _j to TH ₃ and the imaginary part Im _j to 0 and output, that is, Re _j = TH ₃ , Im _j = 0; otherwise Output the read real part Re _j and imaginary part Im _j data as they are

d. When the data judgment of RAM1 is completed, the data in RAM2 is also stored. At this time, the work of step c is repeated for the data in RAM2, and new data is stored in RAM1.

(5) The data output by the interference suppression and judgment module is input to the IFFT module with the clock f _s =96MHz, where the module stores it through the dual-port RAM and reads it with the clock f _in =32MHz to complete the conversion of the data rate. The read data is input to the IFFT core, inversely transformed and output.

(6) The outputs of the two IFFT modules are directly added and combined, and sent to the external interface, and the anti-interference work is completed.

According to the characteristics of the spread spectrum signal, the degree of suppression of the interference signal can be judged by the correlation peak value of the spread spectrum signal and the local code signal.

The frequency spectrum and related values of the spread spectrum signal without interference are shown in Figure 3.

Figure 4 shows the spectrum and related values of the spread spectrum signal after adding an interference signal with a bandwidth of 2MHz and an interference signal ratio of 40dB.

The Modelsim simulation diagram of the threshold iteration process when FPGA is implemented is shown in Figure 5.

In the signal shown in FIG. 5 , threshold1 , threshold2 , and threshold3 correspond to the threshold values of the first iteration, the second iteration, and the third iteration, respectively.

From the perspective of the overall process, each threshold value (such as threshold1) will be updated according to the statistical results of the newly input data after each 512-point data judgment, that is, the threshold value will change dynamically according to the input data. . From the point of view of a complete judgment process of 512 points of data, after the first judgment iteration, the threshold value drops from threshold1 to threshold2, after the second iteration, the threshold value drops from threshold2 to threshold3, and in the process of the third iteration The lieutenant will output the data judgment and complete the interference judgment work of 512 points of data. The concrete implementation matches the theory.

After the signal passes through the interference suppression module implemented by FPGA, the frequency spectrum and related values of the spread spectrum signal are shown in Figure 6.

According to the results shown in Fig. 4, Fig. 5 and Fig. 6, it can be seen that no obvious correlation peak can be obtained after the interference signal is added, and the receiver cannot work. After interference suppression, the correlation peak is more obvious, and the position is the same as that of the signal without interference, and the interference suppression is successful.

After ISE synthesis and layout and routing, the RTL diagram implemented by FPGA is shown in Figure 7.

The specific resource consumption is shown in Table 2.

Table 2 Resource consumption graph

Claims (1)

1. a FPGA implementation method for the anti-interference algorithm of iterative frequency-domain, is characterized in that comprising the steps:

(1) by under change to intermediate frequency satellite-signal carry out AD sampling, the data that obtain are output as two-way, 1/2 window length delay is carried out on a road, and two paths of data is input to respectively to windowing module;

(2) windowing module is that the data of input are carried out windowing operation, and window function adopts broad sense hamming window, and window length is L, adopts the quantification of 8 bit data bit wides; After windowing has operated, data input FFT module;

(3) RAM that is L in degree of depth of FFT module use checks the data of input and stores, and reading out data is transported to FFT core afterwards, carries out FFT computing; FFT is set to Pipelined, Streaming I/O pattern, and operating frequency is f _in, f _inidentical with AD sampling clock, the output of its computing has real part Re and imaginary part Im two parts, and the mould value R jointly calculating by these two parts with by real part imaginary part in the present invention merges into one dimension matrix according to senior middle school's low level, i.e. { Re, Im, R}, is transported to and disturbs identification and suppress module;

(4) each interference identification is as follows with the course of work that suppresses module:

A. set up two-port RAM core RAM1 and RAM2 that two degree of depth are L=512, RAM1 work is selected in data input selection unit, and the data of FFT output are with clock f _instore in RAM1, calculate the L point cumulative sum of mould value R in stored data simultaneously and threshold value k is thresholding optimized coefficients;

B. after RAM1 is filled with, RAM2 work is selected in data input selection unit, and the data of FFT output are deposited in RAM2, calculates L point cumulative sum SUM and the threshold value TH of stored data mould value R in repeating step a simultaneously ₁work;

C. in the process of RAM2 data storage, to the data in RAM1 with clock f _sread f _s=N*f _in, N is iterations; Can obtain, can read N time to the data in RAM1 in this following period of time of RAM2 data storage; A flag register that bit wide is identical with the RAM1 degree of depth is set, in the process that RAM1 first pass is read, will in the data that read, represents a part of R of mould value _jwith TH ₁compare, j=1,2,3...L, if be greater than TH ₁the corresponding position j-i of flag register puts 1, i.e. flag[j-1]=1, SUM=SUM-(R _j-TH ₁); Otherwise flag[j-1]=0, SUM remains unchanged; Read the complete moment at first pass, calculate thresholding TH by up-to-date SUM ₂, start RAM1 to read for second time; By the data R reading _jwith TH ₂relatively, if R _jbe greater than thresholding TH ₂, now check whether the relevant position of flag is 1, if 1, flag relevant position remains unchanged, SUM=SUM-(TH ₁-TH ₂); Otherwise flag puts relevant position 1, SUM=SUM-(R _j-TH ₂); If R _jbe less than thresholding TH ₂, flag corresponding positions and SUM remain unchanged; Read the complete moment at second time, calculate thresholding TH according to up-to-date SUM value ₃, start the 3rd time read; The 3rd time to N-1 all over reading done operation and to read done operation for second time identical, a to the last reading out data, N, all over reading out data, can obtain threshold T H by N-1 time read operation _nif, the data R now reading _jbe greater than TH _n, by the real part Re reading _jbe set to TH _n, imaginary part Im _jbe set to 0 output, i.e. Re _j=TH _n, Im _j=0; Otherwise by the real part Re reading _jwith imaginary part Im _jdata are in statu quo exported;

D. in the time that the data decision of RAM1 is complete, the data in RAM2 are also stored end, and now the work to the Data duplication step c in RAM2, starts to store new data to RAM1;

(5) will disturb the data of identification and the output of inhibition module with clock f _sbe input to IFFT module, store by two-port RAM in this module and with clock f _inread, complete the conversion of data rate; The data input IFFT core reading, carries out inverse transformation output;

(6) output of two-way IFFT module is directly added to merging, flows to external interface, anti-interference end-of-job.