CN103198856A - DDR (Double Data Rate) controller and request scheduling method - Google Patents
DDR (Double Data Rate) controller and request scheduling method Download PDFInfo
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Abstract
The invention relates to a DDR (Double Data Rate) controller and a request scheduling method. The controller comprises an AHB (Advanced High Performance Bus) interface adaptive module (10), a plurality of client request transmission modules (11), a client interface module (12), a port scheduling module (13), a BANK scheduling module (14), an interpretation module (15), a PUB_PHY adaptive module (16), a DDR2/3PHY module (17), a DDR2/3 device (18), an interface data cache module (19), a data processing module (20), a microcomputer port configuration module (21) and a clock management module (22). The DDR controller and the request scheduling method are applied to data storage and transmission in high-speed communication system transmission chip design; and compared with the conventional controller, the DDR controller adopts request scheduling based on the structural characteristics of a DRAM (Dynamic Random Access Memory), so that the delay of the request is greatly reduced, the utilization rate of a data bus in transmission is improved, and larger bus bandwidth can be obtained in same configuration.
Description
Technical field
The present invention relates to digital integrated circuit DDR controller design field, is a kind of DDR controller and request scheduling method specifically.Described DDR refers to DDR2/3(DDR2 or DDR3).
Background technology
Along with developing rapidly of computer system, modem computer systems more and more is subjected to the restriction of primary memory performance.Performance of processors is increasing with annual 60% speed, and primary memory chip bandwidth is only increasing with the speed in every year 10%.Aspect speed, primary memory and processor have kept the gap of about order of magnitude always.Increasing for the cost that main memory bandwidth can the matched-field processors performance be spent, Computer System Design person must go to dwindle the performance gap between processor and the primary memory as possible.
The request scheduling method of DDR2/3 controller is exactly the technology of the associative operation of main memory accesses being carried out rational management, shortens the memory access time by this scheduling, thereby reaches the purpose that improves main memory bandwidth.
Summary of the invention
At the defective that exists in the prior art, the object of the present invention is to provide a kind of DDR controller and request scheduling method, be applied to storage and the forwarding of data in the high-speed communication system transmission chip design, traditional controller of comparing, employing is based on the request scheduling of DRAM architectural characteristic, reduce the delay of request greatly, the utilization factor of data bus can obtain bigger bus bandwidth under the identical configuration when improving transmission.
For reaching above purpose, the technical scheme that the present invention takes is:
A kind of DDR controller is characterized in that, comprising: AHB interface adaptation module 10, some client requests sending modules 11, customer interface module 12, Port Scheduling module 13, BANK scheduler module 14, explanation module 15, PUB_PHY adaptation module 16, DDR2/3PHY module 17, DDR2/3 device 18, interface data cache module 19, data processing module 20, microcomputer mouth configuration module 21, Clock management module 22;
AHB interface adaptation module 10 is finished the privately owned interface that the request on the ahb bus is transformed into the design of DDR controller, and the request after will changing outputs to customer interface module 12;
Client requests sending module 11 is finished the privately owned interface that client requests is fitted to the design of DDR controller, and the request after will changing outputs to customer interface module 12;
Port Scheduling module 13, it is finished according to the priority of the request of different port configuration the execution sequence of request is dispatched, and will ask to export to BANK scheduler module 14 according to the port priority order;
BANK scheduler module 14 is finished according to the BANK address of request and read-write type and is asked adjustment in proper order, export to downstream explanation module 15, purpose is as much as possible the request of identical BANK address to be scatter, the request of identical read-write type is got up continuously, thereby make the interpreted command efficient of downstream explanation module higher;
Explanation module 15, mainly finish and keep the refreshing of DRAM, the read-write requests of business is carried out command scheduling, client's reading and writing request after will arbitrating according to the DDR2/3 agreement is interpreted as the DRAM order, finishes cutting apart of requested service, finishes DDR self-refresh mode and battery saving mode function;
PUB_PHY adaptation module 16 is mainly finished the adaptive of the DRAM order of controller output and reading and writing data and different manufacturers DDR-PHY; The function that it is realized the initialization of DRAM and comes by the microcomputer mouth DRAM is tested;
DDR2/3PHY module 17 is finished the connection between DDR controller and the DDR2/3 device 18, carries out the calibration of conversion, writing level, the read data collection of electric signal and reads work such as data-bias correction;
What interface data cache module 19 cache interfaces were sent reads and writes data;
Data processing module 20 comprises read data processing module 201 and writes data processing module 202 two parts, data read/ablation process in the read/write interface buffering, based on the action of the row after cutting apart at every turn, produce the read of egress buffer, calculation command is to the entire path time-delay of data;
The various parameter configuration that microcomputer mouth configuration module 21 comes Configuration Control Unit to use by the microcomputer mouth are to satisfy the different application demand;
The clock source that Clock management module 22 provides designing institute to need.
On the basis of technique scheme, described client requests sending module 11 is according to customer requirement support read-write unification port, independent write port or independent read port.
On the basis of technique scheme, customer interface module 12 has self-checking function, is not having to send a series of read-write requests with verification character under the situation of client requests.
On the basis of technique scheme, Port Scheduling module 13 is as the arbitration scheduler module, and it is running into the method that adopts polling dispatching under the equal priority, guarantees that the delay of high priority port request is shorter, obtains bigger bus bandwidth.
On the basis of technique scheme, each module of described DDR controller realizes with the hardware FPGA form fully.
A kind of request scheduling method of DDR controller is characterized in that, may further comprise the steps:
Step 1: the user sends the read-write requests of data to customer interface module 12 by client requests sending module 11, the read-write requests of described data comprises request type, address, length, ID number at least, customer interface module 12 temporarily deposits request in the buffer memory in the module, after waiting for that downstream port scheduler module 13 provides the response ack signal, order is sent request to Port Scheduling module 13;
Wherein:
Data path is write direction, writes data and deposits in according to the page address in the solicited message and deposit writing in the buffer memory of customer interface module 12 in, waits for that will write data again when follow-up explanation module 15 is explained these requests sends;
Data path is read direction, receive the read pulse of explanation module 15 after, according to reading enable signal that the data of reading back are temporary to reading in the buffer memory, the order that comes according to client's read request ejects read data successively;
Step 2: the request that customer interface module 12 is sent is dispatched according to port numbers and the BANK address of request in Port Scheduling module 13 and BANK scheduler module 14;
Step 3: enter in proper order in the request waiting list in the explanation module 15 through the request after the scheduling, the sequential of stipulating in the agreement according to DDR requires request is construed to the instruction of DDR identification;
Step 4: DDR that explanation module 15 sends instruction, adjust phase relation between instruction and data through PUB_PHY adaptation module 16, enter then and carry out level conversion in the PHY module 17 and output to DDR device 18.
On the basis of technique scheme, after each request was finished, in customer interface module 12 inside, client's address need discharge according to the sequence of request input.
On the basis of technique scheme, the concrete scheduling process of Port Scheduling module 13 and BANK scheduler module 14 is as follows:
At first, request can be carried out preliminary scheduling according to the priority of request port in Port Scheduling module 13, and high priority is preferential, uses the Roundrobin polling algorithm to arbitrate under the same priority;
Then, will ask branch to be gone in the different formations according to BANK address and the read-write type of request, BANK scheduler module 14 can interleave scheduling between the request of different formations, at utmost guarantee discontinuous request of calling same BANK; Simultaneously, BANK scheduler module 14 also can guarantee read-write requests " binding " output, namely guarantees DDR data bus transmission direction unanimity in a period of time, reduces unnecessary read-write switching time; In addition, BANK scheduler module 14 also has overtime protection mechanism, guarantees can not occur the problem that certain type request always can not get responding and occurs.
On the basis of technique scheme, described customer interface module 12 comprises following function sub-modules: read data buffer memory 119, read request are turned round order 120, read response queue 121, are read BUFF page pointer 122, customer address to address mapping 125, the solicited message buffer queue 124 of the buffer memory page, write BUFF page pointer 126, write request is turned round order 127, write response formation 128, is write data buffer memory 129;
The workflow of customer interface module 12 is as follows:
Processing for write request, client is after receiving write response cli_waq_ack, send write request, customer information and data to customer interface module 12, address information in the customer information is shone upon 125 submodules through customer address and is converted to the discernible page address page_addr of customer interface to the address of the buffer memory page, and deposits in the solicited message buffer queue 124 with other solicited messages; Writing the buffer memory page address page_addr of data cli_wd after according to mapping deposits in and writes in the data cache writing data buffer memory 129; The BUFF page pointer 126 of writing that records the write request number of buffer memory in the customer interface simultaneously adds 1; Wait for then when request waiting list in the Port Scheduling module 13 in downstream is discontented, just eject request and information by the formation sequence; After the explanation module 15 in downstream is finished the explanation of certain write request, can send the request of getting this request msg to customer interface module 12 by writing data processing module 202; Therefore because downstream module can be carried out certain scheduling to the request execution order, writing the write response that data processing module 202 returns is out of order release; In order to prevent that the problem of address conflict from appearring in client, customer interface module 12 can deposit the write response of out of order release in the write response formation 128 in, and the order that enters according to actual write request is turned round order 127 order outputs by write request successively and write and finish indication and id information at last;
For the processing of read request, solicited message deposit in and the address mapping principle with the processing of write request; Finish the explanation of read request when explanation module 15 after, after waiting for certain delay the read data basis is read the relevant position that BUFF page pointer 122 deposits read data buffer memory 119 in, enter Deng the response of returning in the response queue 121 of continuing, after read request was turned round order 120 and turned round order and become the order that request enters, order was sent read data and id information to the client then.
DDR controller of the present invention and request scheduling method, dispatching method has high-level efficiency, can support controller design and the implement device of DDR2/3 device flexibly, effectively data are passed through the lower bottleneck problem of DDR device stores forward efficiency in the present digital transmission chip of solution, and hardware is realized the problem of implementation of memory access dispatching algorithm.
Description of drawings
The present invention has following accompanying drawing:
Fig. 1: the structural representation of high speed DDR2/3 controller.
Fig. 2: customer interface module workflow diagram.
Fig. 3: the structural representation of request arbitration.
Fig. 4: the workflow diagram of request arbitration.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in further detail.
As shown in Figure 1, DDR controller of the present invention (DDR3C controller) is to contain user interface and DDR device physics layer (PHY) on a kind of structure, the control device of the DDR2/3 of compatible general data request and the request of AHB class on the function, and it comprises:
AHB interface adaptation module (AHB_APT) 10, some client requests sending modules (CLI_HOST) 11, customer interface module (CLI_INF) 12, Port Scheduling module (PORT_SCH) 13, BANK scheduler module (BANK_SCH) 14, explanation module (DDR3CTR) 15, PUB_PHY adaptation module 16, DDR2/3PHY module 17, DDR2/3 device 18, interface data cache module 19, data processing module (W/RDCC) 20, microcomputer mouth configuration module (UPI_DDR3C) 21, Clock management module (CLK_MANAGE) 22;
AHB interface adaptation module 10 is finished the privately owned interface that the request on the ahb bus is transformed into the design of DDR controller, and the request after will changing outputs to customer interface module 12;
Client requests sending module 11 is finished the privately owned interface that client requests is fitted to the design of DDR controller, and the request after will changing outputs to customer interface module 12; Described client requests sending module 11 is according to customer requirement support read-write unification port, independent write port or independent read port; In embodiment illustrated in fig. 1, be provided with N client requests sending module 11, the N value is the positive integer more than or equal to 1;
Port Scheduling module 13 also can be described as the arbitration scheduler module, and it is finished according to the priority of the request of different port configuration the execution sequence of request is dispatched, and will ask to export to BANK scheduler module 14 according to the port priority order; Adopt the method for polling dispatching under the equal priority, guarantee that the delay of high priority port request is shorter, obtain bigger bus bandwidth;
BANK scheduler module 14 is finished according to the BANK address of request and read-write type and is asked adjustment in proper order, export to downstream explanation module 15, purpose is as much as possible the request of identical BANK address to be scatter, the request of identical read-write type is got up continuously, thereby make the interpreted command efficient of downstream explanation module higher;
Explanation module 15, also be called the read-write requests explanation module, mainly finish and keep the refreshing of DRAM, the read-write requests of business is carried out command scheduling, client's reading and writing request after will arbitrating according to the DDR2/3 agreement is interpreted as the DRAM order, finish cutting apart of requested service, finish DDR self-refresh mode and battery saving mode functions such as (low power dissipation design);
PUB_PHY adaptation module 16 is mainly finished the adaptive of the DRAM order of controller output and reading and writing data and different manufacturers DDR-PHY; In addition, the initialization of DRAM and the function coming DRAM is tested by the microcomputer mouth are also in this realization; At different producers or DDR2/3 type, this module needs to adjust;
DDR2/3PHY module 17 is finished the connection between DDR controller and the DDR2/3 device 18, carries out the calibration of conversion, writing level, the read data collection of electric signal and reads work such as data-bias correction;
What interface data cache module 19 cache interfaces were sent reads and writes data;
Data processing module 20 comprises read data processing module 201(RDCC) and write data processing module 202(WDCC) two parts, data read/ablation process in the read/write interface buffering, move based on the row after cutting apart at every turn, produce the read of egress buffer, calculation command is to the entire path time-delay of data;
The various parameter configuration that microcomputer mouth configuration module 21 comes Configuration Control Unit to use by the microcomputer mouth, purpose are to make the present invention can satisfy the different application demand;
The clock source that Clock management module 22 provides designing institute to need.
The design of DDR2/3 controller of the present invention realizes with the hardware FPGA form fully.By microcomputer mouth (UPI) controller is carried out easy configuration about DDR parameter and controller characteristic, just can realize transmitting data by hardware interface to the DDR2/3 device stores.Carry out the system that the mass data storage is transmitted for needing in the high-speed communication, use the present invention's design, (the less complexity of hardware area is not high) can obtain the total line use ratio of higher data (data transfer bandwidth) under the hardware costs that can bear.In addition, the present invention supports the CPU request of ahb bus class, and guarantees that by arbitration algorithm the request of AHB class is responded faster.
It has following characteristic and advantage:
1, compatible DDR2/3 agreement of while;
2, support industrywide standard DDR PHY Interface2.1;
3, the project organization of low area, low client request delay;
4, support AMBA AXI/AHB and service class request simultaneously, but the port flexible configuration;
5, request scheduling method (based on client requests and DRAM characteristic) guarantees high bandwidth utilization and low delay efficiently;
6, support low power dissipation design, reduce system power dissipation;
7, adopt controller and the DRAM clock frequency ratio of 1:2, reduce design part sequential;
8, have self-checking function, can test controller under the situation that does not connect external interface and the working condition of DDR device.
At above-mentioned DDR controller, the present invention gives the request scheduling method of this DDR controller, may further comprise the steps:
Step 1: the user comprises two class requests by this module of client requests sending module 11(: common customer port request and the request of AHB interface class) send the read-write requests (comprising request type, address, length, ID etc.) of data to customer interface module 12, customer interface module 12 temporarily deposits request in the buffer memory in the module, after waiting for that downstream port scheduler module 13 provides the response ack signal, order is sent request to Port Scheduling module 13;
Data path is write direction, writes data and deposits in according to the page address in the solicited message and deposit writing in the buffer memory of customer interface module 12 in, waits for that will write data again when follow-up explanation module 15 is explained these requests sends;
Data path is read direction, receive the read pulse of explanation module 15 after, according to reading enable signal that the data of reading back are temporary to reading in the buffer memory, the order that comes according to client's read request ejects read data successively;
Because entering the request of customer interface module 12 need be through the out of order scheduling of downstream port scheduler module 13 and BANK scheduler module 14, therefore the request that might occur arriving previously in explanation module 15 is not also carried out, and the conflict situations of identical address been has just has been read and write in the request of back.For fear of the situation of this request address conflict, after each request was finished, in customer interface module 12 inside, client's address need discharge according to the sequence of request input;
Step 2: the request meeting that customer interface module 12 is sent is dispatched to a certain extent according to port numbers and the BANK address of request in Port Scheduling module 13 and BANK scheduler module 14.The effect of scheduling: the one, the high priority of assurance low delay port request, the 2nd, improve the explanation efficient of downstream explanation module, thereby obtain the high-throughput on the DDR data bus.
The concrete scheduling process of Port Scheduling module 13 and BANK scheduler module 14 is as follows:
At first, request can be carried out preliminary scheduling according to the priority of request port in Port Scheduling module 13, and high priority is preferential, uses the Roundrobin polling algorithm to arbitrate under the same priority;
Then, BANK address and read-write type according to request will ask branch to go into that (DDR is totally 8 BANK in the different formations, each BANK is divided into two formations of reading and writing, totally 16 formations), BANK scheduler module 14 can interleave scheduling between the request of different formations, at utmost guarantee discontinuous request of calling same BANK; Simultaneously, BANK scheduler module 14 also can guarantee read-write requests " binding " output, namely guarantees DDR data bus transmission direction unanimity in a period of time, reduces unnecessary read-write switching time; In addition, BANK scheduler module 14 also has overtime protection mechanism, guarantees can not occur the problem that certain type request always can not get responding and occurs;
Step 3: enter in proper order in the request waiting list in the explanation module 15 through the request after the scheduling, the sequential of stipulating in the agreement according to DDR requires request is construed to the instruction of DDR identification; In the specific explanations process, on the one hand, explanation module 15 is understood serial interpretation and is carried out the read-write motion of waiting list head of the queue request, on the other hand, if detecting, module have other requests to need the demand of preparing in advance (such as charging or activation) in the formation, then can be in the interval of carrying out the row action, plug hole is carried out the charging of asking in the formation or is activated action; In addition, explanation module also needs to finish the refresh operation of DDR regulation and the self refresh operation under the battery saving mode;
Step 4: DDR that explanation module 15 sends instruction, adjust phase relation between instruction and data through PUB_PHY adaptation module 16, enter then and carry out level conversion in the PHY module 17 and output to DDR device 18; PUB_PHY adaptation module 16 interfaces can be fitted on the different phy interfaces flexibly by simple process, and are convenient general; In order to reduce the sequential requirement of whole design, the present invention designs and adopts the control core layer to use low-frequency clock, in the method for PUB_PHY module frequency multiplication to the DDR high frequency clock, be explanation module under low-frequency clock and the data of order, address and the double bit wide of two paths of line output, in the PUB_PHY module, use to be merged into a path after the frequency doubling clock sampling and to export to DDR; Concrete sequential relationship satisfies industrywide standard DDR PHY Interface2.1 between interface.
Be illustrated in figure 2 as the workflow diagram of the customer interface module 12 of DDR2/3 controller of the present invention design, wherein the concrete enforcement of customer interface module 12 comprises following function sub-modules: read data buffer memory 119, read request are turned round order 120, read response queue 121, are read BUFF page pointer 122, customer address shines upon 125 to the address of the buffer memory page, solicited message buffer queue 124, write BUFF page pointer 126, write request is turned round order 127, write response formation 128, is write data buffer memory 129.
The customer interface module 12 of the DDR2/3 controller of embodiment of the invention design go for reading and writing the customer interface of unification, independently read interface, independently write interface, AHB class customer interface (front end need increase the adapter circuit module of ahb bus).Under different application scenarioss, can come the type of option interface by configuration.The workflow of customer interface module 12 is as follows:
1) for the processing of write request, client is after receiving write response cli_waq_ack, send write request, customer information (comprising address, length, ID, mask etc.) and data to customer interface module 12, address information in the customer information is shone upon 125 submodules through customer address and is converted to the discernible page address page_addr of customer interface to the address of the buffer memory page, and deposits solicited message buffer queue 124(asynchronous FIFO composition in other solicited messages) in; Writing the buffer memory page address page_addr of data cli_wd after according to mapping deposits in and writes in the data cache writing data buffer memory 129; The BUFF page pointer 126 of writing that records the write request number of buffer memory in the customer interface simultaneously adds 1; Wait for then when request waiting list in the Port Scheduling module 13 in downstream is discontented (the back-pressure ack signal is effective), just eject request and information by the formation sequence; After the explanation module 15 in downstream is finished the explanation of certain write request, can be by writing data processing module 202(WDCC, the submodule of data processing module 20 among Fig. 1) send the request of getting this request msg to customer interface module 12; Therefore because downstream module (Port Scheduling module 13, BANK scheduler module 14) can be carried out certain scheduling to the request execution order, writing the write response that data processing module 202 returns is out of order release; In order to prevent that client from the problem of address conflict occurring (for example because behind the request scheduling, certain DDR address is not just read before also not write), customer interface module 12 can deposit the write response of out of order release in the write response formation (asynchronous FIFO) 128 in, and the order that enters according to actual write request is turned round order 127 order outputs by write request successively and write and finish indication and id information at last;
2) for the processing of read request, solicited message deposit in and the address mapping principle with the processing of write request; Finish the explanation of read request when explanation module 15 after, after waiting for certain delay the read data basis is read the relevant position that BUFF page pointer 122 deposits read data buffer memory 119 in, enter Deng the response of returning in the response queue 121 of continuing, after read request was turned round order 120 and turned round order and become the order that request enters, order was sent read data and id information to the client then.
Be illustrated in figure 3 as the Port Scheduling module 13 that is used for realization request arbitration function of DDR2/3 controller design of the present invention and the structured flowchart of BANK scheduler module 14, namely ask the concrete enforcement of arbitration function to comprise following functional module: Port Scheduling module 13, BANK scheduler module 14.The request of each port entry port scheduler module 13 that walks abreast, according to priority, continuously between request under the dispatching principle such as the request of the request separation of identical BANK address, read-write type unanimity binding executions serial export.
Be illustrated in figure 4 as the concrete workflow diagram of request scheduling (request arbitration) function of DDR2/3 controller design of the present invention.Because the three-dimensional storage organization (the DDR address is divided into the Bank block address) of the uniqueness of DDR device, Row (row address) and Column (column address) three parts), the performance height of its access data depends on the pattern (being the execution order of ordering between each business) of performed order.Find by analyzing, the principle that request is carried out according to the request binding of identical BANK address discretize, read-write type unanimity is carried out out of order scheduling, can improve the performance (bandwidth, time-delay etc.) of storer significantly.
The DDR2/3 controller design of the embodiment of the invention is carried out request scheduling according to top dispatching principle, its workflow is as follows: whole scheduling is divided into two stages, Port Scheduling (port arbitration, i.e. once arbitration) and BANK scheduling (BANK arbitration, i.e. secondary arbitration).At first, the request of each customer interface module 12 entry port scheduler module 13 that walks abreast, the Request Priority that Port Scheduling module 13 can dispose according to each interface divides into groups request, and (step 100 design supporting interface can dispose 1-8 kinds of priority, 1 priority is the highest), respectively organize priority request then and enter the corresponding wheel of this group scheduling Roundrobin(Round-Robin Scheduling) poll module (abbreviating the RR module as) interior (step 101), after waiting for that downstream procedures 102 ejects a request, start the poll of respective priority RR module, select the next one request to be exported of this priority.The wait output request that RR module under every kind of priority is selected can be according to fixing priority orders (1 → 8) (step 102), and serial output enters BANK scheduler module 14.BANK scheduler module 14 can be according to the BANK address of request, the request will imported is divided into 8 BANK administrative unit BMU(steps 103), port type (read-write unification in each BANK administrative unit internal condition port arrangement, write separately, read separately) request is deposited in three formations (step 104), the request of head of the queue enters respectively according to read-write type and reads or writes in the RR module (step 105) in each BANK administrative unit formation then, the selection signal that provides according to request type selection mode machine to select request output (step 106) in the RR module, the request (step 109) after the final serial output scheduling from reading or writing.The selection of read-write type request is to determine (step 107) by a request type selection mode machine, and this state machine can be adjusted the type of output request according to the request BANK address of the maximum execution time of the read-write requests of microcomputer mouth configuration and the current output that feeds back.In addition, in order to guarantee from the dispersiveness of the request BANK address of BANK scheduler module 14 serials output, the BANK address of the request of current output can be recorded, and feeding back to the porch of read and write RR module, the request that (Configuration Values) shields such BANK address in a period of time enters in the read and write RR module (step 108) again.Request stream through above-mentioned two stages scheduling, BANK address discretize, read-write type binding with request, and taken into account the characteristics of the priority of client port, and heightened the efficient that the downstream explanation module carries out command interpretation greatly, improved the forwarding performance of entire controller.
The embodiment of the invention described above is that prerequisite is implemented according to the control method of technical solution of the present invention, has provided detailed embodiment and concrete operating process, but protection scope of the present invention comprises and is not limited to this embodiment.
The content that is not described in detail in this instructions belongs to this area professional and technical personnel's known prior art.
Claims (9)
1. a DDR controller is characterized in that, comprising: AHB interface adaptation module (10), some client requests sending modules (11), customer interface module (12), Port Scheduling module (13), BANK scheduler module (14), explanation module (15), PUB_PHY adaptation module (16), DDR2/3PHY module (17), DDR2/3 device (18), interface data cache module (19), data processing module (20), microcomputer mouth configuration module (21), Clock management module (22);
AHB interface adaptation module (10) is finished the privately owned interface that the request on the ahb bus is transformed into the design of DDR controller, and the request after will changing outputs to customer interface module (12);
Client requests sending module (11) is finished the privately owned interface that client requests is fitted to the design of DDR controller, and the request after will changing outputs to customer interface module (12);
Customer interface module (12) is finished application client request absorption and exchanges data, customer address is to the mapping of DDR address, read-write requests address assignment and recovery, and have and distribute address error detection protective capability, reading and writing request ordinal response function, the mutual handoff functionality of client clock territory and DDR3C core key-course clock zone;
Port Scheduling module (13), it is finished according to the priority of the request of different port configuration the execution sequence of request is dispatched, and will ask to export to BANK scheduler module (14) according to the port priority order;
BANK scheduler module (14) is finished according to the BANK address of request and read-write type and is asked adjustment in proper order, export to downstream explanation module (15), purpose is as much as possible the request of identical BANK address to be scatter, the request of identical read-write type is got up continuously, thereby make the interpreted command efficient of downstream explanation module higher;
Explanation module (15), mainly finish and keep the refreshing of DRAM, the read-write requests of business is carried out command scheduling, client's reading and writing request after will arbitrating according to the DDR2/3 agreement is interpreted as the DRAM order, finishes cutting apart of requested service, finishes DDR self-refresh mode and battery saving mode function;
PUB_PHY adaptation module (16) is mainly finished the adaptive of the DRAM order of controller output and reading and writing data and different manufacturers DDR-PHY; The function that it is realized the initialization of DRAM and comes by the microcomputer mouth DRAM is tested;
DDR2/3PHY module (17) is finished the connection between DDR controller and the DDR2/3 device (18), carries out the calibration of conversion, writing level, the read data collection of electric signal and reads work such as data-bias correction;
What interface data cache module (19) cache interface was sent reads and writes data;
Data processing module (20) comprises read data processing module (201) and writes data processing module (202) two parts, data read/ablation process in the read/write interface buffering, move based on the row after cutting apart at every turn, produce the read of egress buffer, calculation command is to the entire path time-delay of data;
The various parameter configuration that microcomputer mouth configuration module (21) comes Configuration Control Unit to use by the microcomputer mouth are to satisfy the different application demand;
The clock source that Clock management module (22) provides designing institute to need.
2. DDR controller as claimed in claim 1 is characterized in that: described client requests sending module (11) is according to customer requirement support read-write unification port, write port or read port separately separately.
3. DDR controller as claimed in claim 1, it is characterized in that: customer interface module (12) has self-checking function, is not having to send a series of read-write requests with verification character under the situation of client requests.
4. DDR controller as claimed in claim 1, it is characterized in that: Port Scheduling module (13) is as the arbitration scheduler module, it is running into the method that adopts polling dispatching under the equal priority, guarantees that the delay of high priority port request is shorter, obtains bigger bus bandwidth.
5. DDR controller as claimed in claim 1, it is characterized in that: each module of described DDR controller realizes with the hardware FPGA form fully.
6. the request scheduling method of a DDR controller is characterized in that, may further comprise the steps:
Step 1: the user sends the read-write requests of data to customer interface module (12) by client requests sending module (11), the read-write requests of described data comprises request type, address, length, ID number at least, customer interface module (12) temporarily deposits request in the buffer memory in the module, after waiting for that downstream port scheduler module (13) provides the response ack signal, order is sent request to Port Scheduling module (13);
Wherein:
Data path is write direction, writes data and deposits in according to the page address in the solicited message and deposit writing in the buffer memory of customer interface module (12) in, waits for that will write data again when follow-up explanation module (15) is explained this request sends;
Data path is read direction, receive the read pulse of explanation module (15) after, according to reading enable signal that the data of reading back are temporary to reading in the buffer memory, the order that comes according to client's read request ejects read data successively;
Step 2: the request that customer interface module (12) is sent is dispatched according to port numbers and the BANK address of request in Port Scheduling module (13) and BANK scheduler module (14);
Step 3: enter in proper order in the interior request waiting list of explanation module (15) through the request after the scheduling, the sequential of stipulating in the agreement according to DDR requires request is construed to the instruction of DDR identification;
Step 4: DDR that explanation module (15) sends instruction, adjust phase relation between instruction and data through PUB_PHY adaptation module (16), enter then and carry out level conversion in the PHY module (17) and output to DDR device (18).
7. method as claimed in claim 6 is characterized in that: after each request was finished, in customer interface module (12) inside, client's address need discharge according to the sequence of request input.
8. method as claimed in claim 6 is characterized in that, the concrete scheduling process of Port Scheduling module (13) and BANK scheduler module (14) is as follows:
At first, request can be carried out preliminary scheduling according to the priority of request port in Port Scheduling module (13), and high priority is preferential, uses wheel to make scheduling Roundrobin polling algorithm arbitrate under the same priority;
Then, will ask branch to be gone in the different formations according to BANK address and the read-write type of request, BANK scheduler module (14) can interleave scheduling between the request of different formations, at utmost guarantee discontinuous request of calling same BANK; Simultaneously, BANK scheduler module (14) also can guarantee read-write requests " binding " output, namely guarantees DDR data bus transmission direction unanimity in a period of time, reduces unnecessary read-write switching time; In addition, BANK scheduler module (14) also has overtime protection mechanism, guarantees can not occur the problem that certain type request always can not get responding and occurs.
9. method as claimed in claim 6, it is characterized in that described customer interface module (12) comprises following function sub-modules: read data buffer memory (119), read request are turned round order (120), read response queue (121), are read BUFF page pointer (122), customer address to address mapping (125), the solicited message buffer queue (124) of the buffer memory page, write BUFF page pointer (126), write request is turned round order (127), write response formation (128), is write data buffer memory (129);
The workflow of customer interface module (12) is as follows:
Processing for write request, client is after receiving write response cli_waq_ack, send write request, customer information and data to customer interface module (12), address information in the customer information is shone upon (125) submodule through customer address to the address of the buffer memory page and is converted to the discernible page address page_addr of customer interface, and deposits in the solicited message buffer queue (124) with other solicited messages; Writing the buffer memory page address page_addr of data cli_wd after according to mapping deposits in and writes in the data cache writing data buffer memory (129); The BUFF page pointer (126) of writing that records the write request number of buffer memory in the customer interface simultaneously adds 1; Wait for then when request waiting list in the Port Scheduling module (13) in downstream is discontented, just eject request and information by the formation sequence; After the explanation module (15) in downstream is finished the explanation of certain write request, can send the request of getting this request msg to customer interface module (12) by writing data processing module (202); Therefore because downstream module can be carried out certain scheduling to the request execution order, writing the write response that data processing module (202) returns is out of order release; In order to prevent that the problem of address conflict from appearring in client, customer interface module (12) can deposit the write response of out of order release in the write response formation (128) in, and the order that enters according to actual write request is turned round the output of order (127) order by write request successively and write and finish indication and id information at last;
For the processing of read request, solicited message deposit in and the address mapping principle with the processing of write request; After explanation module (15) is finished the explanation of read request, after waiting for certain delay the read data basis is read the relevant position that BUFF page pointer (122) deposits read data buffer memory (119) in, enter Deng the response of returning in the response queue of continuing (121), after read request was turned round order (120) and turned round order and become the order that request enters, order was sent read data and id information to the client then.
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Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103810123A (en) * | 2014-02-18 | 2014-05-21 | 龙芯中科技术有限公司 | Memory control device and method |
| CN104850501A (en) * | 2015-04-29 | 2015-08-19 | 中国人民解放军国防科学技术大学 | Memory access address mapping method and memory access address mapping unit for DDR (Double Data Rate) memory |
| CN105159853A (en) * | 2015-09-25 | 2015-12-16 | 中国船舶重工集团公司第七0九研究所 | DFI standard DDR3 controller based on FPGA |
| CN105825880A (en) * | 2016-03-07 | 2016-08-03 | 深圳市紫光同创电子有限公司 | Access control method used for DDR controller, and apparatus and circuit thereof |
| CN105868134A (en) * | 2016-04-14 | 2016-08-17 | 烽火通信科技股份有限公司 | High-performance multi-port DDR (double data rate) controller and method for implementing same |
| WO2016202041A1 (en) * | 2015-06-18 | 2016-12-22 | 中兴通讯股份有限公司 | Method and apparatus for controlling double data rate synchronous dynamic random access memory |
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| CN108009372A (en) * | 2017-12-15 | 2018-05-08 | 中国科学院计算技术研究所 | A kind of method of DDR memory virtuals writing level adjustments responsive |
| CN108897696A (en) * | 2018-06-15 | 2018-11-27 | 西安微电子技术研究所 | A kind of high-capacity FIFO controller based on DDRx memory |
| CN109144421A (en) * | 2018-08-29 | 2019-01-04 | 深圳忆联信息系统有限公司 | A kind of method and device accelerating DDR access efficiency |
| CN111506264A (en) * | 2020-04-10 | 2020-08-07 | 华中科技大学 | Virtual multi-channel SDRAM access method supporting flexible block access |
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| CN111949578A (en) * | 2020-08-04 | 2020-11-17 | 西安电子科技大学 | DDR3 controller based on DFI standard |
| CN112052205A (en) * | 2020-08-31 | 2020-12-08 | 浙江双成电气有限公司 | DDR3 multi-port read-write storage management method based on FPGA |
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| CN113190477A (en) * | 2021-04-19 | 2021-07-30 | 烽火通信科技股份有限公司 | Low-delay DDR control method and device suitable for table look-up application |
| CN113435148A (en) * | 2021-06-04 | 2021-09-24 | 上海天数智芯半导体有限公司 | Parameterized cache digital circuit micro-architecture and design method thereof |
| CN114036085A (en) * | 2021-09-24 | 2022-02-11 | 北京无线电测量研究所 | Multitask read-write scheduling method based on DDR4, computer equipment and storage medium |
| CN114968169A (en) * | 2022-05-17 | 2022-08-30 | 赵浩然 | DDR-FIFO (double data Rate-first in first out) implementation system and method controlled by FGPA (double data Rate Power Amplifier) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201760B1 (en) * | 1998-12-30 | 2001-03-13 | Hyundai Electronics Industries Co., Ltd. | Apparatus and method for performing data read operation in DDR SDRAM |
| CN101000796B (en) * | 2006-01-12 | 2010-06-09 | 旺玖科技股份有限公司 | Control module and method for double data rate synchronous dynamic random access memory |
-
2013
- 2013-03-22 CN CN201310096014.3A patent/CN103198856B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201760B1 (en) * | 1998-12-30 | 2001-03-13 | Hyundai Electronics Industries Co., Ltd. | Apparatus and method for performing data read operation in DDR SDRAM |
| CN101000796B (en) * | 2006-01-12 | 2010-06-09 | 旺玖科技股份有限公司 | Control module and method for double data rate synchronous dynamic random access memory |
Non-Patent Citations (1)
| Title |
|---|
| 蔡蕊: "网络处理器中DDR SDRAM控制器的设计与实现", 《万方学术会议数据库》 * |
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