CN103188192A - Baseband processing device applied to video sensor - Google Patents
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Abstract
本发明提供一种应用于视频传感器的基带处理装置，包括数字调制电路和数字解调电路，所述数字调制电路包括：子载波映射模块、IFFT变换模块、加循环器、加窗器、限幅器、以及上采样滤波器；所述数字解调电路包括：下采样滤波器、辅助同步器、去循环器、FFT变换模块、子载波解映射模块、信道估计器、均衡器、以及判决器；其中，所述IFFT变换模块和所述FFT变换模块共用一个FFT核，所述FFT核按照时分方式复用；所述辅助同步器的设计方法基于GPS和长循环前缀。相对于现有技术，本发明将FFT变换器和IFFT变换器复用，同时省去帧头，利用GPS和循环前缀进行同步，简化了算法并节省了硬件资源，提高了频谱利用率，为工程设计提供了一种切实可行的方法。
The invention provides a baseband processing device applied to a video sensor, including a digital modulation circuit and a digital demodulation circuit, and the digital modulation circuit includes: a subcarrier mapping module, an IFFT transformation module, a circulator, a windowing device, and a limiter device, and an upsampling filter; the digital demodulation circuit includes: a downsampling filter, an auxiliary synchronizer, a decirculator, an FFT transformation module, a subcarrier demapping module, a channel estimator, an equalizer, and a decision device; Wherein, the IFFT transformation module and the FFT transformation module share one FFT core, and the FFT cores are multiplexed in a time-division manner; the design method of the auxiliary synchronizer is based on GPS and long cyclic prefix. Compared with the prior art, the present invention multiplexes the FFT converter and the IFFT converter, saves the frame header at the same time, uses GPS and cyclic prefix for synchronization, simplifies the algorithm and saves hardware resources, improves the spectrum utilization rate, and contributes to engineering Design offers a practical approach.
Description
Technical field
The present invention relates to wireless sensor technology, relate in particular to a kind of base band processing device that is applied to video sensor.
Background technology
Transducer is a kind of device or the device that can experience specified measuring range spare and convert available signal according to certain rules to, the wireless sense network of being made up of transducer is widely used,, for example Smart Home, environmental monitoring, Industry Control, ground observation, military surveillance etc.In the wireless sense network system, comprise the two large divisions, transmitting terminal and receiving terminal.
In existing wireless sense network, Base-Band Processing all is based on single carrier wave time domain balanced way and spread spectrum mode.
Single carrier is realized simpler, and transmitting terminal at first obtains data from information source or channel encoder, carries out the planisphere mapping then, carries out up-sampling filtering at last, perhaps closes digital intermediate frequency of generation frequently by numeral and inserts radio circuit again.Receiving terminal is sent radiofrequency signal into if demodulator and is obtained digital baseband signal, eliminates intersymbol interference by time-domain equalizer then, finishes symbol judgement by the planisphere inverse mapping at last.
The spread spectrum mode is to add a frequency multiplier and despreader on the single carrier basis, frequency multiplier comprises frequency expansion sequence generator and multiplier, multiply each other by input data and spread spectrum code sequence, each Bit data is extended to some bit code sheets, despreader is a matched filter corresponding with selected frequency multiplier, list entries and local frequency expansion sequence are carried out related operation, and operation result is sent into decision device.
Both compare, and simple based on the sensor node Base-Band Processing of single carrier, algorithm complex is low, but in the city wireless environment that multipath enriches, can there be serious intersymbol interference, for overcoming intersymbol interference, need carry out time domain equalization, and the design meeting more complicated of time-domain equalizer.Correspondingly, the communication distance of spread spectrum sensor node is far away, but spectrum efficiency and transmission rate are lower, and is not suitable for the bigger application scenario of data volume.
Along with digital signal processing technology rapid development, make multicarrier in digital baseband, realize becoming possibility, this wherein one of the technology of most critical be exactly discrete Fourier transform (Discrete Fourier Transform, DFT) and inverse discrete Fourier transform (Inverse Discrete Fourier Transform, IDFT).Fast Fourier transform (Fast Fourier Transform, algorithm has been simplified in proposition FFT) and application greatly, and therefore multicarrier system be used widely.
In bilateral system, modulation circuit comprises that (demodulator circuit comprises a FFT device to an inverse fast Fourier transform for Inverse Fast Fourier Transformation, IFFT) device, when if Fourier transform length is longer, these two devices can take a large amount of resources.In addition, in multicarrier system, the ofdm signal of transmission comprises frame head, frequency pilot sign and data symbol, frame head is mainly used to carry out synchronously, in order to resist time and the frequency selective fading under the urban environment, select the PN sequence that correlated performance is good, length is long usually, comprise the matched filter of a PN sequence simultaneously in the demodulator circuit, walk abreast and carry out multiply-add operation, under the situation of high sampling rate, can consume a large amount of hardware resources.
Summary of the invention
The object of the present invention is to provide a kind of base band processing device that is applied to video sensor, be used for to solve the prior art system complex, computing is loaded down with trivial details and consumes problem such as great amount of hardware resources.
The invention provides a kind of base band processing device that is applied to video sensor, comprise digital modulation circuit and digital demodulating circuit, wherein, described digital modulation circuit comprises: subcarrier mapping block, IFFT conversion module, add circulator, window added device, amplitude limiter and up-sampling filter; Described digital demodulating circuit comprises: downsampling filter, assist in synchronization device, remove circulator, FFT conversion module, subcarrier solution mapping block, channel estimator, equalizer and decision device; Described IFFT conversion module and described FFT conversion module share a FFT nuclear, and described FFT nuclear is multiplexing according to time division way; The method for designing of described assist in synchronization device is based on GPS and long loop prefix.
Alternatively, described subcarrier mapping block comprises: serial-parallel converter, be connected with one information source/channel encoder, be used for the sequence number according to the data that are received from described information source/channel encoder output, described data are divided into the first via data that are made of odd indexed and second circuit-switched data that is made of described even number sequence number; Clock rate behind serial to parallel conversion is half of clock frequency before the conversion; Qpsk modulator is connected with described serial-parallel converter, adopts the mode of planisphere mapping, and each QPSK symbol is as a subcarrier data, and the real part of each QPSK symbol is as the output on I road, and the imaginary part of each QPSK symbol is as the output on Q road; Symbol mapper is connected with described qpsk modulator, is used for one group of subcarrier data is mapped to an OFDM symbol; Add pilot cell, be connected with described symbol mapper, be the OFDM symbol insertion frequency pilot sign of described symbol mapper output.
Alternatively, described symbol mapper comprises: the real part memory is used for storage I circuit-switched data; The imaginary part memory is used for storage Q circuit-switched data; Logic control for generation of the address that writes of described real part memory and described imaginary part memory, determines that according to OFDM subcarrier mapping relations the next one writes the address, and writing position then is not empty subcarrier.
Alternatively, the described navigator that adds comprises control logic and local ROM memory, wherein, the block pilot frequency information of described OFDM symbol is stored in the described local ROM memory, and the output of described ROM memory and the output of described symbol mapper realize multiplexing by the MUX multiplexer; The described control logic that adds navigator produces enable signal and determines described MUX multiplexer output frequency pilot sign or data symbol.
Alternatively, described IFFT conversion module comprises: IFFT controller and by the control of described IFFT controller and multiplexing FFT nuclear.
Alternatively, described FFT nuclear adopts based on Radix-2
2Structure.
Alternatively, the described circulator that adds is used to each OFDM symbol to add Cyclic Prefix and cyclic suffix, comprising: two RAM memories are used for storing via the I circuit-switched data after the conversion of described IFFT conversion module, Q circuit-switched data respectively; Address generator is used for order and produces write address.
Alternatively, described window added device comprises: a local ROM memory is used for the time-domain response of storage raised cosine; Two multipliers, the I circuit-switched data, Q circuit-switched data that is used for having Cyclic Prefix and cyclic suffix multiply each other with the raised cosine of this locality respectively; Two local RAM memories are connected with two described multipliers respectively, are used for storing respectively the multiplication result of two described multipliers; Two adders are used for the cyclic suffix data of the current OFDM symbol respectively two described two local RAM memories are stored and the part Cyclic Prefix data addition of next OFDM symbol, obtain the OFDM Cyclic Prefix after the windowing.
Alternatively, described amplitude limiter comprises: a CORDIC converter, be used for receiving I circuit-switched data, the Q circuit-switched data that described window added device is exported, and realize rectangular coordinate to the conversion of polar coordinate representation form, amplitude information and the phase information of output time-domain signal; Comparator is used for the range value and the default range value that are received from described CORDIC converter output are compared; If described range value is less than default described range value, then described comparator is output as the range value of first CORDIC converter output, otherwise, if described range value is greater than default described range value, then described comparator is output as the default range value of first CORDIC converter output; Low pass filter is connected with described comparator, is used for the high fdrequency component that filtering hard-limiting introduces; The 2nd CORDIC converter is used for receiving the output of described low pass filter and the phase information that a described CORDIC converter is exported, and realizes that polar coordinates to the conversion of rectangular coordinate representation, obtain I circuit-switched data, the Q circuit-switched data of quadrature and homophase.
Alternatively, described up-sampling filter comprises: interpolater, with described amplitude limiter, finish the interpolation between the sampled point, and the sampling rate after the interpolation becomes M times before the interpolation; The FIR filter is connected with described interpolater, is used for suppressing signal frequency domain periodic extension component.
Alternatively, described interpolater two-port RAM, input port are data and basic clock rate before the interpolation, output port be data and basic clock rate after the interpolation M doubly, the address at two ends is sequential access, input port is ahead of output port on the time.
Alternatively, described downsampling filter comprises: the FIR filter is used for suppressing signal frequency domain periodic extension component; Withdrawal device is connected with described FIR filter, extracts some subcarriers from all subcarriers.
Alternatively, described Cyclic Prefix and cyclic suffix of going circulator to be used for removing each OFDM symbol comprises: two RAM memories are used for storing respectively I circuit-switched data, Q circuit-switched data via described assist in synchronization device output; Address generator is used for the order generation and reads the address.
Alternatively, described FFT conversion module comprises: FFT controller and the multiplexing FFT nuclear of being controlled by described FFT controller.
Alternatively, described subcarrier solution mapping block comprises: the pilot sub-carrier extractor comprises: for generation of a local counter of the enable signal of frequency pilot sign; And under the effective situation of the enable signal of frequency pilot sign, be respectively applied to store the I circuit-switched data of FFT conversion module output, two pilot tone RAM memories of Q circuit-switched data; The data subcarrier extractor comprises: for generation of a local counter of the enable signal of data symbol; And under the effective situation of the enable signal of data symbol, be respectively applied to store the I circuit-switched data of FFT conversion module output, two data RAM memories of Q circuit-switched data; Two described pilot tone RAM memories and two described data RAM memories share one and read address generator, according to the subcarrier mapping ruler, extract data subcarrier and pilot sub-carrier, delete empty subcarrier.
Alternatively, described channel estimator comprises: local pilot tone ROM memory, and the enable signal control of the pilot signal that is provided by described pilot sub-carrier extractor when the enable signal of pilot signal when being effective, is exported the frequency pilot sign of storing among the local ROM successively; Complex divider, wherein, dividend links to each other with the output of pilot sub-carrier extractor, and divisor links to each other with local pilot tone ROM memory, the frequency pilot sign of complex divider after with local frequency pilot sign and demodulation is divided by, and obtains the least square LS estimated result of current channel response; Tunable filter is connected with described complex divider, is used for the least square LS estimated result of described complex divider output is carried out the filtering processing.
Alternatively, described equalizer comprises complex divider, the dividend of described complex divider links to each other with the output of data subcarrier extractor, divisor links to each other with the output of channel estimator, data subcarrier after the demodulation is divided by the channel estimating parameter, eliminate amplitude and phase distortion that data subcarrier causes in transmission course, obtain I circuit-switched data, Q circuit-switched data corresponding on the planisphere.
Alternatively, described decision device comprises: the hard decision device, comprise the QPSK de-mapping device, link to each other with I circuit-switched data, the Q circuit-switched data of described equalizer output, be used for by judging the positive and negative of I circuit-switched data, Q circuit-switched data, obtain the 2bit data corresponding with qpsk modulator, and described 2bit is sent to described channel decoder; The soft-decision device is used for I circuit-switched data, the Q circuit-switched data of described equalizer output directly are sent to described channel decoder through parallel serial conversion.
The present invention is in providing base band processing device, and IFFT conversion module and FFT conversion module is multiplexing, that is, IFFT conversion module and FFT conversion module share a FFT nuclear, have saved hardware resource.
In addition, the base band processing device that provides of the present invention, assist in synchronization device has wherein adopted the mentality of designing based on GPS and long loop prefix, saved the frame head expense of physical frame, and utilize GPS and Cyclic Prefix to carry out synchronously, and need not complicated acquisition algorithm, improved the availability of frequency spectrum.
Description of drawings
Fig. 1 is the high-level schematic functional block diagram in one embodiment of base band processing device of the present invention.
Fig. 2 is based on Radix-2
2Handle structural representation.
Fig. 3 is the structural representation that is applied to amplitude limiter of the present invention.
Fig. 4 is for being applied to FIR multiphase filter structure of the present invention.
Fig. 5 a and Fig. 5 b are respectively among the schematic diagram of method for synchronous of the prior art and the present invention the assist in synchronization device based on the schematic diagram of the method for synchronous of GPS and long loop prefix.
Fig. 6 is the structural representation that is applied to channel estimator of the present invention.
Embodiment
The present inventor finds: in the multicarrier system of the Base-Band Processing technology that has wireless sense network now, the FFT device is two self-contained units in IFFT device in the modulation circuit and the demodulator circuit, when if Fourier transform length is longer, these two devices can take a large amount of resources; In addition, in multicarrier system, the ofdm signal of transmission comprises frame head, frequency pilot sign and data symbol, can consume a large amount of hardware resources when carrying out synchronous computing.Therefore, for preventing above-mentioned each problem, the present inventor improves prior art, a kind of new base band processing device is provided, mainly be to utilize a shared FFT to examine the multiplexing of existing IFFT conversion module and FFT conversion module, and in the assist in synchronization device, adopted mentality of designing based on GPS and long loop prefix, saved the frame head expense of physical frame, utilize GPS and Cyclic Prefix to carry out synchronously, need not complicated acquisition algorithm, improve the availability of frequency spectrum, saved system resource.
Below in conjunction with the more complete description the present invention of diagram, preferred embodiment provided by the invention, but should not be considered to only limit among the embodiment set forth herein.Reference diagram is schematic diagram of the present invention, and the expression among the figure is illustrative nature, should not be considered to limit the scope of the invention.
Fig. 1 is the high-level schematic functional block diagram in one embodiment of base band processing device of the present invention.As shown in Figure 1, in the wireless sense network that described base band processing device is applied to be made up of video sensor, during wireless sense network goes for several scenes such as for example Smart Home, environmental monitoring, Industry Control, ground observation, military surveillance or uses.Here, described Base-Band Processing is based on multicarrier system.
In the present invention, described base band processing device comprises digital modulation circuit and digital demodulating circuit, wherein, described digital modulation circuit comprises: subcarrier mapping block 11, IFFT conversion module 12, add circulator 13, window added device 14, amplitude limiter 15 and up-sampling filter 16; Described digital demodulating circuit comprises: downsampling filter 21, assist in synchronization device 22, remove circulator 23, FFT conversion module 24, subcarrier solution mapping block 25, channel estimator 26, equalizer 27 and decision device 28.
Below above-mentioned each device is elaborated.
Serial-parallel converter 111 is connected with information source/channel encoder 30, and the sequence number according to the data that are received from 30 outputs of information source/channel encoder splits into two-way with described data, and wherein, the data of odd indexed are as the first via, and the data of even number sequence number are as the second the tunnel.In addition, the clock rate behind serial to parallel conversion is half of clock frequency before the conversion.
The input of qpsk modulator 112 links to each other with the output of serial-parallel converter 111, adopts the mode of planisphere mapping, and each QPSK symbol is as a subcarrier data, described subcarrier data can be expressed as the form of plural number: 01--＞1-j, 00--＞1+j, 10--＞-1+j, 11--＞-1-j.The real part of each QPSK symbol is as the output (that is, the I circuit-switched data) on I road, and the imaginary part of each QPSK symbol is as the output (that is Q circuit-switched data) on Q road.
The input of symbol mapper 113 links to each other with the output of qpsk modulator 112, is used for one group of subcarrier data is mapped to an OFDM symbol.Here, symbol mapper 113 comprises two RAM memories (being called real part memory and imaginary part memory) and a logic control.Described real part memory is used for storage I circuit-switched data, described imaginary part memory is used for storage Q circuit-switched data, the write address of two RAM memories is produced by described control logic, determines that according to OFDM subcarrier mapping relations the next one writes the address, and writing position is not empty subcarrier.The sequence of addresses of reading of two RAM memories produces, and reads whole I road and Q circuit-switched data at every turn, and triggers an enable signal.
The input that adds pilot cell 114 links to each other with the output of symbol mapper 113, is used to the OFDM symbol of symbol mapper 113 outputs to insert frequency pilot sign.In the present invention, add pilot cell 114 and comprise a control logic and a local ROM memory, wherein, the block pilot frequency information of described OFDM symbol is stored in the local ROM memory, the output of the output of described ROM memory and symbol mapper 113 is multiplexing by a MUX, and the control logic that adds pilot cell 114 produces enable signal and determines MUX multiplexer output frequency pilot sign or data symbol.
IFFT conversion module 12 comprises IFFT controller 121 and examines 122 by 121 controls of IFFT controller and multiplexing FFT.IFFT controller 121 produces the control parameter of IFFT conversion.FFT nuclear 122 is multiplexing according to time division way by transmitting terminal and receiving terminal, disposes the prior art that FFT examines respectively with respect to transmitting terminal and receiving terminal, and the present invention can relatively save hardware resource.
Especially, FFT nuclear 122 adopts based on Radix-2
2Structure, so, the butterfly structure of existing Radix-2 has the structure with the same calculation requirement of Radix-4 again.Adopt three-dimensional linear subscript mapping:
See also Fig. 2, it has shown based on Radix-2
2Handle structural representation.As shown in Figure 2, FFT nuclear 122 is produced by IFFT controller 121 parameter is set, at first I circuit-switched data, the Q circuit-switched data of the output of subcarrier mapping block are delivered in the buffer storage before the first order butterfly computation nuclear, through the first order based on Radix-2
2The butterfly computation of butterfly computation nuclear after, send into the second level again based on Radix-2
2Butterfly computation nuclear before buffer storage in, through the second level based on Radix-2
2The butterfly computation of butterfly computation nuclear ..., by that analogy, send into the tenth grade based on Radix-2
2Butterfly computation nuclear before buffer storage in, through the tenth grade based on Radix-2
2The butterfly computation of butterfly computation nuclear, thereby finish 2
10=1024 fast Fourier transform is finally by crossing backward arithmetic unit arrangement output I circuit-switched data, Q circuit-switched data.
Add circulator 13 (also claim add CP device) be used to the OFDM symbol add Cyclic Prefix (Cyclic Prefix, CP) and cyclic suffix (Cyclic postfix CP), is used for resisting under the urban environment because multipath transmits the frequency selective fading that causes.
In the present invention, add circulator 13 and comprise two RAM memories and an address generator.Through the I circuit-switched data after 12 conversion of IFFT conversion module and Q circuit-switched data respectively as the input of two described RAM memories, write address is then produced in proper order by described address generator, read address elder generation from the high bit address of RAM memory, read RAM memory end address as the Cyclic Prefix of OFDM symbol, and then read the end address from the initial address of RAM memory and finish an output that comprises the Cyclic Prefix in OFDM System symbol.In addition, the adition process of the above-mentioned Cyclic Prefix of adding method of cyclic suffix is similar, and the prior art that is well known to those skilled in the art, so no longer give unnecessary details at this.
Window added device 14 links to each other with the output that adds circulator 13, is mainly used to accelerate the rate of decay of OFDM sideband, thereby reduces the interference that the multicarrier secondary lobe causes neighboring trace.Window added device 14 comprises: a local ROM memory, two multipliers, two local RAM memories, and two adders.For above-mentioned each device, wherein, described local ROM memory is used for the time-domain response of storage raised cosine; Two multipliers, the I circuit-switched data, Q circuit-switched data that is used for having Cyclic Prefix and cyclic suffix multiply each other with the raised cosine of this locality respectively; Two local RAM memories are connected with two described multipliers respectively, are used for storing respectively the multiplication result of two described multipliers; Two adders are used for the cyclic suffix data of the current OFDM symbol respectively two described two local RAM memories are stored and the part Cyclic Prefix data addition of next OFDM symbol, obtain the OFDM Cyclic Prefix after the windowing.Therefore said process comprises: I circuit-switched data, the Q circuit-switched data that will have Cyclic Prefix and cyclic suffix earlier delivers in two multipliers to multiply each other with the raised cosine of this locality respectively respectively, and two results that will obtain deposit in respectively in two RAM memories, two RAM memories are responsible for the cyclic suffix data of current sign are delivered in the adder part Cyclic Prefix data addition with next OFDM symbol, obtain the OFDM Cyclic Prefix after the windowing.
Fig. 3 has shown the structural representation that is applied to amplitude limiter of the present invention.As shown in Figure 3, amplitude limiter 15 comprises: two CORDIC (Coordinate Rotation Digital Computer, the rotation of coordinate numerical calculation) converter (being designated hereinafter simply as: a CORDIC converter 151 and the 2nd CORDIC converter 151), a comparator 152, and a low pass filter 154.The I circuit-switched data of window added device 14 output, Q circuit-switched data be as the input of a CORDIC converter 151, and a CORDIC converter 151 realizes that rectangular coordinates to the conversion of polar coordinate representation form, export amplitude information and the phase information of time-domain signal; Range value and default range value two inputs of device 152 as a comparison of 151 outputs of the one CORDIC converter, if the range value of a CORDIC converter 151 outputs is less than default range value, then comparator 152 is output as the range value of a CORDIC converter 151 outputs, otherwise, if the range value of a CORDIC converter 151 outputs is greater than default range value, then comparator 152 is output as default range value; The output that is input as comparator 152 of low pass filter 154, low pass filter 154 are used for the high fdrequency component that filtering hard-limiting is introduced, and method for designing and operation principle thereof are fairly simple, think prior art well-known to those skilled in the art, so no longer give unnecessary details at this; The output of low pass filter 154 and a CORDIC converter 151 output and done to postpone to handle by a delay cell after phase information as the input of the 2nd CORDIC converter 153, the 2nd CORDIC converter 153 realizes that polar coordinates to the conversion of rectangular coordinate representation, obtain I circuit-switched data, the Q circuit-switched data of quadrature and homophase.
Up-sampling filter 16 comprises an interpolater and a FIR filter.
Described interpolater links to each other with amplitude limiter 15, mainly finishes the interpolation between the sampled point, and the sampling rate after the interpolation becomes M times before the interpolation.Described interpolater is realized by a two-port RAM memory, input port is data and basic clock rate before the interpolation, output port be data and basic clock rate after the interpolation M doubly, the address at two ends is sequential access, input port is ahead of output port on the time.
Described FIR filter is mainly used to suppress signal frequency domain periodic extension component, in order to save hardware resource, adopts heterogeneous structure to design.See also Fig. 4, it has shown and has been applied to FIR multiphase filter structure of the present invention.As shown in Figure 4, suppose that filter coefficient is N, at first the I circuit-switched data after the interpolation, Q circuit-switched data (inserting M-1 individual 0) are sent non-0 data into N/M register in proper order according to basic clock rate, and filter coefficient divided into groups, M organizes altogether, every group of N/M coefficient, then with the input as multiplier of packet filtering device coefficient and non-0 data, filter coefficient divides into groups to switch by the multiplier timeticks, the multiplier clock is M times of basic clock, at last the result of N/M multiplier is merged addition and is exported.
Downsampling filter 21 links to each other with the output of RF circuit, is used for the out-of-band noise of filtered signal.In the present invention, downsampling filter 21 comprises a FIR filter and a withdrawal device.Described FIR filter is used for suppressing signal frequency domain periodic extension component; Described withdrawal device is connected with described FIR filter, is used for extracting some subcarriers from all subcarriers.
It should be noted that downsampling filter 21 also adopts heterogeneous structure, method for designing is the inverse process of up-sampling filter 16, therefore, repeats no more here.
See also Fig. 5 a and Fig. 5 b, it has shown that respectively the assist in synchronization device is based on the schematic diagram of the method for synchronous of GPS and long loop prefix among the schematic diagram of method for synchronous of the prior art and the present invention.In conjunction with Fig. 5 a and Fig. 5 b, in the present invention, the method for designing of assist in synchronization device 22 is based on GPS (Global Positioning System, global positioning system) and long loop prefix, thus frame head expense and the required great amount of hardware resources of related algorithm of having saved physical frame.Described GPS uses for video sensor running fix, only needs here the pulse per second (PPS) output of GPS is got final product.Assist in synchronization device 22 be input as the GPS pulse per second (PPS), the local timer that is used for resetting, local timer is exported coarse synchronization signal by calculating frame length.There are certain overgauge (thick synchronization point is ahead of true synchronization constantly) constantly in thick synchronization point and true synchronization, this overgauge allows in having the multicarrier system of long loop prefix, the frequency-domain equalizer of back can be offset this deviation, and can not exert an influence to error performance.Need to prove, because there is overgauge (transmission delay Δ t), can reduce the ability of anti-multipath of multicarrier system, but because in urban environment, we generally select circulating prefix-length is 3～5 times of maximum multipath time-delay or more, and Δ t as can be known, so can not have problems under application-specific.
Go circulator 23 to link to each other with the output of assist in synchronization device, be used for removing Cyclic Prefix and the cyclic suffix of each OFDM symbol, comprising: two RAM memories are used for storing respectively I circuit-switched data, Q circuit-switched data via described assist in synchronization device output; Address generator is used for the order generation and reads the address.Because going the method for operation of circulator 23 is for adding the inverse process of circulator 13, so no longer give unnecessary details at this.
Subcarrier solution mapping block 25 comprises: pilot sub-carrier extractor 251 and data subcarrier extractor 252.
The enable signal control of the pilot signal that local pilot tone ROM memory 261 is provided by pilot sub-carrier extractor 251 when the enable signal of pilot signal when being effective, is exported the frequency pilot sign of storing among the local ROM successively.
Dividend in the complex divider 262 links to each other with the output of pilot sub-carrier extractor 251, divisor links to each other with local pilot tone ROM memory 261, the frequency pilot sign of complex divider 262 after with local frequency pilot sign and demodulation is divided by, and obtains the least square LS estimated result of current channel response.
In sum, the present invention has following advantage:
The present invention is in providing base band processing device, and IFFT conversion module and FFT conversion module is multiplexing, that is, IFFT conversion module and FFT conversion module share a FFT nuclear, have saved hardware resource.
In addition, the base band processing device that provides of the present invention, assist in synchronization device has wherein adopted the mentality of designing based on GPS and long loop prefix, saved the frame head expense of physical frame, and utilize GPS and Cyclic Prefix to carry out synchronously, and need not complicated acquisition algorithm, improved the availability of frequency spectrum.
Above-described embodiment just lists expressivity principle of the present invention and effect is described, but not is used for restriction the present invention.Any personnel that are familiar with this technology all can make amendment to above-described embodiment under spirit of the present invention and scope.Therefore, the scope of the present invention should be listed as claims.
Claims (18)
1. base band processing device that is applied to video sensor, comprise digital modulation circuit and digital demodulating circuit, wherein, described digital modulation circuit comprises: subcarrier mapping block, IFFT conversion module, add circulator, window added device, amplitude limiter and up-sampling filter; Described digital demodulating circuit comprises: downsampling filter, assist in synchronization device, remove circulator, FFT conversion module, subcarrier solution mapping block, channel estimator, equalizer and decision device;
It is characterized in that,
Described IFFT conversion module and described FFT conversion module share a FFT nuclear, and described FFT nuclear is multiplexing according to time division way;
The method for designing of described assist in synchronization device is based on GPS and long loop prefix.
2. base band processing device as claimed in claim 1 is characterized in that, described subcarrier mapping block comprises:
Serial-parallel converter is connected with one information source/channel encoder, is used for the sequence number according to the data that are received from described information source/channel encoder output, and described data are divided into the first via data that are made of odd indexed and second circuit-switched data that is made of described even number sequence number; Clock rate behind serial to parallel conversion is half of clock frequency before the conversion;
Qpsk modulator is connected with described serial-parallel converter, adopts the mode of planisphere mapping, and each QPSK symbol is as a subcarrier data, and the real part of each QPSK symbol is as the output on I road, and the imaginary part of each QPSK symbol is as the output on Q road;
Symbol mapper is connected with described qpsk modulator, is used for one group of subcarrier data is mapped to an OFDM symbol;
Add pilot cell, be connected with described symbol mapper, be the OFDM symbol insertion frequency pilot sign of described symbol mapper output.
3. base band processing device as claimed in claim 2 is characterized in that, described symbol mapper comprises:
The real part memory is used for storage I circuit-switched data;
The imaginary part memory is used for storage Q circuit-switched data;
Logic control for generation of the address that writes of described real part memory and described imaginary part memory, determines that according to OFDM subcarrier mapping relations the next one writes the address, and writing position then is not empty subcarrier.
4. base band processing device as claimed in claim 3, it is characterized in that, the described navigator that adds comprises control logic and local ROM memory, wherein, the block pilot frequency information of described OFDM symbol is stored in the described local ROM memory, and the output of described ROM memory and the output of described symbol mapper realize multiplexing by the MUX multiplexer; The described control logic that adds navigator produces enable signal and determines described MUX multiplexer output frequency pilot sign or data symbol.
5. base band processing device as claimed in claim 2 is characterized in that, described IFFT conversion module comprises: IFFT controller and by the control of described IFFT controller and multiplexing FFT nuclear.
6. base band processing device as claimed in claim 5 is characterized in that, described FFT nuclear adopts based on Radix-2
2Structure.
7. base band processing device as claimed in claim 5 is characterized in that, the described circulator that adds is used to each OFDM symbol to add Cyclic Prefix and cyclic suffix, comprising:
Two RAM memories are used for storing via the I circuit-switched data after the conversion of described IFFT conversion module, Q circuit-switched data respectively;
Address generator is used for order and produces write address.
8. base band processing device as claimed in claim 7 is characterized in that, described window added device comprises:
A local ROM memory is used for the time-domain response of storage raised cosine;
Two multipliers, the I circuit-switched data, Q circuit-switched data that is used for having Cyclic Prefix and cyclic suffix multiply each other with the raised cosine of this locality respectively;
Two local RAM memories are connected with two described multipliers respectively, are used for storing respectively the multiplication result of two described multipliers;
Two adders are used for the cyclic suffix data of the current OFDM symbol respectively two described two local RAM memories are stored and the part Cyclic Prefix data addition of next OFDM symbol, obtain the OFDM Cyclic Prefix after the windowing.
9. base band processing device as claimed in claim 8 is characterized in that, described amplitude limiter comprises:
The one CORDIC converter is used for receiving I circuit-switched data, the Q circuit-switched data that described window added device is exported, and realizes rectangular coordinate to the conversion of polar coordinate representation form, amplitude information and the phase information of output time-domain signal;
Comparator is used for the range value and the default range value that are received from described CORDIC converter output are compared; If described range value is less than default described range value, then described comparator is output as the range value of first CORDIC converter output, otherwise, if described range value is greater than default described range value, then described comparator is output as the default range value of first CORDIC converter output;
Low pass filter is connected with described comparator, is used for the high fdrequency component that filtering hard-limiting introduces;
The 2nd CORDIC converter is used for receiving the output of described low pass filter and the phase information that a described CORDIC converter is exported, and realizes that polar coordinates to the conversion of rectangular coordinate representation, obtain I circuit-switched data, the Q circuit-switched data of quadrature and homophase.
10. base band processing device as claimed in claim 9 is characterized in that, described up-sampling filter comprises:
Interpolater with described amplitude limiter, is finished the interpolation between the sampled point, and the sampling rate after the interpolation becomes M times before the interpolation;
The FIR filter is connected with described interpolater, is used for suppressing signal frequency domain periodic extension component.
11. base band processing device as claimed in claim 10, it is characterized in that, described interpolater is two-port RAM, input port is data and basic clock rate before the interpolation, output port be data and basic clock rate after the interpolation M doubly, the address at two ends is sequential access, and input port is ahead of output port on the time.
12. base band processing device as claimed in claim 9 is characterized in that, described downsampling filter comprises:
The FIR filter is used for suppressing signal frequency domain periodic extension component;
Withdrawal device is connected with described FIR filter, extracts some subcarriers from all subcarriers.
13. base band processing device as claimed in claim 12 is characterized in that, described Cyclic Prefix and cyclic suffix of going circulator to be used for removing each OFDM symbol comprises:
Two RAM memories are used for storing respectively I circuit-switched data, Q circuit-switched data via described assist in synchronization device output;
Address generator is used for the order generation and reads the address.
14., it is characterized in that described FFT conversion module comprises as claim 5 or 13 described base band processing devices: FFT controller and the multiplexing FFT nuclear of being controlled by described FFT controller.
15. base band processing device as claimed in claim 14 is characterized in that, described subcarrier solution mapping block comprises:
The pilot sub-carrier extractor comprises: for generation of a local counter of the enable signal of frequency pilot sign; And under the effective situation of the enable signal of frequency pilot sign, be respectively applied to store the I circuit-switched data of FFT conversion module output, two pilot tone RAM memories of Q circuit-switched data;
The data subcarrier extractor comprises: for generation of a local counter of the enable signal of data symbol; And under the effective situation of the enable signal of data symbol, be respectively applied to store the I circuit-switched data of FFT conversion module output, two data RAM memories of Q circuit-switched data;
Two described pilot tone RAM memories and two described data RAM memories share one and read address generator, according to the subcarrier mapping ruler, extract data subcarrier and pilot sub-carrier, delete empty subcarrier.
16. base band processing device as claimed in claim 15 is characterized in that, described channel estimator comprises:
Local pilot tone ROM memory, the enable signal control of the pilot signal that is provided by described pilot sub-carrier extractor when the enable signal of pilot signal when being effective, is exported the frequency pilot sign of storing among the local ROM successively;
Complex divider, wherein, dividend links to each other with the output of pilot sub-carrier extractor, and divisor links to each other with local pilot tone ROM memory, the frequency pilot sign of complex divider after with local frequency pilot sign and demodulation is divided by, and obtains the least square LS estimated result of current channel response;
Tunable filter is connected with described complex divider, is used for the least square LS estimated result of described complex divider output is carried out the filtering processing.
17. as claim 15 or 16 described base band processing devices, it is characterized in that, described equalizer comprises complex divider, the dividend of described complex divider links to each other with the output of data subcarrier extractor, divisor links to each other with the output of channel estimator, data subcarrier after the demodulation is eliminated amplitude and phase distortion that data subcarrier causes divided by the channel estimating parameter in transmission course, obtain I circuit-switched data, Q circuit-switched data corresponding on the planisphere.
18. base band processing device as claimed in claim 17 is characterized in that, described decision device comprises:
The hard decision device, comprise the QPSK de-mapping device, link to each other with I circuit-switched data, the Q circuit-switched data of described equalizer output, be used for by judging the positive and negative of I circuit-switched data, Q circuit-switched data, obtain the 2bit data corresponding with qpsk modulator, and described 2bit is sent to described channel decoder;
The soft-decision device is used for I circuit-switched data, the Q circuit-switched data of described equalizer output directly are sent to described channel decoder through parallel serial conversion.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105791197B (en) * | 2015-12-25 | 2019-04-26 | 中国科学院上海微系统与信息技术研究所 | A Pulse Shaping Filter for Offset Orthogonal Multi-Carrier Systems |
| CN105635022A (en) * | 2015-12-29 | 2016-06-01 | 中国科学院上海微系统与信息技术研究所 | Offset orthogonal multicarrier baseband system |
| CN105635022B (en) * | 2015-12-29 | 2018-09-18 | 中国科学院上海微系统与信息技术研究所 | A kind of offset quadrature multicarrier baseband system |
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