CN103187395B - Semiconductor interconnect structure and formation method - Google Patents
Semiconductor interconnect structure and formation method Download PDFInfo
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- CN103187395B CN103187395B CN201110454104.6A CN201110454104A CN103187395B CN 103187395 B CN103187395 B CN 103187395B CN 201110454104 A CN201110454104 A CN 201110454104A CN 103187395 B CN103187395 B CN 103187395B
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Abstract
A kind of semiconductor interconnect structure and formation method, described semiconductor interconnect structure comprises: metal interconnecting layer, the first metal lug that described metal interconnecting layer comprises metal level and is connected with described metal level edge; Be positioned at the conductive plunger on described first metal lug surface, wherein, described conductive plunger is greater than minimum design dimension to the distance of the end points of the first metal lug.When semiconductor interconnect structure is reduced to room temperature from higher manufacturing process temperature, described conductive plunger all can shrink to part first metal lug corresponding to the end points of the first metal lug and described conductive plunger part first metal lug corresponding to metal level edge, the stress produced is cancelled out each other, make the position of conductive plunger and metal lug relative dislocation can not occur, the position that described conductive plunger and metal lug contact can not produce cavity.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of semiconductor interconnect structure and formation method that can reduce interconnection layer stress migration.
Background technology
Along with the progress of semiconductor technology, the size during integrated circuit becomes more and more less, and when the integrated level of integrated circuit increases, chip surface cannot provide enough areas to make required interconnection line.Therefore, the structure of current very lagre scale integrated circuit (VLSIC) mostly adopts the metal interconnect structure of multiple-level stack.
In the metal interconnect structure of multiple-level stack, every one deck metal interconnecting layer all comprises some strip metal interconnection lines, between the metal interconnecting wires of same layer, utilize dielectric material isolated, between the metal interconnecting wires of different layers, also utilize dielectric material isolated, be connected by conductive plunger between the metal interconnecting wires of different layers.Because the thermal expansion coefficient difference of metal interconnecting layer and dielectric material is very large, therefore, when multiple-level stack metal interconnect structure residing for ambient temperature produce larger change time, metal interconnecting wires and the thermal stress difference suffered by dielectric material also very large, the metal interconnect structure of multiple-level stack is made to produce stress migration (StressMigration, SM).
When metal interconnect structure is reduced to room temperature from higher manufacturing process temperature, metal interconnecting layer and dielectric material all can shrink, because metal interconnecting layer is different from the thermal coefficient of expansion of dielectric material, described metal interconnecting layer can produce tensile stress, and particularly the position tensile stress that is connected with metal interconnecting layer of conductive plunger is the most concentrated.Described tensile stress can form room in a metal, and under the effect of tensile stress, excess vacancy diffusion in metal interconnecting wires, conductive plunger, nucleation, growth produce cavity in the position that conductive plunger is connected with metal interconnecting layer, thus cause interconnection resistance to increase even to cause metal interconnecting layer and conductive plunger electric isolation.Please refer to Fig. 1, the position be connected with metal interconnecting layer for conductive plunger in existing metal interconnect structure produces empty structural representation, and the position wherein between metal interconnecting wires 11 and conductive plunger 12 forms cavity 13.
Publication number is that the american documentation literature of US2006/0091557A1 discloses a kind of semiconductor device for reducing interconnection layer stress migration, please refer to Fig. 2, specifically comprise: substrate 20, be positioned at the metal interconnecting layer 21 on substrate 20 surface, be positioned at the interlayer dielectric layer 22 on described metal interconnecting layer 21 surface, run through the thickness of described interlayer dielectric layer 22 and the conductive plunger 23 be connected with described metal interconnecting layer 21, wherein, in described conductive plunger 23, be provided with fibrous carbon nanomaterials 24 equably.Because the covalent bond of described fibrous carbon nanomaterials 24 is higher than the bond energy of metallic bond, be separated and need larger energy, therefore, the conductive plunger 23 with described fibrous carbon nanomaterials 24 has good resistance to stress transfer ability.And there is high mechanical properties due to described fibrous carbon nanostructure, described fibrous carbon nanostructure enhances the mechanical strength of conductive plunger 23, and the position that conductive plunger 23 is connected with metal interconnecting layer 21, conductive plunger 23 be not by the impact of stress migration.
But the formation process of above-mentioned prior art is complicated, and do not mate with existing semiconductor fabrication process, production cost is high.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor interconnect structure and formation method, can improve the resistance to stress transfer ability of semiconductor interconnect structure, and formation process is simple.
For solving the problem, technical solution of the present invention provides a kind of semiconductor interconnect structure, comprising:
Metal interconnecting layer, the first metal lug that described metal interconnecting layer comprises metal level and is connected with described metal level edge;
Be positioned at the conductive plunger on described first metal lug surface,
Wherein, described conductive plunger is greater than minimum design dimension to the distance of the end points of the first metal lug.
Optionally, described conductive plunger is less than or equal to the distance of described conductive plunger to metal level edge to the distance of the end points of the first metal lug.
Optionally, described conductive plunger is more than or equal to 2 μm to the distance at metal level edge.
Optionally, the width of described metal lug is greater than the diameter of described conductive plunger, is less than or equal to 1.5 times of the diameter of described conductive plunger.
Optionally, described metal interconnecting layer also comprises the second metal lug, and described second metal lug is positioned at least side of the position that described conductive plunger contacts with the first metal lug and is connected with the first metal lug.
Optionally, described metal interconnecting layer also comprises at least one metal interconnecting wires, and described second metal lug is connected with metal level electricity by least one metal interconnecting wires.
Optionally, also comprise, be positioned at the pseudo-conductive plunger on described second metal lug surface.
Optionally, the area of described metal level is greater than the area of described first metal lug.
Technical solution of the present invention additionally provides a kind of formation method of semiconductor interconnect structure, comprising:
There is provided metal interconnecting layer, the first metal lug that described metal interconnecting layer comprises metal level and is connected with described metal level edge;
Interlayer dielectric layer is formed on described metal interconnecting layer surface;
In described interlayer dielectric layer, form the conductive plunger running through described interlayer dielectric layer, described conductive plunger is positioned at the first metal lug surface, and described conductive plunger is greater than minimum design dimension to the distance of the end points of the first metal lug.
Optionally, described metal interconnecting layer also comprises the second metal lug, and described second metal lug is positioned at least side of the position that described conductive plunger contacts with the first metal lug.
Optionally, described metal interconnecting layer also comprises at least one metal interconnecting wires, and described second metal lug is connected with metal level electricity by least one metal interconnecting wires.
Optionally, also comprise, form the pseudo-conductive plunger running through described interlayer dielectric layer in described interlayer dielectric layer, described pseudo-conductive plunger is positioned at the second metal lug surface.
Optionally, described pseudo-conductive plunger and conductive plunger are formed in same formation process.
Optionally, the material of described metal interconnecting layer and conductive plunger is copper, and formation process is layers for dual damascene copper interconnects technique.
Compared with prior art, technical solution of the present invention has the following advantages:
The first metal lug that the metal interconnecting layer of described semiconductor interconnect structure comprises metal level and is connected with described metal level edge, conductive plunger is positioned at described first metal lug surface, and described conductive plunger is greater than minimum design dimension to the distance of the end points of the first metal lug.When metal interconnect structure is reduced to room temperature from higher manufacturing process temperature, described conductive plunger all can shrink to part first metal lug corresponding to the end points of the first metal lug and described conductive plunger part first metal lug corresponding to metal level edge, the stress produced is cancelled out each other, make the position of conductive plunger and metal lug relative dislocation can not occur, the position that described conductive plunger and metal lug contact can not produce cavity.
Further, the at least side of the position that described conductive plunger contacts with the first metal lug is formed with the second metal lug, described second metal lug is connected with the first metal lug, the mechanical strength of described first metal lug can be strengthened, effectively can prevent the first metal lug from shrinking to the direction of metal level, avoid the position that conductive plunger is connected with the first metal lug and rupture.
Further, utilize metal interconnecting wires to be connected with metal level by described second metal lug, described conductive plunger is diminished to the interconnection resistance of metal level.
Further, pseudo-conductive plunger is formed on described second metal lug surface, the quantity in the room of the position utilizing described pseudo-conductive plunger to disperse conductive plunger to contact with the first metal lug, reduces the probability in the generation room, position that described conductive plunger contacts with the first metal lug.
Accompanying drawing explanation
Fig. 1 is that the position that in existing metal interconnect structure, conductive plunger is connected with metal interconnecting layer produces empty structural representation;
Fig. 2 is the structural representation of existing a kind of semiconductor device for reducing interconnection layer stress migration;
Fig. 3 to Fig. 6 is the structural representation of the semiconductor interconnect structure of the embodiment of the present invention;
Fig. 7 is the schematic flow sheet of the formation method of the semiconductor interconnect structure of the embodiment of the present invention;
Fig. 8 to Figure 10 is the cross-sectional view of the forming process of the semiconductor interconnect structure of the embodiment of the present invention.
Embodiment
The prior art formation process mentioned due to background technology is complicated, do not mate with existing semiconductor fabrication process, production cost is high, inventor finds, the described room for the formation of cavity is formed in the circular metal layer that the position contacted with silicon through hole and metal interconnecting layer is the center of circle, if the area of described metal interconnecting layer is very little, the quantity in the room that tensile stress is formed is few, the probability forming cavity will significantly reduce, thus, inventors herein propose a kind of semiconductor interconnect structure, please refer to Fig. 3, for the structural representation of the semiconductor interconnect structure of the present embodiment, comprise: metal interconnecting layer 01, the metal lug 03 that described metal interconnecting layer 01 comprises metal level 02 and is connected with described metal level 02 edge, be positioned at the conductive plunger 04 on described metal lug 03 surface, wherein, described conductive plunger 04 is minimum design dimension to the distance S1 of the end points of metal lug 03.Described minimum design dimension is the minimum spacing of sidewall to metal interconnecting layer edge of the conductive plunger when layout-design, when the sidewall of conductive plunger is less than described minimum dimension to the spacing at metal interconnecting layer edge, due to the error of Alignment Process, easily make to only have partially conductive connector to be positioned at metal interconnecting layer surface, make interconnection resistance become large, affect the electric property of interconnection structure.Be diffused in by room the position that described conductive plunger 04 is connected with metal lug 03 in order to avoid the room that formed in described metal level 02 as far as possible and form cavity, described conductive plunger 04 is minimum design dimension to the distance on the top of metal lug 03, to make described conductive plunger 04 maximum to the distance at described metal level 02 edge.Due to compared with metal level 02, the area of described metal lug 03 is less, the quantity in the room that metal lug 03 produces is few, and the position being not easy to be connected with metal lug 03 at described conductive plunger 04 forms cavity, can not affect the electric property of metal interconnect structure.
But inventor finds through experiment, although the area of metal lug is very little, the negligible amounts in the room produced by the effect of tensile stress, cavity be ruptured or be formed in the position that conductive plunger is connected with metal lug still may.Inventor finds through research, this mainly because: when metal interconnect structure is reduced to room temperature from higher manufacturing process temperature, metal lug and dielectric material all can shrink, because metal interconnecting layer is different from the thermal coefficient of expansion of dielectric material, the distance that metal lug shrinks to the direction of metal level is larger, and conductive plunger is due to the stop of interlayer dielectric layer, the distance of shrinking is less, make the position of conductive plunger and metal lug that relative dislocation occur, there is fracture and produce cavity in the position that described conductive plunger and metal lug contact, metal interconnect structure resistance is become and even open circuit occurs greatly, chip is caused to be damaged.
For this reason, inventor, through research, also been proposed a kind of semiconductor interconnect structure, comprising: metal interconnecting layer, the first metal lug that described metal interconnecting layer comprises metal level and is connected with described metal level edge; Be positioned at the conductive plunger on described first metal lug surface, wherein, described conductive plunger is greater than minimum design dimension to the distance of the end points of the first metal lug.Due to when metal interconnect structure is reduced to room temperature from higher manufacturing process temperature, described conductive plunger also can shrink to part first metal lug that the end points of the first metal lug is corresponding, the described stress produced that shrinks offsets the described conductive plunger of part part first metal lug corresponding to metal level edge to I haven't seen you for ages because the stress produced by cold events, the distance that described first metal lug is shunk to metal level direction reduces, avoid the position of described conductive plunger and the first metal lug is misplaced, there is fracture and produce cavity in the position causing described conductive plunger and the first metal lug to contact.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
The embodiment of the present invention provide firstly a kind of semiconductor interconnect structure, please refer to Fig. 4, for the structural representation overlooking visual angle of the semiconductor interconnect structure of the embodiment of the present invention, specifically comprise: metal interconnecting layer 110, described metal interconnecting layer 110 comprises metal level 111, first metal lug 112 and the second metal lug 113; Described first metal lug 112 touches with the side edge of metal level 111; Be positioned at the conductive plunger 120 on described first metal lug 112 surface, wherein, the distance S2 of the end points of described conductive plunger 120 to the first metal lug 112 is greater than minimum design dimension; Described second metal lug 113 is positioned at the both sides of the position that described conductive plunger 120 contacts with the first metal lug 112.
The material of described metal interconnecting layer 110 is copper or aluminium, and in the present embodiment, the material of described metal interconnecting layer 110 is copper.
Described metal level 111 is the metal interconnecting layer that area is larger, if directly conductive plunger to be formed at described area larger metal level 111 surface, metal level catch a cold produce tensile stress can produce a lot of room, the position being very easy to contact with metal level at conductive plunger forms cavity.Therefore, need described conductive plunger to be formed at the less metal interconnecting layer surface of an area.In the present embodiment, described conductive plunger 120 is formed at the surface of described first metal lug 112.The shape of described first metal lug 112 is elongated rectangle, the width of described first metal lug 112 is greater than the diameter of described conductive plunger 120, be less than or equal to 1.5 times of the diameter of described conductive plunger 120, not only can ensure that described conductive plunger 120 can be fully formed the surface in described first metal lug 112, avoid the electric property affecting interconnection structure, and the first narrower metal lug 112 can ensure that the quantity in the room formed is also less, be conducive to reducing the probability forming cavity.When the cross section figure of described conductive plunger 120 is circular, described diameter is circular diameter; When the cross section figure of described conductive plunger 120 is square, described diameter is the foursquare length of side.Inventor finds through research, when described conductive plunger 120 is more than or equal to 2 μm to the distance at metal level 111 edge, the room produced in metal level 111 can not be diffused into the position that conductive plunger 120 contacts with the first metal lug 112, and the probability that the position that described conductive plunger 120 is contacted with the first metal lug 112 produces cavity reduces.In the present embodiment, described conductive plunger 120 equals 2 μm to the distance at metal level 111 edge.
When metal interconnect structure is reduced to room temperature from higher manufacturing process temperature, in order to avoid the position of the first metal lug 112 of causing because of the difference of the coefficient of expansion and conductive plunger 120 misplaces, described conductive plunger 120 is not positioned at the end points place of described first metal lug 112, and the distance S2 of the end points of described conductive plunger 120 to the first metal lug 112 is greater than minimum design dimension.And the first metal lug corresponding to the end points of described conductive plunger 120 to the first metal lug 112 is Part I 1121, described conductive plunger 120 is Part II 1122 to the first metal lug of metal level edge 111 correspondence, and described Part I 1121 and Part II 1122 are oppositely arranged.Because described Part I 1121 also can shrink, the described stress produced that shrinks offsets the described Part II 1122 of part because the stress produced by cold events to I haven't seen you for ages, the distance that described first metal lug 112 is shunk to metal level 111 direction reduces, avoiding the position of described conductive plunger 120 and the first metal lug 112 is misplaced, there is fracture and produces cavity in the position causing described conductive plunger 120 and the first metal lug 112 to contact.In the present embodiment, the length of described Part I 1121 equals the length of described Part II 1122, because the stress produced by cold events offsets both making, avoids the position of described conductive plunger 120 and the first metal lug 112 is misplaced.In other embodiments, the length of described Part I 1121 is less than the distance of described conductive plunger 120 to metal level edge 111.
In the present embodiment, described metal interconnecting layer 110 also comprises the second metal lug 113, and described second metal lug 113 is positioned at the both sides of the position that described conductive plunger 120 contacts with the first metal lug 112 and is connected with the first metal lug 112.In other embodiments, described second metal lug 113 is at least positioned at the side of the position that described conductive plunger 120 contacts with the first metal lug 112.Because the described first easier direction to metal level 111 of metal lug 112 is shunk, conductive plunger 120 and the first metal lug 112 is easily made to rupture, in the both sides of the position that described conductive plunger 120 contacts with the first metal lug 112, there is the second metal lug 113, described second metal lug 113 can strengthen the mechanical strength of described first metal lug 112, effectively can prevent the first metal lug 112 from shrinking to the direction of metal level 111, avoid the position that conductive plunger 120 is connected with the first metal lug 112 and rupture.
Although the position that the above embodiment of the present invention can effectively avoid conductive plunger 120 to contact with the first metal lug 112 produces cavity, described first metal lug 112 length is larger, width is less, resistance is larger, make overall interconnection resistance larger, therefore, another embodiment of the present invention additionally provides a kind of semiconductor interconnect structure, please refer to Fig. 5, specifically comprise: metal interconnecting layer 110, described metal interconnecting layer 110 comprises metal level 111, first metal lug 112, second metal lug 113 and metal interconnecting wires 114; Described first metal lug 112 touches with the side edge of metal level 111; Be positioned at the conductive plunger 120 on described first metal lug 112 surface, wherein, the distance of the end points of described conductive plunger 120 to the first metal lug 112 is greater than minimum design dimension; Described second metal lug 113 is positioned at the both sides of the position that described conductive plunger 120 contacts with the first metal lug 112; Described second metal lug 113 is connected with metal level 111 by described metal interconnecting wires 114.
In the present embodiment, described metal interconnecting wires 114 is connected with the edge of metal level 111 with the end points of the second metal lug 113 respectively.Because described second metal lug 113 is positioned at the both sides of described first metal lug 112, described metal interconnecting wires 114 is two metal wires parallel with described first metal lug 112.In other embodiments, the optional position of the second metal lug 113 can be connected with the edge of metal level 111 by described metal interconnecting wires 114, and each second metal lug 113 can connect multiple parallel metal interconnecting wires 114.Because many metal interconnecting wires 114 effectively can reduce the interconnection resistance between conductive plunger 120 and metal level 111, thus the electric property of described metal interconnect structure can be improved.
Because described second metal lug 113 can increase the area of the metal interconnecting layer around conductive plunger 120 on a small quantity, the room quantity produced by the effect of tensile stress can be increased on a small quantity, the embodiment of the present invention additionally provides a kind of semiconductor interconnect structure, please refer to Fig. 6, described second metal lug 113 surface is also formed with pseudo-conductive plunger 130.Described pseudo-conductive plunger 130 is not used in signal and connects, just in order to reduce the room quantity being gathered in the position that conductive plunger 120 contacts with the first metal lug 112, reduce the probability in the generation room, position that described conductive plunger 120 contacts with the first metal lug 112.The room produced due to the effect of tensile stress is not only gathered in the position that conductive plunger 120 contacts with the first metal lug 112, also can be gathered in the position that described pseudo-conductive plunger 130 contacts with the second metal lug 113, the quantity in the room of the position having disperseed conductive plunger 120 to contact with the first metal lug 112, reduces the probability in the generation room, position that described conductive plunger 120 contacts with the first metal lug 112.
In the present embodiment, described pseudo-conductive plunger 130 is formed at the position that the second metal lug 113 is connected with metal interconnecting wires 113, in other embodiments, when metal interconnecting layer only includes metal level, the first metal lug and the second metal lug, described pseudo-conductive plunger is positioned at the surface of described second metal lug.
The embodiment of the present invention additionally provides a kind of formation method of the semiconductor interconnect structure as described in above-described embodiment, please refer to Fig. 7, is the schematic flow sheet of the formation method of described semiconductor interconnect structure, comprises:
Step S101, provides metal interconnecting layer, the first metal lug that described metal interconnecting layer comprises metal level and is connected with described metal level edge;
Step S102, forms interlayer dielectric layer on described metal interconnecting layer surface;
Step S103, forms the conductive plunger running through described interlayer dielectric layer in described interlayer dielectric layer, and described conductive plunger is positioned at the first metal lug surface, and described conductive plunger is greater than minimum design dimension to the distance of the end points of the first metal lug.
Fig. 8 to Figure 10 is the cross-sectional view of the forming process of the conductive interconnect structures of the embodiment of the present invention.
Please refer to Fig. 8, metal interconnecting layer 110 is provided, the first metal lug 112 that described metal interconnecting layer 110 comprises metal level 111 and is connected with described metal level 111 edge.
In other embodiments, described metal interconnecting layer can also comprise described second metal lug of at least side being positioned at the position that conductive plunger to be formed contacts with the first metal lug, and described second metal lug is connected with metal level electricity by least one metal interconnecting wires.Because the concrete structure of described metal interconnecting layer is described in the above-described embodiments, therefore not to repeat here.
In the present embodiment, because the material of described metal interconnecting layer 110 is copper, the technique forming described metal interconnecting layer is layers for dual damascene copper interconnects technique.In other embodiments, when the material of described metal interconnecting layer 110 is aluminium, the technique of the described metal interconnecting layer of described formation is aluminium interconnection process.
Please refer to Fig. 9, form interlayer dielectric layer 140 on described metal interconnecting layer 110 surface.
The material of described interlayer dielectric layer 140 is silica or low-K dielectric material.The technique forming described interlayer dielectric layer 140 is chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition etc.
Please refer to Figure 10, the conductive plunger 120 running through described interlayer dielectric layer 140 is formed in described interlayer dielectric layer 140, described conductive plunger 120 is positioned at the first metal lug 112 surface, and the distance of the end points of described conductive plunger 120 to the first metal lug 112 is greater than minimum design dimension.
In the present embodiment, the electric conducting material of filling in described conductive plunger 120 is copper, and formation process is dual damascene copper interconnection structure.In other embodiments, also tungsten can be filled as electric conducting material in described conductive plunger.
In other embodiments, when described metal level comprises the second metal lug, form the pseudo-conductive plunger running through described interlayer dielectric layer in described interlayer dielectric layer, described pseudo-conductive plunger is positioned at the second metal lug surface.The structure of described pseudo-conductive plunger is identical with conductive plunger, and therefore, described pseudo-conductive plunger can be formed in same formation process with conductive plunger, to save processing step.
Because the concrete structure of described pseudo-conductive plunger is described in the above-described embodiments, therefore not to repeat here.
To sum up, the first metal lug that the metal interconnecting layer of the semiconductor interconnect structure of the embodiment of the present invention comprises metal level and is connected with described metal level edge, conductive plunger is positioned at described first metal lug surface, and described conductive plunger is greater than minimum design dimension to the distance of the end points of the first metal lug.When metal interconnect structure is reduced to room temperature from higher manufacturing process temperature, described conductive plunger all can shrink to part first metal lug corresponding to the end points of the first metal lug and described conductive plunger part first metal lug corresponding to metal level edge, the stress produced is cancelled out each other, make the position of conductive plunger and metal lug relative dislocation can not occur, the position that described conductive plunger and metal lug contact can not produce cavity.
Further, the at least side of the position that described conductive plunger contacts with the first metal lug is formed with the second metal lug, described second metal lug is connected with the first metal lug, the mechanical strength of described first metal lug can be strengthened, effectively can prevent the first metal lug from shrinking to the direction of metal level, avoid the position that conductive plunger is connected with the first metal lug and rupture.
Further, utilize metal interconnecting wires to be connected with metal level by described second metal lug, described conductive plunger is diminished to the interconnection resistance of metal level.
Further, pseudo-conductive plunger is formed on described second metal lug surface, the quantity in the room of the position utilizing described pseudo-conductive plunger to disperse conductive plunger to contact with the first metal lug, reduces the probability in the generation room, position that described conductive plunger contacts with the first metal lug.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a semiconductor interconnect structure, is characterized in that, comprising:
Metal interconnecting layer, the first metal lug that described metal interconnecting layer comprises metal level and is connected with described metal level edge;
Be positioned at the conductive plunger on described first metal lug surface,
Wherein, described conductive plunger is greater than minimum design dimension to the distance of the end points of the first metal lug, in order to make described conductive plunger to described first metal lug end points between stresses counteract part described in stress between conductive plunger to metal edge, described minimum design dimension is the minimum spacing of sidewall to metal interconnecting layer edge of conductive plunger;
Described metal interconnecting layer also comprises the second metal lug, and described second metal lug is positioned at least side of the position that described conductive plunger contacts with the first metal lug and is connected with the first metal lug;
Be positioned at the pseudo-conductive plunger on described second metal lug surface.
2. semiconductor interconnect structure as claimed in claim 1, it is characterized in that, described conductive plunger is less than or equal to the distance of described conductive plunger to metal level edge to the distance of the end points of the first metal lug.
3. semiconductor interconnect structure as claimed in claim 1, it is characterized in that, described conductive plunger is more than or equal to 2 μm to the distance at metal level edge.
4. semiconductor interconnect structure as claimed in claim 1, it is characterized in that, the width of described metal lug is greater than the diameter of described conductive plunger, is less than or equal to 1.5 times of the diameter of described conductive plunger.
5. semiconductor interconnect structure as claimed in claim 1, it is characterized in that, described metal interconnecting layer also comprises at least one metal interconnecting wires, and described second metal lug is connected with metal level electricity by least one metal interconnecting wires.
6. semiconductor interconnect structure as claimed in claim 1, it is characterized in that, the area of described metal level is greater than the area of described first metal lug.
7. a formation method for semiconductor interconnect structure, is characterized in that, comprising:
There is provided metal interconnecting layer, the first metal lug that described metal interconnecting layer comprises metal level and is connected with described metal level edge;
Interlayer dielectric layer is formed on described metal interconnecting layer surface;
The conductive plunger running through described interlayer dielectric layer is formed in described interlayer dielectric layer, described conductive plunger is positioned at the first metal lug surface, described conductive plunger is greater than minimum design dimension to the distance of the end points of the first metal lug, make described conductive plunger to described first metal lug end points between stresses counteract part described in stress between conductive plunger to metal edge, described minimum design dimension is the minimum spacing of sidewall to metal interconnecting layer edge of conductive plunger;
Described metal interconnecting layer also comprises the second metal lug, and described second metal lug is positioned at least side of the position that described conductive plunger contacts with the first metal lug;
In described interlayer dielectric layer, form the pseudo-conductive plunger running through described interlayer dielectric layer, described pseudo-conductive plunger is positioned at the second metal lug surface.
8. the formation method of semiconductor interconnect structure as claimed in claim 7, it is characterized in that, described metal interconnecting layer also comprises at least one metal interconnecting wires, and described second metal lug is connected with metal level electricity by least one metal interconnecting wires.
9. the formation method of semiconductor interconnect structure as claimed in claim 7, it is characterized in that, described pseudo-conductive plunger and conductive plunger are formed in same formation process.
10. the formation method of semiconductor interconnect structure as claimed in claim 7, it is characterized in that, the material of described metal interconnecting layer and conductive plunger is copper, and formation process is layers for dual damascene copper interconnects technique.
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