CN103179434B - Package receiver and method for processing packet thereof - Google Patents

Abstract

The packet processing method provided by the present invention is applied to a packet receiver. An approximate bit rate is first determined based on the respective timestamps of the two packets. Then, based on the timestamp of at least one other packet, the approximate bit rate is revised to generate a fine-tuned bit rate. The fine-tuned bit rate is used as a reference for reading one or more subsequent packets from a register. The timestamp of the other packet is provided according to the approximate bit rate.

Description

Packet receiver and its packet processing method

technical field

The present invention is related to wireless transmission technology, and especially related to the technology of determining the packet output rate according to the time stamp.

Background technique

With the advancement of communication technology, the development of digital TV broadcasting is becoming more and more mature. Digital video broadcasting-second generation terrestrial (DVB-T2) is currently the most widely used standard in this field, and the video encoding methods include MPE6-2, H.264/MPEG-4AVC and AVS. . Figure 1 is a schematic diagram of the relative relationship between the DVB-T2 wireless transmitter/receiver using the MPE6-2 specification.

Transmitter 10 includes encoder 12 and modulator 14 ; receiver 20 includes decoder 22 , demodulator 24 and register 26 . In this example, the encoder 12 is responsible for encoding data respectively corresponding to three different program channels to generate three transport streams (transferstream, TS) TS0, TS1, and TS2. Each Transport Stream contains multiple packets each. As shown in Figure 1, the modulator 14 unpacks these transport streams into data streams data_PLP0, data_PLP1, data_PLP2 and common_PLP. The data stream common_PLP is composed of the common data packets of the transport streams TS0, TS1, and TS2, and the data streams data_PLP0, data_PLP1, and data_PLP2 respectively include the data packets of the transport streams TS0-TS2 except the common data packets and null packets. Aggregating the common packets in the data stream common_PLP can save the bandwidth consumed by repeatedly transmitting the same packets.

In order to assist the receiver 20 to restore the transport stream correctly, the sender 10 will selectively record an input stream time reference (ISCR) value in each or some of the packets when generating the data packets. In practice, the modulator 14 may be provided with a counter that keeps counting. Every time a packet transmitted from the encoder 12 is received, the modulator 14 writes the current count value of the counter into the ISCR field of the packet.

Assuming that the user of the receiver 20 chooses to watch the program channel corresponding to the transport stream TS0, the demodulator 24 will combine the data streams data_PLP0 and common_PLP to generate the restored transport stream TS0', and then deliver the transport stream TS0' to the decoder 22 decoding. As shown in FIG. 1 , the demodulated data packets are first stored in the register 26 . The receiver 20 must determine the bit rate for reading packets from the register 26 according to the ISCR values recorded in these packets, so as to correctly reconstruct the transport stream TS0'.

Contents of the invention

In order to meet the above requirements, the present invention proposes a circuit architecture and a packet processing method for determining a packet reading rate according to a timestamp of the packet. In addition to determining an approximate bit rate based on the timestamp of the earlier packet, the timestamp of the subsequent packet can also be used to continuously correct the packet reading rate, so as to improve the accuracy of the packet reading rate. The concept proposed by the present invention can be applied to various situations where the packet reading rate needs to be determined according to the time stamp, not limited to the DVB-T2 receiving system adopting the MPEG-2 standard.

A specific embodiment according to the present invention is a packet processing method applied to a packet receiver. First, an approximate bit rate is determined according to a first timestamp of a first packet and a second timestamp of a second packet. Based on a third timestamp of at least a third packet, the approximate bit rate is revised to generate a fine-tuned bit rate. Then, according to the fine-tuned bit rate, a fourth packet is read. Wherein, the second packet is continuous with the first packet, the third packet is continuous with the second packet, and the fourth packet is continuous with the third packet.

Another specific embodiment according to the present invention is a packet receiver, which includes a register, a rough estimation module, a fine adjustment module and a control module. The register is used to temporarily store at least one packet. The rough estimation module is used for determining an approximate bit rate according to a first timestamp of a first packet and a second timestamp of a second packet. The fine-tuning module is used for correcting the approximate bit rate according to a third timestamp of at least one third packet, so as to generate a fine-tuned bit rate. The control module is used for controlling the register to output a fourth packet according to the fine-tuned bit rate. Wherein, the second packet is continuous with the first packet, the third packet is continuous with the second packet, and the fourth packet is continuous with the third packet.

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

Description of drawings

Figure 1 is a schematic diagram of the relative relationship between the DVB-T2 wireless transmitter/receiver using the MPEG-2 standard.

FIG. 2 is a circuit block diagram of a packet receiver according to an embodiment of the present invention.

Figure 3 shows an example of relative relationship among packets.

FIG. 4(A) is used to show a detailed implementation example of the fine-tuning module; FIG. 4(B) is used to show a detailed implementation example of the difference detection unit.

FIG. 5(A) and FIG. 5(B) show two detailed implementation examples of the correction unit.

FIG. 6 is an example of a detailed circuit relationship of the packet receiver according to the present invention.

Figure 7 is a graphical illustration of intermediate count values and control signals versus time.

8 and 9 are flowcharts of a packet processing method according to a specific embodiment of the present invention.

Description of main component symbols

10: Transmitter 12: Encoder

14: Modulator 20: Receiver

22: Decoder 24: Demodulator

26: Scratchpad TS0-TS2: Transport Stream

data_PLP0, data_PLP1, data_PLP2, common_PLP: data flow

300: packet receiver 32: register

34: Rough estimation module 36: Fine-tuning module

38: Control module P1, P2, P3: packet

362: Difference detection unit 364: Correction unit

362A: first counter 362B: subtractor

364A: first multiplier 364B: integrator

364C: adder 364D: second multiplier

364E: adder 32A: first storage unit

32B: second storage unit S82-S86: process steps

S84A-S84C: process steps S86A-S86E: process steps

detailed description

A specific embodiment according to the present invention is a packet receiver 300 as shown in FIG. 2 , which includes a register 32 , a rough estimation module 34 , a fine-tuning module 36 and a control module 38 . The following description will take the case where the packet receiver 300 is located in the DVB-T2 digital TV broadcast receiving end as an example, but not limited thereto. In this example, the temporary register 32 is used to temporarily store demodulated original packets in a certain transport stream (transportstream, TS), in which part or all of the packets are recorded with an input stream time reference (ISCR) Value, that is, with the reference timestamp provided by the sender (timestamp). The main work of the rough estimation module 34 , the fine-tuning module 36 and the control module 38 is to determine a fine-tuned bit rate according to these time stamps, as a reference for the subsequent output data packets of the register 32 .

The rough estimation module 34 is responsible for estimating a rough bit rate based on the packets received earlier by the packet receiver 300 . In practice, a duty cycle T of the counter responsible for generating the ISCR value at the transmitting end is known. The rough estimation module 34 calculates the approximate bit rate in units of duty cycle T. As shown in FIG. 3 , assuming that the ISCR values of the first and second packets P1 and P2 directly adjacent to each other are 100 and 300 respectively, it means that the time point when the register 32 outputs the packet P2 and the time point when the packet P1 is output It should be 200 duty cycles T apart. The rough estimation module 34 further considers the number of packets between two ISCR read packets to obtain the packet read rate. For example, if there are four nullpackets or data packets without ISCR values between the packets P1 and P2, the approximate bit rate is the reciprocal of [(300-100)*T]/5, That is 1/(40*T). The coarse estimation module 34 can use the above concept to infer an approximate bit rate based on the ISCR values of the two packets. It should be noted that there may be other packets between the packets P1 and P2 or between the packets P2 and P3, or two adjacent packets.

In fact, the approximate bit rate determined only based on the two ISCR values may have errors. For example, the count value of the counter responsible for generating the ISCR value at the transmitting end is usually an integer, but in fact the time interval between two packets may not be exactly an integer multiple of the duty cycle T. Therefore, the approximate bit rate estimated in the above way will not be the exact bit rate. If the subsequent packets are output from the register 32 only according to the approximate bit rate, the error deviation will accumulate and become larger. For example, suppose the approximate bit rate indicates that the output time interval between two packets is 10T, but the correct time interval is actually 10.1T, then after outputting 10 packets according to the approximate bit rate, the output time error will accumulate to 1T . In other words, the time when the eleventh packet is output by the register 32 will be faster than the correct time 1T.

As shown in FIG. 2 , the approximate bit rate generated by the coarse estimation module 34 is sent to the fine adjustment module 36 . The fine-tuning module 36 is used for modifying the approximate bit rate according to the ISCR value carried by at least one other packet (eg, the third packet P3 in FIG. 3 ), so as to generate a fine-tuned bit rate. FIG. 4(A) shows a detailed implementation example of the fine-tuning module 36, which is described as follows.

The fine-tuning module 36 in this example includes a difference detection unit 362 and a correction unit 364 , wherein the packet P3 and its ISCR value are originally stored in the register 32 . As shown in FIG. 4(A), the approximate bit rate generated by the rough estimation module 34 according to the ISCR values of the packets P1 and P2 is provided to the correction unit 364, and the correction unit 364 also provides the fine-tuned bit rate to the control module 38 for the control module 38 The time to provide the ISCR value of the packet P3 to the difference detection unit 362 is determined. It should be noted that before generating the bit rate correction amount, the correction unit 364 directly provides the approximate bit rate to the control module 38 . After generating the bit rate correction amount, the correction unit 364 provides the fine-tuned bit rate to the control module 38 . For the example of FIG. 3, the approximate bit rate is 1/(200*T). Therefore, before the fine-tuned bit rate is generated, the control module 38 controls the register 32 to provide the ISCR value of the packet P3 to the difference detection at the time point when the count length is 200*T after the packet P2 is output by the register 32 Unit 362. According to the approximate bit rate calculation, the ISCR value of the packet P3 is 300 plus 200, that is, 500, the ISCR value of the packet P2.

In this example, the sender actually writes the ISCR value of 501 into the packet P3 instead of 500. The difference detection unit 362 is used to subtract a receiving end count value 500 from the real ISCR value (also called the transmitting end count value) 501 of the packet P3 (the generation method will be described in detail later) to determine that the difference between the two count values is 1 . When this count difference is positive, it means that the approximate bit rate is too high and must be lowered. Conversely, when the count difference is negative, it indicates that the approximate bit rate is too low and must be increased. The correction unit 364 is used for generating a bit rate correction amount according to the count difference, and correcting the approximate bit rate according to the bit rate correction amount.

FIG. 4(B) is a detailed embodiment of the difference detection unit 362 . The difference detection unit 362 in this example includes a first counter 362A and a subtractor 362B. The ISCR value of the packet P2 can be used as the counting start value of the first counter 362A. Taking the situation in FIG. 3 as an example, the first counter 362A can count up from 300 and increment by 1 every other reference period T provided by a reference clock pulse. As shown in FIG. 4(B), the first counter 362A receives the reference clock pulse as a counting reference, and the period of the reference clock pulse is T. As mentioned above, the control module 38 controls the register 32 to provide the ISCR value of the packet P3 to the difference detection unit 362 after 200*T. The discrepancy detection unit 362 uses the counting result when receiving the ISCR value of the packet P3 as the counting value of the receiving end. Therefore, the sink count value is 500. The subtractor 362B is responsible for subtracting the receiving end count value from the transmitting end count value (real ISCR value of packet P3 ) to determine a count difference.

In one embodiment, the first counter 362A continues to count up from 500 after the count difference is generated. In another embodiment, after the difference detection unit 362 generates the count difference, it uses the count value of the transmitting end (ie, the ISCR value for comparison) just passed from the register 32 as a new counting value of the receiving end value. Taking the example in FIG. 3 as an example, the difference detection unit 362 can make the first counter 362A change to start counting up with the ISCR value 501 of the packet P3 after a count difference is generated. Likewise, every time a new ISCR value occurs, the counting start value of the first counter 362A can be updated. The advantage of this method is that the convergence behavior from the approximate bit rate to the correct bit rate is relatively stable without oscillation, and the convergence speed is fast.

FIG. 5(A) is a detailed embodiment of the correction unit 364 . The correction unit 364 in this example includes a first multiplier 364A, an integrator 364B, a frequency converter (not shown) and an adder 364C. The first multiplier 364A is used for multiplying the count difference by a first ratio Ki to generate a first multiplication result. The integrator 364B is used for accumulating the first multiplication result as a time correction amount. The first ratio Ki is not limited to a specific value, and can also be 1. A frequency converter is used to invert the approximate bit rate to generate an approximate packet spacing. The adder 364C is responsible for adding the approximate packet spacing and the time correction amount, and taking the inverse to generate the fine-tuned bit rate. In practice, the fine-tuned bit rate does not have to be processed in the time domain, and other methods can be used to obtain the result equivalent to the approximate packet spacing and the reciprocal of the time correction amount in the frequency domain, so as to In other words, the correction unit does not necessarily include a frequency converter, and this embodiment is only an example and is not limited thereto.

FIG. 5(B) is another detailed implementation example of the correction unit 364 . The modification unit 364 in this example further includes a second multiplier 364D and an adder 364E. The second multiplier 364D is used for multiplying the count difference by a second ratio Kp to generate a second multiplication result. The adder 364E is used for adding the accumulation result output by the integrator 364B to the second multiplication result, as the time correction amount. It can be seen from the above two illustrations that when the bit rate correction amount is 0, the correction unit 364 provides the approximate bit rate to the control module 38 . In practice, both the first ratio Ki and the second ratio Kp are not limited to specific values.

FIG. 6 is a detailed implementation example of the packet receiver 300 . In this example, the register 32 includes a first storage unit 32A for storing packet data and a second storage unit 32B for storing the timestamp (ISCR value) of each packet. In practice, the two storage units may be first-in-first-out (FIFO) type memories. As mentioned earlier, the coarse estimation module 34 is responsible for estimating an approximate bit rate based on the ISCR values of earlier packets. Taking the packet shown in FIG. 3 as an example, after receiving the ISCR values of the packets P1 and P2 , the rough estimation module 34 can generate an approximate bit rate and provide the approximate bit rate to the correction unit 364 . Before generating the bit rate correction amount, the correction unit 364 directly provides the approximate bit rate to the control module 38 . After generating the bit rate correction amount, the correction unit 364 provides the fine-tuned bit rate to the control module 38 .

The control module 38 generates a control signal according to the bit rate provided by the modification unit 364 , and provides the control signal to the first storage unit 32A, the second storage unit 32B and the difference detection unit 362 . Practically, these circuits can be designed to be triggered and take the next action whenever there is a voltage rising edge in the control signal. The first storage unit 32A can output a packet of data every time a rising voltage edge occurs in the control signal. If the packet data output by the first storage unit 32A has an ISCR value, the second storage unit 32B will correspondingly output the ISCR value of the packet when a rising voltage edge occurs in the control signal. For example, when the first storage unit 32A outputs the packet P3, the second storage unit 32B transmits the ISCR value of the packet P3 to the difference detection unit 362 at the same time.

The difference detection unit 362 checks whether there is a new ISCR value input every time a voltage rising edge occurs in the control signal. If the check result is yes, the discrepancy detection unit 362 promptly calculates the difference between the ISCR value (transmitting end count value) and the receiving end count value, and provides the count difference to the correction unit 364 for the correction unit 364 to generate fine-tuned bits basis for the rate. After receiving the fine-tuned bit rate, the control module 38 will generate the above-mentioned control signal according to the new bit rate.

In one embodiment, the control module 38 includes a second counter, and the fine-tuned bit rate corresponds to an initial count value of the second counter. The second counter counts down from the initial count value and subtracts 1 every other reference period to generate an intermediate count value. The reference period is also provided by the reference clock pulse. In practice, the second counter can be realized by using a numerically controlled oscillator (NCO). Taking the case where the approximate bit rate is 1/(5*T) and the time correction amount is 0.3 as an example, the initial count value is equal to 5.3. The second counter starts counting down from 5.3, and the change of the above-mentioned intermediate count value is 5.3, 4.3, 3.3, 2.3, 1.3, 0.3 in sequence. Whenever the intermediate count value is less than 1, the second counter subtracts 1 from the intermediate count value and adds the initial count value to generate a new count value. Therefore, after the intermediate count value drops to 0.3, the new count value is 0.3-1+5.3, which equals 4.6.

FIG. 7 is a graphical illustration of the intermediate count value and control signal versus time. As shown in FIG. 7, after a reference period T passes after the intermediate count value is less than 1, the second counter will make the control signal a high-level pulse to trigger the first storage unit 32A, the second storage unit 32B and the difference detection Unit 362. In addition, after a reference period T passes after the intermediate count value is less than 1, the second counter will count down from the new count value again. Taking the case where the new count value is 4.6 as an example, the change of the intermediate count value is 4.6, 3.6, 2.6, 1.6, 0.6 in sequence. If the new count value is 4.9, the change of the intermediate count value is 4.9, 3.9, 2.9, 1.9, 0.9 in sequence.

As shown in Figure 7, the distance between the first high-level pulse and the second high-level pulse in the figure is 6T, the distance between the second high-level pulse and the third high-level pulse is 5T, and the third high-level pulse The distance between the level pulse and the fourth high level pulse is also 5T. In fact, if the bit rate is fixed at 1/(5.3*T) after fine-tuning, in the long run, the average period of high-level pulses in the control signal will be correspondingly 5.3T. That is to say, the average bit rate of the output packets of the first storage unit 32A is equal to 1/(5.3*T). This method is suitable for situations where the output time of each packet is not required to be accurate, but it can still ensure that the long-term average packet reading rate is correct. The advantage of this method is that the fine-tuned bit rate can be generated more frequently, and can follow the bit rate of the transmitting end more closely.

Another specific embodiment according to the present invention is a packet processing method as shown in FIG. 8 . First, step S82 is to determine an approximate bit rate according to a first timestamp of a first packet and a second timestamp of a second packet. Next, step S84 is to modify the approximate bit rate according to a third time stamp of at least one third packet, so as to generate a fine-tuned bit rate. The third timestamp is provided according to the approximate bit rate. Step S86 is to read one or more subsequent packets according to the fine-tuned bit rate.

As shown in FIG. 9, step S84 may include three sub-steps. Step S84A is to read the third time stamp according to the approximate bit rate. Step S84B is to subtract a receiving end count value from the third time stamp to determine a count difference, wherein the receiving end count value is related to the second time stamp. Step S84C is to generate a bit rate correction amount according to the count difference, and correct the approximate bit rate according to the bit rate correction amount.

In addition, step S86 may also include five sub-steps. Step S86A is to count down from the initial count value corresponding to the fine-tuned bit rate. Step S86B is to subtract 1 every other reference period to generate an intermediate count value. Step S86C is to judge whether the current intermediate count value is less than 1. If the judgment result of step S86C is negative, the process will return to step S86B to continue counting down. If the judgment result of step S86C is yes, then step S86D will be executed to subtract 1 from the current intermediate count value less than 1 and add the initial count value to generate a new count value. Step S86E is to read a subsequent packet and count down from the new count value at intervals of a reference cycle after the intermediate count value is less than 1. After the step S86E, the process will return to the step S86B, and restart the countdown procedure.

It should be noted that the changes in the circuit operation process described above when introducing the packet receiver 300 can also be applied to the packet processing method shown in FIG. 8 and FIG. 9 , and the details will not be repeated here.

As mentioned above, the present invention proposes a circuit structure and a packet processing method for determining a packet reading rate according to the timestamp of the packet. In addition to determining an approximate bit rate based on the timestamp of the earlier packet, the timestamp of the subsequent packet can also be used to continuously correct the packet reading rate, so as to improve the accuracy of the packet reading rate. The concept proposed by the present invention can be applied to various situations where the packet reading rate needs to be determined according to the time stamp, not limited to the DVB-T2 receiving system adopting the MPEG-2 standard.

Through the above detailed description of the preferred embodiments, it is hoped that the features and spirit of the present invention can be described more clearly, rather than limiting the scope of the present invention by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the claimed patent scope of the present invention.

Claims (10)

1. A packet processing method for a packet receiver, comprising: (a) determining an approximate bit rate based on a first timestamp of a first packet and a second timestamp of a second packet; (b) generating a fine-tuned bit rate according to a third timestamp of a third packet and the approximate bit rate; and (c) reading a fourth packet according to the fine-tuned bit rate; Wherein, the second packet is continuous with the first packet, the third packet is continuous with the second packet, and the fourth packet is continuous with the third packet; Wherein step (b) comprises: (b1) reading the third timestamp according to the approximate bit rate; (b2) subtracting a receiver count value from the third timestamp to determine a count difference, wherein the receiver count value is associated with the second timestamp; and (b3) generating a bit rate correction amount according to the count difference, and generating the fine-tuned bit rate according to the bit rate correction amount and the approximate bit rate; The fine-tuned bit rate corresponds to an initial count value, and step (c) includes: (c1) counting down from the initial count value according to a reference period to generate an intermediate count value; (c2) when the intermediate count value is less than 1, decrementing the intermediate count value by 1 and adding the initial count value to generate a new count value; and (c3) Read the fourth packet and replace the initial count value with the new count value after a reference period after the intermediate count value is less than 1. 2. The packet processing method according to claim 1, comprising: counting up from a first count value according to a reference period to generate a count value, wherein the first count value corresponds to the second timestamp; and The count value when the third packet is read is selected as the count value of the receiving end. 3. The packet processing method according to claim 2, further comprising: After the count difference is generated, the first count value is replaced by the third timestamp. 4. packet processing method as claimed in claim 1, is characterized in that, step (b3) comprises: multiplying the count difference by a first ratio to generate a first multiplication result; and accumulating the first multiplication result, and generating the bit rate correction amount according to the first multiplication result. 5. packet processing method as claimed in claim 1, is characterized in that, step (b3) comprises: multiplying the count difference by a first ratio to generate a first multiplication result; accumulating the first multiplication result to generate an accumulation result; multiplying the count difference by a second ratio to generate a second multiplication result; and The accumulation result is added to the second multiplication result to generate an addition result, and the bit rate correction value is generated according to the addition result. 6. A packet receiver comprising: a register for temporarily storing at least one packet; a rough estimation module, used for determining an approximate bit rate according to a first timestamp of a first packet and a second timestamp of a second packet; a fine-tuning module, configured to generate a fine-tuned bit rate according to a third timestamp of a third packet and the approximate bit rate; and A control module, used to control the register to output a fourth packet according to the fine-tuned bit rate; Wherein, the second packet is continuous with the first packet, the third packet is continuous with the second packet, and the fourth packet is continuous with the third packet; in, The third timestamp is read from the register according to the approximate bit rate, and the fine-tuning module includes: a difference detection unit for subtracting a receiving end count value from the third time stamp to determine a count difference, wherein the receiving end count value is related to the second time stamp; and a correction unit, used to generate a bit rate correction amount according to the count difference, and generate the fine-tuned bit rate according to the bit rate correction amount and the approximate bit rate; The fine-tuned bit rate corresponds to an initial count value, and the control module includes: A second counter is used to count down from the initial count value according to a reference period to generate an intermediate count value; when the intermediate count value is less than 1, the second counter subtracts 1 from the intermediate count value and adds the initial count value value to generate a new count value; after a reference period passes after the intermediate count value is less than 1, the second counter controls the temporary register to output the fourth packet and replace the initial count value with the new count value. 7. The packet receiver according to claim 6, wherein the difference detection unit comprises: A first counter is used for counting up from a first count value according to a reference period to generate a count value, wherein the first count value corresponds to the second timestamp, when the third packet is sent from the temporary storage The count value when the register is read is the count value of the receiver; and A subtractor is used for subtracting the receiving end count value from the third timestamp to determine the count difference. 8. The packet receiver as claimed in claim 7, wherein the difference detection unit replaces the first count value with the third time stamp after the count difference is generated. 9. The packet receiver according to claim 6, wherein the correction unit comprises: a first multiplier for multiplying the count difference by a first ratio to generate a first multiplication result; an integrator for accumulating the first multiplication result; and An operation unit is used for generating the fine-tuned bit rate according to the approximate bit rate and the first multiplication result. 10. The packet receiver according to claim 6, wherein the correction unit comprises: a first multiplier for multiplying the count difference by a first ratio to generate a first multiplication result; an integrator for accumulating the first multiplication result to generate an accumulation result; a second multiplier for multiplying the count difference by a second ratio to generate a second multiplication result; an adder, used for adding the accumulation result and the second multiplication result to generate an addition result; and An operation unit is used for generating the fine-tuned bit rate according to the rough bit rate and the addition result.