CN103177769A - Method and device for optimizing mistake correcting mechanism - Google Patents
Method and device for optimizing mistake correcting mechanism Download PDFInfo
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- CN103177769A CN103177769A CN201310039159XA CN201310039159A CN103177769A CN 103177769 A CN103177769 A CN 103177769A CN 201310039159X A CN201310039159X A CN 201310039159XA CN 201310039159 A CN201310039159 A CN 201310039159A CN 103177769 A CN103177769 A CN 103177769A
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Abstract
The invention discloses a method and a device for optimizing a mistake correcting mechanism. The method comprises the following steps: an encoding module of the mistake correcting mechanism encodes original data through a shifting register, and obtains an odd-even verification bit of the original data; and a correction sub-calculating module of the mistake correcting mechanism calculates the original data and the odd-even verification bit through the shifting register, and obtains a syndrome needed by the mistake correcting mechanism. According to the method and the device, by adopting the mode that the encoding module and the correction sub-calculating module in the mistake correcting mechanism share one same shifting register according to different control signals, the working mode of the mistake correcting mechanism is optimized, the mistake correction performance of the mistake correcting mechanism is ensured, and the logic gate count of the mistake correcting mechanism is reduced, so that the area and the design cost of a flash memory chip are reduced, and the market competitiveness of the flash memory chip is improved.
Description
Technical field
The present invention relates to the flash memory technology field, relate in particular to a kind of method and device of optimizing wrong mechanism for correcting errors.
Background technology
Lifting along with technological level, the capacity of flash memory (Flash) is increasing, but can produce the problem of a series of data stability aspect thereupon, mistake mechanism for correcting errors (ECC mechanism) is most important for the data stability of flash memory (Flash), and the error correcting capability of wrong mechanism for correcting errors (ECC mechanism) is larger, hardware resource also just consumes larger, and mistake mechanism for correcting errors (ECC mechanism) has 4 main modules: 1. coding module; 2. syndrome computations module; 3. miscount polynomial expression module; 4. find the solution errors present and error correcting correction module.Along with the logic gate number of flash memory (Flash) chip is more and more, if do not do corresponding logic optimization, the area of chip will be increasing so, and cost also will be thereupon more and more higher, is unfavorable for the competition in market.Therefore it is necessary hardware resource in flash memory (Flash) chip being occupied that the larger wrong mechanism for correcting errors of proportion (ECC mechanism) is optimized.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of method and device of optimizing wrong mechanism for correcting errors, is intended to reduce the logic gate number of wrong mechanism for correcting errors.
In order to achieve the above object, the present invention proposes a kind of method of optimizing wrong mechanism for correcting errors, comprising:
Coding module by wrong mechanism for correcting errors is encoded to raw data by a shift register, obtains the parity check bit of described raw data;
Syndrome computations module by described wrong mechanism for correcting errors is calculated described raw data and described parity check bit by described shift register, obtains the required syndrome of described wrong mechanism for correcting errors.
Preferably, the coding module of described wrong mechanism for correcting errors is encoded to raw data by a shift register, and the step of obtaining the parity check bit of described raw data comprises:
Shift register is sent the first control signal, control described shift register and carry out in coding module coding to raw data;
Obtain the parity check bit of described raw data according to coding result.
Preferably, the syndrome computations module of described wrong mechanism for correcting errors is calculated described raw data and described parity check bit by described shift register, and the step of obtaining the required syndrome of described wrong mechanism for correcting errors comprises:
Shift register is sent the second control signal, control described shift register and carry out in the syndrome computations module calculating to described raw data and described parity check bit;
Obtain the required syndrome of described wrong mechanism for correcting errors according to result of calculation.
Preferably, described shift register is linear feedback shift register.
The present invention also proposes a kind of device of optimizing wrong mechanism for correcting errors, comprising:
Coding module is encoded to raw data by a shift register, obtains the parity check bit of described raw data;
The syndrome computations module is calculated described raw data and described parity check bit by described shift register, obtains the required syndrome of described wrong mechanism for correcting errors.
Preferably, described coding module comprises:
The control coding unit is used for shift register is sent the first control signal, controls described shift register and carries out in coding module coding to raw data;
The first acquiring unit is for obtain the parity check bit of described raw data according to coding result.
Preferably, described syndrome computations module comprises:
Control computing unit, be used for shift register is sent the second control signal, control described shift register and carry out in the syndrome computations module calculating to described raw data and described parity check bit;
Second acquisition unit is used for obtaining the required syndrome of described wrong mechanism for correcting errors according to result of calculation.
Preferably, described shift register is linear feedback shift register.
A kind of method and device of optimizing wrong mechanism for correcting errors that the present invention proposes, by allowing coding module and syndrome computations module in wrong mechanism for correcting errors share the mode of same shift register according to different control signals, optimized the mode of operation of wrong mechanism for correcting errors, both guaranteed the error-correcting performance of wrong mechanism for correcting errors, can reduce the logic gate number of wrong mechanism for correcting errors again, thereby reduce area and the design cost of flash chip, improved the market competitiveness of flash chip.
Description of drawings
Fig. 1 is the schematic flow sheet that the present invention optimizes the method preferred embodiment of wrong mechanism for correcting errors;
Fig. 2 is that the present invention optimizes in the method preferred embodiment of wrong mechanism for correcting errors and raw data encoded by a shift register by the coding module of wrong mechanism for correcting errors, obtains the schematic flow sheet of the parity check bit of described raw data;
Fig. 3 is that the present invention optimizes in the method preferred embodiment of wrong mechanism for correcting errors and described raw data and described parity check bit calculated by described shift register by the syndrome computations module of described wrong mechanism for correcting errors, obtains the schematic flow sheet of the required syndrome of described wrong mechanism for correcting errors;
Fig. 4 is the structural representation that the present invention optimizes the device preferred embodiment of wrong mechanism for correcting errors;
Fig. 5 is the structural representation that the present invention optimizes coding module in the device preferred embodiment of wrong mechanism for correcting errors;
Fig. 6 is the structural representation that the present invention optimizes syndrome computing module in the device preferred embodiment of wrong mechanism for correcting errors.
In order to make technical scheme of the present invention clearer, clear, be described in further detail below in conjunction with accompanying drawing.
Embodiment
The solution of the embodiment of the present invention is mainly: by allowing coding module and syndrome computations module in wrong mechanism for correcting errors share the mode of same shift register according to different control signals, optimized the mode of operation of wrong mechanism for correcting errors, both guarantee the error-correcting performance of wrong mechanism for correcting errors, and can reduce again the logic gate number of wrong mechanism for correcting errors.
As shown in Figure 1, preferred embodiment of the present invention proposes a kind of method of optimizing wrong mechanism for correcting errors, comprising:
Step S101 is encoded to raw data by a shift register by the coding module of wrong mechanism for correcting errors, obtains the parity check bit of described raw data;
The maximum error correcting capability of supposing wrong mechanism for correcting errors is 30bits, and under galois field 13 territories, when the wrong mechanism for correcting errors of raw data process, at first by the coding module of wrong mechanism for correcting errors, raw data is encoded, then obtain coding parity check bit afterwards, what adopt in cataloged procedure is that shift register removes coding.According to the condition of hypothesis the length of parity check bit be 13*30=390bits, so need the shift register of a 390bits to go to the storage parity position.
Step S102 is calculated described raw data and described parity check bit by described shift register by the syndrome computations module of described wrong mechanism for correcting errors, obtains the required syndrome of described wrong mechanism for correcting errors.
After step S101 obtains parity check bit, calculated by the syndrome computations module of described wrong mechanism for correcting errors and obtain the required syndrome of described wrong mechanism for correcting errors subsequent operation, the syndrome computations module is mainly that the data of decoding are as required calculated, and the data of decoding are comprised of the parity check bit that raw data and step S101 calculate.Maximum error correcting capability in the wrong mechanism for correcting errors of hypothesis is under the condition of 30bits so, and syndrome has at most 2*30, and establishing syndrome is S1, S2 ... S60 is owing to being 2 system error correcting code (BCH code), relational expression S
2n=S
n 2Set up, so just only need to calculate the syndrome S of odd-numbered
n, according to the condition of hypothesis, just only have 30 syndromes to need to calculate, total 30*13=390bits namely need the register of 390bits to go to deposit syndrome, and the syndrome computations module is also the shift register of use.As from the foregoing, because coding module computation of parity bits and syndrome computations module computing syndrome are all the shift registers of use, and the register that all needs identical figure place goes to deposit, so coding module and syndrome computations module can share a cover shift register, and this meets logic.The syndrome computations module is calculated described raw data and described parity check bit by the shift register in step S101, obtains the required syndrome of described wrong mechanism for correcting errors.
In preferred embodiment of the present invention, shift register is preferably linear feedback shift register, and linear feedback shift register has n register, and the input of previous stage has very large relation to the input of rear one-level, and the output of rear one-level affects again the result of previous stage.Get the output of every one-level register, the one group of shift register value that has just formed needs, then linear feedback shift register is sent different control signals and control linear feedback shift register and carry out the work of coding module or carry out the work of syndrome computations module, realize multiplexing to linear feedback shift register of coding module and syndrome computations module in wrong mechanism for correcting errors with this.
In step S101, particularly, at first linear feedback shift register is sent the first control signal, after linear feedback shift register identification the first control signal, carry out in coding module the coding to raw data, the output valve of line taking feedback shift register is the result of coding, is the parity check bit of described raw data.
In step S102, particularly, at first linear feedback shift register is sent the second control signal, after linear feedback shift register identification the second control signal, carry out in the syndrome computations module calculating to described raw data and described parity check bit, the result of the output valve of line taking feedback shift register for calculating is the required syndrome of described wrong mechanism for correcting errors.
Particularly, as shown in Figure 2, above-mentioned steps S101 can comprise:
Step S1011 sends the first control signal to shift register, controls described shift register and carries out in coding module coding to raw data;
Step S1012 obtains the parity check bit of described raw data according to coding result.
Particularly, as shown in Figure 3, above-mentioned steps S102 can comprise:
Step S1021 sends the second control signal to shift register, controls described shift register and carries out in the syndrome computations module calculating to described raw data and described parity check bit;
Step S1022 obtains the required syndrome of described wrong mechanism for correcting errors according to result of calculation.
The present embodiment passes through such scheme, allow coding module and syndrome computations module in wrong mechanism for correcting errors share the mode of same shift register according to different control signals, optimized the mode of operation of wrong mechanism for correcting errors, both guaranteed the error-correcting performance of wrong mechanism for correcting errors, can reduce the logic gate number of wrong mechanism for correcting errors again, thereby reduce area and the design cost of flash chip, improved the market competitiveness of flash chip.
As shown in Figure 4, preferred embodiment of the present invention proposes a kind of device of optimizing wrong mechanism for correcting errors, comprising: coding module 401, syndrome computations module 402 and shift register 403, wherein:
The maximum error correcting capability of supposing wrong mechanism for correcting errors is 30bits, and under galois field 13 territories, when the wrong mechanism for correcting errors of raw data process, at first encoded by 401 pairs of raw data of coding module of wrong mechanism for correcting errors, then obtain coding parity check bit afterwards, what adopt in cataloged procedure is that shift register 403 removes coding.According to the condition of hypothesis the length of parity check bit be 13*30=390bits, so need the shift register of a 390bits to go to the storage parity position.
After coding module 401 is obtained parity check bit, calculated by the syndrome computations module 402 of described wrong mechanism for correcting errors and obtain the required syndrome of described wrong mechanism for correcting errors subsequent operation, syndrome computations module 402 is mainly that the data of decoding are as required calculated, and the data of decoding are comprised of the parity check bit that raw data and coding module 401 calculate.Maximum error correcting capability in the wrong mechanism for correcting errors of hypothesis is under the condition of 30bits so, and syndrome has at most 2*30, and establishing syndrome is S1, S2 ... S60 is owing to being 2 system error correcting code (BCH code), relational expression S
2n=S
n 2Set up, so just only need to calculate the syndrome S of odd-numbered
n, according to the condition of hypothesis, just only have 30 syndromes to need to calculate, total 30*13=390bits namely need the register of 390bits to go to deposit syndrome, and syndrome computations module 402 is also the shift register of use.As from the foregoing, because coding module 401 computation of parity bits and syndrome computations module 402 computing syndromes are all the shift registers of use, and the register that all needs identical figure place goes to deposit, therefore coding module 401 and syndrome computations module 402 can share a cover shift register 403, and this meets logic.Syndrome computations module 402 is calculated by 403 pairs of described raw data of the shift register in coding module 401 and described parity check bit, obtains the required syndrome of described wrong mechanism for correcting errors.
In preferred embodiment of the present invention, shift register 403 is preferably linear feedback shift register, and linear feedback shift register has n register, and the input of previous stage has very large relation to the input of rear one-level, and the output of rear one-level affects again the result of previous stage.Get the output of every one-level register, the one group of shift register value that has just formed needs, then linear feedback shift register is sent different control signals and control linear feedback shift register and carry out the work of coding module 401 or carry out the work of syndrome computations module 402, realize the multiplexing of coding module 401 and 402 pairs of linear feedback shift registers of syndrome computations module in wrong mechanism for correcting errors with this.
Particularly, as shown in Figure 5, described coding module 401 can comprise: control coding unit 4011, the first acquiring unit 4012, wherein:
Control coding unit 4011 is used for shift register 403 is sent the first control signals, controls described shift register 403 and carries out in coding module 401 coding to raw data;
The first acquiring unit 4012 is for obtain the parity check bit of described raw data according to coding result.
Particularly, as shown in Figure 6, described syndrome computations module 402 can comprise: control computing unit 4021, second acquisition unit 4022, wherein:
The present embodiment passes through such scheme, allow coding module 401 and syndrome computations module 402 in wrong mechanism for correcting errors share the mode of same shift register 403 according to different control signals, optimized the mode of operation of wrong mechanism for correcting errors, both guaranteed the error-correcting performance of wrong mechanism for correcting errors, can reduce the logic gate number of wrong mechanism for correcting errors again, thereby reduce area and the design cost of flash chip, improved the market competitiveness of flash chip.
The above is only the preferred embodiments of the present invention; not thereby limit the scope of the claims of the present invention; every equivalent structure or flow process conversion that utilizes instructions of the present invention and accompanying drawing content to do; or directly or indirectly be used in other relevant technical field, all in like manner be included in scope of patent protection of the present invention.
Claims (8)
1. a method of optimizing wrong mechanism for correcting errors, is characterized in that, comprising:
Raw data is encoded by a shift register by the coding module in wrong mechanism for correcting errors, obtain the parity check bit of described raw data;
Described raw data and described parity check bit are calculated by described shift register by the syndrome computations module in described wrong mechanism for correcting errors, obtained the required syndrome of described wrong mechanism for correcting errors.
2. method according to claim 1, is characterized in that, describedly raw data encoded by a shift register by the coding module in wrong mechanism for correcting errors, and the step of obtaining the parity check bit of described raw data comprises:
Described shift register is sent the first control signal, control described shift register and carry out in coding module coding to raw data;
Obtain the parity check bit of described raw data according to coding result.
3. method according to claim 2, it is characterized in that, describedly described raw data and described parity check bit are calculated by described shift register by the syndrome computations module in wrong mechanism for correcting errors, the step of obtaining the required syndrome of described wrong mechanism for correcting errors comprises:
Described shift register is sent the second control signal, control described shift register and carry out in the syndrome computations module calculating to described raw data and described parity check bit;
Obtain the required syndrome of described wrong mechanism for correcting errors according to result of calculation.
4. according to claim 1-3 described methods, is characterized in that, described shift register is linear feedback shift register.
5. a device of optimizing wrong mechanism for correcting errors, is characterized in that, comprising:
Coding module is encoded to raw data by a shift register, obtains the parity check bit of described raw data;
The syndrome computations module is calculated described raw data and described parity check bit by described shift register, obtains the required syndrome of wrong mechanism for correcting errors.
6. device according to claim 5, is characterized in that, described coding module comprises:
The control coding unit is used for shift register is sent the first control signal, controls described shift register and carries out in coding module coding to raw data;
The first acquiring unit is for obtain the parity check bit of described raw data according to coding result.
7. device according to claim 6, is characterized in that, described syndrome computations module comprises:
Control computing unit, be used for shift register is sent the second control signal, control described shift register and carry out in the syndrome computations module calculating to described raw data and described parity check bit;
Second acquisition unit is used for obtaining the required syndrome of described wrong mechanism for correcting errors according to result of calculation.
8. according to claim 5-7 described devices, is characterized in that, described shift register is linear feedback shift register.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5680340A (en) * | 1990-11-08 | 1997-10-21 | Cirrus Logic, Inc. | Low order first bit serial finite field multiplier |
| CN101777922A (en) * | 2010-01-12 | 2010-07-14 | 殷雪冰 | High-speed and low-delay Berlekamp-Massey iteration decoding circuit for broadcast channel (BCH) decoder |
| CN102354535A (en) * | 2011-08-04 | 2012-02-15 | 记忆科技(深圳)有限公司 | Logical unit multiplexing system |
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- 2013-01-31 CN CN201310039159XA patent/CN103177769A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5680340A (en) * | 1990-11-08 | 1997-10-21 | Cirrus Logic, Inc. | Low order first bit serial finite field multiplier |
| CN101777922A (en) * | 2010-01-12 | 2010-07-14 | 殷雪冰 | High-speed and low-delay Berlekamp-Massey iteration decoding circuit for broadcast channel (BCH) decoder |
| CN102354535A (en) * | 2011-08-04 | 2012-02-15 | 记忆科技(深圳)有限公司 | Logical unit multiplexing system |
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