CN103165517A - Method for reducing interlayer dielectric layer dielectric constant - Google Patents

Abstract

The invention provides a method for reducing the dielectric constant of the interlayer dielectric layer: providing a semiconductor substrate whose surface sequentially includes a first etch stop layer and an interlayer dielectric layer from bottom to top; etching the interlayer dielectric layer , the etching is stopped to form a trench on the first etch stop layer, and metal copper is filled in the trench to form a metal interconnection layer of the current layer; a second etch stop layer is deposited on the surface of the formed metal interconnection layer; A patterned photoresist layer is formed on the surface of the second etching stop layer, and the opening of the patterned photoresist layer includes a predetermined area of metal copper and an interlayer dielectric layer between the metal copper; the patterned photoresist layer is mask, etch the second etch stop layer; using the second etch stop layer as a mask, etch back the interlayer dielectric layer between the metal copper to a predetermined depth; automatically form a conductive film on the exposed metal copper surface; remove The remaining interlayer dielectric layer between the copper metals forms a plurality of holes between the copper metals. The invention can reduce the RC delay of large-scale devices.

Description

Method for reducing dielectric constant of interlayer dielectric layer

technical field

The invention relates to semiconductor device manufacturing technology, in particular to a method for reducing the dielectric constant of an interlayer dielectric layer.

Background technique

At present, with the continuous development of integrated circuits, the number of metal interconnection layers in the back stage is becoming more and more dense. In order to reduce the resistance-capacitance (RC) delay of the entire integrated circuit (IC) and improve the electrical performance of the device, the existing technology provides A method for reducing the dielectric constant of the interlayer dielectric layer is proposed:

Step 11, referring to FIG. 1a, a semiconductor substrate 100 is provided in advance, and the surface of the semiconductor substrate 100 includes a first etch stop layer 101 and an interlayer dielectric layer (Inter-layer dielectric, ILD) 102 sequentially from bottom to top. ; The interlayer dielectric layer 102 is etched, the etching is stopped to form a groove on the first etch stop layer 101, and metal copper 103 is filled in the groove to form the current layer of metal interconnection layer; the interlayer dielectric layer generally adopts Low dielectric constant (Low-K) insulating material layer, such as black diamond (black diamond, BD) material similar to oxide (Oxide) containing silicon, oxygen, carbon, hydrogen, undoped silicate glass ( USG) or fluorinated glass (FSG), etc.;

Step 12, referring to FIG. 1b, depositing a second etch stop layer 104 on the surface of the metal interconnection layer formed;

Step 13, please refer to FIG. 1c, form a patterned photoresist layer 105 on the surface of the second etching stop layer 104, and the opening of the patterned photoresist layer includes a predetermined area of metal copper and a layer between metal copper intermediary layer;

Wherein, the openings of the photoresist layer are generally selected in areas where the trenches are relatively dense.

Step 14, referring to FIG. 1d, using the patterned photoresist layer 105 as a mask, etching the second etch stop layer 104;

Step 15, please refer to FIG. 1e, using the second etch stop layer 104 as a mask, etch the interlayer dielectric layer 102 between the metal copper to the surface of the first etch stop layer 101, and form a plurality of holes between the metal copper 103 106.

The hole is filled with air, and the dielectric constant of air is 1, while the dielectric constant of FSG and USG is greater than 3, and the dielectric constant of BD is 2.7-3. From the comparison of the dielectric constant, it can be seen that the formation of the hole makes the layer The overall dielectric constant of the interlayer is reduced. It should be noted that although the above method achieves the purpose of reducing the RC delay of the integrated circuit, for semiconductor devices with a large critical dimension (CD), due to the large space between the trenches, the subsequent deposition of the lower layer When the etch stop layer and the lower interlayer dielectric layer are used, the deposition layer is easy to fall into the hole, resulting in the blockage of the hole and the collapse of the deposition layer, so that the subsequent process cannot be carried out.

Therefore, how to reduce the RC delay of large-scale devices has become a problem to be solved in the industry.

Contents of the invention

In view of this, the technical problem solved by the present invention is: how to reduce the RC delay of large-scale devices.

In order to solve the problems of the technologies described above, the technical solution of the present invention is specifically implemented in the following way:

The invention discloses a method for reducing the dielectric constant of an interlayer dielectric layer, which is applied in the back-stage process of semiconductor devices. The method includes: providing a semiconductor substrate in advance, and the surface of the semiconductor substrate includes sequentially from bottom to top The first etch stop layer and the interlayer dielectric layer; the interlayer dielectric layer is etched, the etching stops to form a trench on the first etch stop layer, and metal copper is filled in the trench to form a current layer metal interconnection layer; the method also includes:

Depositing a second etch stop layer on the surface of the formed metal interconnection layer;

A patterned photoresist layer is formed on the surface of the second etching stop layer, and the opening of the patterned photoresist layer includes a predetermined area of metal copper and an interlayer dielectric layer between the metal copper;

Etching the second etching stop layer by using the patterned photoresist layer as a mask;

Using the second etching stop layer as a mask, etching back the interlayer dielectric layer between the metal copper to a predetermined depth;

Automatically form a conductive film on the exposed metal copper surface;

The remaining interlayer dielectric layer between the copper metals is removed to form a plurality of holes between the copper metals.

After removing the remaining interlayer dielectric layer between the copper metals, the method further includes sequentially depositing an underlying etch stop layer and an underlying interlayer dielectric layer.

The etching-back depth is 1/5-1/2 of the groove depth.

The conductive thin film is cobalt-tungsten phosphide CoWP formed by electroless electroplating selective deposition, and the thickness is 20-60 nanometers.

The remaining interlayer dielectric layer between the metal copper is removed by dilute hydrofluoric acid wet method.

The interlayer dielectric layer includes: black diamond BD, undoped silicate glass USG or fluorinated glass FSG.

It can be seen from the above-mentioned technical scheme that the present invention first etches the interlayer dielectric layer between the metal copper of the metal interconnection layer to a predetermined depth, and then removes the remaining layer between the remaining metal copper after covering the exposed metal copper surface with a conductive film. The inter-dielectric layer forms a plurality of holes between the metal copper. For large-scale semiconductor devices, the space between metal copper is relatively large, if like the prior art, the hole between the formed metal copper is also relatively wide, and the conductive film of the present invention has certain thickness, makes the hole between metal copper The opening is narrowed to support the lower etch stop layer and the lower interlayer dielectric layer, so that the lower etch stop layer and the lower interlayer dielectric layer will not collapse into the hole. Therefore, the present invention also achieves the purpose of reducing RC when manufacturing large-scale semiconductor devices.

Description of drawings

1a to 1e are specific cross-sectional schematic diagrams of a method for reducing the dielectric constant of an interlayer dielectric layer in the prior art.

FIG. 2 is a schematic flowchart of a method for reducing the dielectric constant of an interlayer dielectric layer according to an embodiment of the present invention.

2a to 2g are schematic cross-sectional views of a method for reducing the dielectric constant of an interlayer dielectric layer according to an embodiment of the present invention.

2h is a schematic cross-sectional structure diagram of a lower etching stop layer and a lower interlayer dielectric layer deposited on the surface of the current metal interconnection layer.

Detailed ways

In order to make the object, technical solution, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples.

The present invention has been described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the schematic diagram showing the structure will not be partially enlarged according to the general scale, which should not be used as a limitation of the present invention. In addition, in actual production In , the three-dimensional space dimensions of length, width and depth should be included.

The method for reducing the dielectric constant of an interlayer dielectric layer according to an embodiment of the present invention is shown in FIG. 2 , and includes the following steps. The method will be described in detail below in conjunction with FIGS. 2 a to 2 g.

Step 21, please refer to FIG. 2a, provide the metal interconnection layer of the current layer, specifically: provide a semiconductor substrate 100 in advance, and the surface of the semiconductor substrate 100 includes the first etch stop layer 101 and the interlayer Dielectric layer 102; etch the interlayer dielectric layer 102, stop etching to form a trench on the first etch stop layer 101, and fill the trench with metal copper 103 to form a current layer of metal interconnection layer; interlayer dielectric The layer generally adopts a Low-K insulating material layer, such as oxide-like black diamond material containing silicon, oxygen, carbon, and hydrogen elements, undoped silicate glass or fluorinated glass, etc.;

Step 22, referring to FIG. 2b, depositing a second etch stop layer 104 on the surface of the metal interconnection layer formed;

Step 23. Referring to FIG. 2c, a patterned photoresist layer 105 is formed on the surface of the second etching stop layer 104, and the opening of the patterned photoresist layer includes a predetermined area of metal copper and layers between metal copper intermediary layer;

Among them, the opening of the patterned photoresist layer is generally selected in the area where the grooves are relatively dense, and the opening of the patterned photoresist layer corresponds to the predetermined area of metal copper and the interlayer dielectric layer between the metal copper, which refers to the optical The resist layer 105 covers all the other areas where the grooves are relatively sparse, and forms openings in the predetermined area, that is, the selected area where the grooves are relatively dense, exposing the interlayer dielectric layer 102 and the metal copper 103 .

Step 24, please refer to FIG. 2d, use the patterned photoresist layer 105 as a mask to etch the second etch stop layer 104;

Step 25, please refer to FIG. 2e, use the second etch stop layer 104 as a mask, etch back the interlayer dielectric layer between the metal copper 103 to a predetermined depth;

Wherein, the etching-back depth is 1/5-1/2 of the trench depth, that is to say, the interlayer dielectric layer between the metal copper is not completely etched, but a part of the metal copper is exposed.

Step 26, please refer to FIG. 2f, automatically form a conductive film 200 on the surface of the exposed metal copper 103;

This step is the key of the present invention. In the embodiment of the present invention, the conductive film is cobalt-tungsten phosphide (CoWP) formed by electroless plating selective deposition, because this compound can only be deposited on the metal copper surface, and will not deposit On the surface of other substances, the formation of CoWP on the surface of metal copper is simple and easy to realize. CoWP will cover (coat) the exposed metal copper surface like a hat, that is, the upper surface and upper side wall of metal copper. CoWP also has a certain The thickness is specifically 20-60 nanometers. The thickness of the deposited CoWP is appropriately selected according to the size of the device, and cannot be too thin, so that the problems described in the prior art still occur when the space between the metal copper is large.

Step 27 , please refer to FIG. 2 g , remove the remaining interlayer dielectric layer between the metal copper 103 , and form a plurality of holes 201 between the metal copper 103 .

So far, the embodiment of the present invention realizes the method for reducing the dielectric constant of the interlayer dielectric layer.

Wherein, wet etching or dry etching may be used to remove the remaining interlayer dielectric layer between the copper metals. Taking wet etching as an example, dilute hydrofluoric acid can be used, which is a method well known to those skilled in the art, and will not be repeated here.

Further, the embodiment of the present invention also includes step 28, referring to FIG. 2h , depositing the lower etch stop layer 202 and the lower interlayer dielectric layer 203 in sequence. Those skilled in the art can know that trenches and connection holes can be formed on the underlying interlayer dielectric layer like the metal interconnection layer, and details will not be repeated here.

According to FIG. 2h, it can be seen that the method of the present invention can be applied to large-scale semiconductor devices, and the lower etch stop layer and the lower interlayer dielectric layer can well cover the current metal interconnection layer without collapse.

It should be noted that the embodiment of the present invention utilizes the characteristics of automatically forming a conductive film on the surface of metallic copper, and covers a layer of conductive film on the upper surface and upper sidewall of metallic copper. The conductive film has a certain thickness, so that the metallic copper The upper opening of the hole in between is narrowed to support the lower etch stop layer and the lower interlayer dielectric layer, so that the lower etch stop layer and the lower interlayer dielectric layer will not collapse into the hole. Other conductive films that can be automatically formed on the surface of metal copper are all within the protection scope of the present invention. Moreover, the conductive film is not limited to the CoWP formed by electroless electroplating selective deposition in the embodiment of the present invention, and can also be a conductive film obtained in any other way. The conductive film is integrated with metal copper, even if it is not removed later. Will not affect device functionality.

Through the method of the invention, on the basis of overcoming the problems of large-scale devices, the purpose of the invention is realized, and the dielectric constant of the interlayer dielectric layer is greatly reduced, thereby reducing the RC delay of the integrated circuit.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Claims (6)

1. a method that reduces the interlayer dielectric layer dielectric constant, be applied in the last part technology of semiconductor device, and the method comprises: semi-conductive substrate is provided in advance, and described semiconductor substrate surface comprises the first etch stop layer and interlayer dielectric layer from bottom to top successively; Interlayer dielectric layer is carried out etching, and etching stopping forms groove on the first etch stop layer, and fills metallic copper formation when a layer metal interconnecting layer in groove; It is characterized in that, the method also comprises:

Layer metal interconnecting layer surface deposition second etch stop layer of working as that is forming;

Photoresistance glue-line at the second etch stop layer surface formation patterning comprises the interlayer dielectric layer between presumptive area metallic copper and metallic copper in the opening of the photoresistance glue-line of described patterning;

Take the photoresistance glue-line of patterning as mask, etching the second etch stop layer;

Take the second etch stop layer as mask, return to carve interlayer dielectric layer between metallic copper to desired depth;

Automatically form conductive film at the copper surface that manifests;

Remove the residue interlayer dielectric layer between metallic copper, form a plurality of holes between metallic copper.

2. the method for claim 1, is characterized in that, after the residue interlayer dielectric layer of removing between metallic copper, the method further comprises the etch stop layer that deposits successively lower floor and the interlayer dielectric layer of lower floor.

3. method as claimed in claim 2, is characterized in that, returning and carving the degree of depth is 1/5～1/2 of gash depth.

4. method as claimed in claim 3, is characterized in that, described conductive film is the cobalt tungsten phosphide CoWP of the selectively deposited formation of electroless plating, and thickness is 20～60 nanometers.

5. method as claimed in claim 4, is characterized in that, the residue interlayer dielectric layer between described metallic copper adopts the diluted hydrofluoric acid wet method to remove.

6. the method for claim 1, is characterized in that, described interlayer dielectric layer comprises: carbonado BD, unadulterated silicate glass USG or fluoride glass FSG.

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