CN103165472A - Fiber channel (FC)-ball grid array (BGA) packaging bump distributed heat dissipation novel method - Google Patents

Abstract

The invention relates to a new heat dissipation method for FC-BGA packaging bump distribution, which is characterized in that it includes: effectively improving the heat dissipation problem of local hot spots through different distributions of bumps; The substrate of the chip is coated with a layer of metal; through the distribution of corresponding bumps, the heat is conducted out reasonably and quickly, thereby reducing the heat of the chip, making the chip reach heat balance as soon as possible, and the stable field of the entire packaging system reaches a stable state. In the FC-BGA structure, the heat dissipation is mainly through the bumps. The present invention uses Solidworks software for solid modeling. The model simulates the structural stable temperature field and the transient temperature field, and finds the key bumps, that is, the positions of the bumps with higher temperatures. Position classification, and then adjust the distribution of bumps, and increase the distribution density of bumps at the original higher temperature bumps, so that the heat can be transmitted to the substrate through the bumps reasonably and quickly to be dissipated.

Description

A New Method of Heat Dissipation for FC-BGA Package Bump Distribution

technical field

The present invention relates to a new heat dissipation method for FC-BGA packaging bump distribution, more specifically, it relates to classifying bump positions according to different bump temperatures, and then adjusting bump distribution. Proper position increases the distribution density of bumps, so that the heat can be conducted reasonably and quickly, thereby reducing the heat of the chip, so that the chip can reach the heat balance as soon as possible, and the stable field of the entire packaging system can reach a stable state.

technical background

FC-BGA (Flip Chip Ball Grid Array) is flip-chip ball grid array packaging, which is a mainstream high-end advanced packaging form at present, and is mainly used for large chips with more pins. Figure 1 shows a photo of a graphics accelerator chip packaged in FC-BGA.

FC-BGA combines the advantages of spherical packaging and flip-chip packaging technologies. First, it solves the problems of electromagnetic compatibility (EMC) and electromagnetic interference (EMI). Generally speaking, for chips using the previous Wire Bond packaging technology, the signal transmission is carried out through metal wires with a certain length. This method will produce the so-called impedance effect in the case of high frequency, forming a signal travel route. However, FC-BGA uses small balls instead of the original pins to connect the processor. This package uses a total of 479 balls, but the diameter is 0.78 mm, which can provide the shortest external connection distance. Figure 2 shows a typical structural diagram of an FC-BGA package with a copper alloy heat dissipation cover on an organic material substrate. Its components include: Adhesive (adhesive), Underfill (underfill), Solder Bump (solder bump), Die (chip) , Capacitor (capacitor), CuAlloy Lid (copper alloy heat dissipation cover), Solder Ball (solder ball), Organic Substrate (organic material substrate). The use of this package not only provides excellent electrical performance, but also reduces the loss and inductance between component interconnections, reduces the problem of electromagnetic interference, and withstands higher frequencies, making it possible to break through the overclocking limit.

Secondly, when the designers of display chips embed more and more dense circuits in the same silicon area, the number of input and output terminals and pins will increase rapidly, and another advantage of FC-BGA is that it can increase the I/O. Density of O. Generally speaking, the I/O leads using Wire Bond technology are arranged around the chip, but after the FC-BGA package is used, the I/O leads can be arranged on the surface of the chip in an array to provide higher density I/O. The /O layout produces the best use efficiency, and because of this advantage, the flip-chip technology reduces the area by 30% to 60% compared with the traditional packaging form.

The thermal management of electronic packaging refers to the reasonable cooling/radiation technology and structural design optimization of heat-consuming components and systems in the package, and the control of their temperature, so as to ensure the normal and reliable operation of electronic devices or systems.

There are two main sources of heat in the package. One is that the current flows in the chip inside the package to convert electrical energy into heat. Leads, resistors, polysilicon, etc. will generate heat after being energized, especially some core devices with high functional density ( Such as CPU) generates more heat; the second is the heat generated by the friction of flowable components inside the package, such as micromirror arrays. As heat builds up, if there is no effective flow path to carry the heat away, the temperature inside the package will continue to rise until the electronic device stops functioning or fails completely.

In the BGA structure, the heat generated by the chip is mainly transmitted through two ways, namely the internal way and the external way. The heat transfer resistance of the semiconductor itself, and then the heat transfer resistance of the adhesive layer between the chip and the substrate; the second is that after the heat flow reaches the substrate, it overcomes the conduction thermal resistance of the substrate and the conduction thermal resistance of the shell, so as to reach the outer surface of the shell. surface. In addition, part of the heat generated by the heat source passes through the inner space of the package to the inner surface of the shell through convection and radiation, and then overcomes the conduction thermal resistance of the shell to reach the outer surface. However, the thermal resistance of the inner space of the package is generally relatively large. , so the heat flow on this path can be ignored. The external way of heat flow transmission is mainly that the heat generated by the chip is conducted to the outer surface of the package, and then dissipates to the environment through convection and radiation. Fig. 3 is the simulated schematic diagram of the heat dissipation situation of FC-BGA encapsulation structure, and about 98.5% heat passes through this path of chip and substrate and the bump in the middle, so the heat dissipation of this path is dominant, and the present invention will also have Significance.

In the new generation of high-speed, highly integrated display chips, heat dissipation will be a big challenge. Based on the unique flip-package form of FC-BGA, the back of the chip can be exposed to the air and can dissipate heat directly. At the same time, the substrate can also improve the heat dissipation efficiency through the metal layer, and a metal heat sink is installed on the back of the chip to further enhance the heat dissipation capability of the chip and greatly improve the stability of the chip when it is running at high speed. At present, the research and analysis on the thermal performance of FC-BGA packaging mainly focuses on the chip size [1], the number of substrate layers, the thermal conductivity of the substrate, the thermal conductivity of the thermally conductive resin and the metal heat dissipation cover adhesive, and the structural parameters of the metal heat dissipation cover [2], etc. In terms of factors, Figure 4 is a graph of thermal resistance and airflow velocity with different substrate layers and with or without external heat sinks, and Figure 5 is the difference between junction temperature and ambient temperature and the thermal conductivity of the substrate with or without external heat sinks The following curve diagram [3].

In the existing research, the heat dissipation capability of the FC-BGA package can be improved through the selection of the substrate material, the selection of the number of substrate layers, and the placement of the heat sink. The ability to dissipate heat between the same substrate, thereby improving the heat dissipation capability of the entire packaging system.

With the rapid development of integrated circuits, especially ultra-large-scale integrated circuits, the volume of electronic components is getting smaller and smaller. At the same time, the power of chips is getting bigger and bigger, which leads to the increasing heat flux density in the package. In the 1970s By the 1990s, the heat flux density in integrated circuit chips increased from about 10W*cm ^-2 to 100W*cm ^-2 , and the current trend of increasing values is still continuing, as shown in Figure 6. The increasing trend of heat flux, such a large energy density, if the thermal management design cannot be reasonably carried out, it will lead to the failure of the microprocessor.

Statistics indicate that about 55% of the failures of electronic products are caused by overheating and heat-related problems. The failure of electronic devices is often closely related to its operating temperature. Within a certain temperature range, with the increase of temperature, the failure rate of electronic devices rises sharply. Studies have shown that the failure rate of devices increases exponentially with the increase of temperature. High temperature will have a series of effects on electronic components: electronic packages are made of materials with different thermal expansion coefficients, and thermal stress caused by mismatching thermal expansion coefficients will occur during production, manufacturing, testing, etc.; obvious temperature fluctuations will Lead to fatigue fracture of packaging materials; changes in temperature will cause changes in the current gain of transistors and integrated circuits, and the resulting changes in capacitance, resistance, etc. will affect the transmission characteristics of electrical signals.

The uneven distribution of chip power density will produce so-called local hot spots. The traditional heat dissipation technology can no longer meet the thermal design, management and control requirements of advanced electronic packaging. It not only limits the increase of chip power, but also causes excessive cooling. Bring unnecessary energy waste. Therefore, the present invention innovatively proposes a bump distribution method for FC-BGA packaging to effectively improve the heat dissipation problem of local hot spots, so that the heat generated at different positions of the chip can be reasonably and rapidly distributed through the corresponding bump distribution. Conduction out, thereby reducing the heat of the chip, so that the chip reaches heat balance as soon as possible, and the stable field of the entire packaging system reaches a stable state.

Contents of the invention

The present invention adjusts the bump distribution according to the temperature of the bump position, so that where the local heat of the chip is relatively high, the corresponding bump distribution density is relatively large, and where the local heat of the chip is relatively low, the bump distribution density is small, so that the heat Transmit quickly.

Figure 7 shows a schematic diagram of the FC-BGA package structure bump, and its components include: LSI chip (LSI chip), Solder Bump (solder bump), Heat Spreader (radiator), Underfill Resin (underfill resin), Stiffener (hardener), Build-up Layer (build layer), Core Layer (core layer). The common feature of the flip-chip connection structure is that the chips are attached face-down on the substrate, and the connection between the chip and the substrate uses bumps made of conductive materials. Generally, flip-chip connections with and without underfill are used. When the underfill is not used, the chip and the substrate are connected by bumps to conduct electrical properties and heat. When the underfill is used, there are different connections due to the anisotropy of the underfill, isotropic or the choice of insulating adhesive In the process structure, bumps still have an important influence.

For chips and bumps, the heat transfer between the bumps and the substrate is mainly in the form of heat conduction. The heat conduction problem in the package can be expressed by the one-dimensional Fourier equation:

$\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; kA</span>}\frac{\mathrm{<span\; class="notranslate">\; dT</span>}}{\mathrm{<span\; class="notranslate">\; dx</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

热流方向上的温度梯度；负号表示热量传递方向与温度升高方向相反。In the formula, q is the heat flux density; k is the thermal conductivity; A is the cross-sectional area perpendicular to the heat flow direction;

The temperature gradient in the direction of heat flow; a negative sign indicates that heat is transferred in the opposite direction to the temperature increase.

很相似，其中，热流q类似于电流I，温降ΔT类似于电压降ΔV。因此可以定义热阻为：From the Fourier equation of heat transfer, it can be seen that the heat conduction and the Ohm's law of the current passing through the conductor

Very similar, where the heat flow q is analogous to the current I, and the temperature drop ΔT is analogous to the voltage drop ΔV. So the thermal resistance can be defined as:

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; h</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;T</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Resistance in a circuit represents the resistance to the flow of current. Similarly, in heat conduction, thermal resistance represents the resistance to heat flow. For the same temperature difference, the greater the thermal resistance, the harder it is for heat to transfer. Thermal resistance is an important technical index and characteristic of electronic packaging, and it is also the most commonly used evaluation parameter in thermal analysis. The purpose of thermal design is to hope that the package structure can dissipate heat easily, and make its thermal resistance as small as possible.

At present, the main wafer-level bump processing is evaporated solder bump, electroplated solder bump and printed solder sticky bump. Solder bumps use thinner modified ball bonders and also use solder alloy material leads.

Under-bump metallurgy (UBM) deposition on the chip substrate area is an important factor for bump formation and flip-chip bonding. The under-bump metal layer has many functions. It must have a good enough ability to support the metal plating of the substrate. The metal plating is generally aluminum. It must be used as a diffusion stack during the soldering process to maintain good wettability of the soldering material. And prevent surface oxidation. Different bump metallizations are used for different bump processes.

The recommended maximum soldering temperature is 140°C without underfill and 150°C with underfill. The thermal resistance of each solder joint is 1000-1500°C/W. The thermal resistance from chip to substrate via flip-chip can be roughly calculated as the thermal resistance on each bump divided by the number of bumps on the chip. Additional bumps can increase cooling efficiency, and high thermal conductivity underfills can also be used. To work together to achieve efficient cooling.

Considering the symmetry of the structure and saving time, we take the 1/4 model for analysis. The model uses Solidworks software for solid modeling. Since the finite element software ANASYS Workbench has established a seamless interface with Solidworks, the Solidworks model is directly imported into ANSYS Workbench for analysis [4].

Since the whole model has a relatively regular geometric structure, hexahedron elements are used for mesh division. Consider the following principles when dividing the grid: 1. For the part of concern such as the chip, use a denser network when dividing the grid to ensure calculation accuracy; 2. For the part where the expected temperature gradient is large, such as the vicinity of the chip, use a denser network grid, and the parts with smaller temperature gradients, such as the package shell and PCB, use a sparser network. This not only ensures the calculation accuracy, but also does not cause the model scale to be too large and take up a lot of time. Figure 8 is the overall finite element mesh diagram of the FC-BGA model.

The innovation of the present invention proposes that according to the difference in the local heat of the chip, the corresponding distribution of the design bumps is different. Where the local heat of the chip is high, the corresponding bump distribution density is relatively large, and where the local heat of the chip is relatively low, the bumps The point distribution density is small, which makes the heat evenly transmitted to the substrate through the bumps and dissipated reasonably and quickly [5]. The choice of bump material and filler material is also important, and can have a great impact on the heat transfer and the corresponding density distribution requirements of the bumps.

Figure 9 is a schematic diagram of the location distribution of the key bumps. Through the simulation of the stable temperature field of the structure and the simulation of the transient temperature field, the bumps are evenly distributed first, and then through the simulation of the stable distribution of the heat of the bumps, it is found that The position of the key bump, that is, the position of the higher temperature bump. According to the different bump temperature, the bump position is classified, and then the bump distribution is adjusted, and the bump distribution density is appropriately increased at the original bump position with a higher temperature. Point C in the figure is a key point of high temperature. Therefore, it is necessary to increase C The distribution density of the bumps at the point makes the heat dissipated faster at the local position of the chip corresponding to the point C.

In addition, due to the different thermal expansion coefficients of the materials of the package, thermal stress and thermal strain will be caused after the temperature changes. FIG. 10 is a schematic diagram of thermal deformation of the package. Usually, the structure of the package is finalized after the solder balls are reflowed at 135°C, and when the temperature is cooled to 25°C at room temperature, the package deforms into a situation where the edges are concave downward and the middle is protruding. Therefore, we need to take this situation into consideration and adjust the bump density, that is, adjust the spacing between bumps.

Description of drawings

Fig. 1 is the photograph that adopts the graphic accelerator chip of FC-BGA package;

Figure 2 is a typical structural diagram of an FC-BGA package with a copper alloy heat dissipation cover on an organic material substrate;

Fig. 3 is the simulated schematic diagram of the heat dissipation of the FC-BGA package structure;

Figure 4 is a graph of thermal resistance and airflow velocity under different substrate layers and with or without external heat sinks;

Figure 5 is a graph showing the relationship between the junction temperature and the ambient temperature difference and the thermal conductivity of the substrate with or without an external heat sink;

Figure 6 shows the growth trend of the maximum heat flux of the chip;

Figure 7 is a schematic diagram of bumps in the FC-BGA package structure;

Figure 8 is the overall finite element grid diagram of the FC-BGA model;

Figure 9 is a schematic diagram of the position distribution of key bumps;

Figure 10 is a schematic diagram of thermal deformation of the package;

Detailed ways

The technical scheme of the present invention will be further described below in conjunction with the accompanying drawings.

According to the above invention principle, we simulate according to the model in Figure 8, we take 45mm*45mmFC-BGA (19.7*19.7mm chip size, sample size: 28 units) as an example, the data obtained from the experiment are shown in Table 1.

Change parameters (mm) Wafer maximum temperature (°C) FR4 circuit board temperature (℃) Total thermal resistance R(°C/W) Bump pitch 0.028 56.994 29.9784 45.5304 Bump pitch 0.024 56.746 29.980 46.0489 Bump pitch 0.02 56.273 29.9827 46.2812

Table 1 shows the changes in the maximum temperature of the chip/temperature of the FR4 circuit board/total thermal resistance R under different bump pitches

It can be obtained from the analysis of the data in the table that adjusting the bump spacing, that is, adjusting the density of the local bumps, can significantly improve the maximum temperature of the chip, the temperature of the FR4 circuit board, and the total thermal resistance value. When increasing the bump density , that is, reducing the pitch of the bumps can significantly reduce the maximum temperature of the chip, reduce the total thermal resistance, improve the heat transfer capability, and make the heat of the chip be transmitted through the bumps faster and more evenly. The invention avoids thermal failure of the chip caused by local overheating of the chip by considering local heat dissipation, and significantly improves the heat management of the FC-BGA packaging structure and the heat transmission of the chip.

This new method of improving heat transfer in FC-BGA packaging by adjusting the distribution of bumps can effectively solve the problem of local hot spots. To improve the cooling efficiency of thermoelectric materials, optimize the entire package structure and overall operation, this method is combined with the selection of bump materials, the selection of underfill materials, the selection of substrate materials, and the consideration of the number of substrate layers. Effectively improve the thermal management of the FC-BGA packaging structure.

The present invention uses 45mm*45mm FC-BGA (19.7*19.7mm chip size, sample size: 28 units) as an example to simulate and illustrate the situation of the present invention. There is no actual example operation, but the method of changing the bump spacing, In the packaging process, the operability is strong, the operation is simple, and through the consideration of the selection of materials, better results can be achieved.

The above content is a further detailed description of the present invention in conjunction with specific embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (6)

1. the heat dissipation new method that FC-BGA encapsulation salient point distributes, is characterized in that comprising: the heat dissipation problems of effectively improving hot localised points by the different distributions of salient point; By the substrate plating layer of metal of ubm layer UBM to chip; Distribute rationally and promptly by corresponding salient point heat is conducted, thereby the heat of reduction chip makes chip reach as early as possible heat balance, whole package system stationary field reaches stable state.

2. the method for claim 1, it is characterized in that, be connected by salient point between chip and substrate, heat dissipation situation to the encapsulation of FC-BGA structure is simulated, about 98.5% heat is by this paths of salient point of chip and substrate and centre, so the heat radiation of salient point accounts for dominating role.

3. as claim 1 and the described method of Fig. 9, it is characterized in that, carry out salient point position classification according to the difference of salient point temperature, and then the adjustment salient point distributes, the salient point location-appropriate higher in original temperature improves the salient point distribution density, find the high temperature key point, improve the salient point distribution density at this some place.

4. as claim 1 and the described method of Figure 10, it is characterized in that, because the thermal coefficient of expansion of each material of packaging body is different, after variations in temperature, can cause the thermal strain of thermal stress, cause the packaging body distortion, re-start adjustment to bump density.

5. AsMethod claimed in claim 1 is characterized in that, ubm layer (UBM) must possess enough good support substrate plating ability, is conducive to salient point and forms and flip chip bonding, and the coated metal of general chip substrate is aluminium.

6. AsMethod claimed in claim 1 is characterized in that, after salient point distributes and to complete, thereby rationally and promptly makes being transferred to substrate by salient point and dissipating away of heat balance.

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