CN1031376C - Electronic game device capable of producing pseudo-stereo sound - Google Patents

Abstract

In an electronic game device capable of producing pseudo-stereophonic sound, a plurality of sound generating circuits controlled by a microcomputer to generate audio signals are controlled, outputs of the sound generating circuits are sent to either or both of two independent channel outputs independently of each other, so that the pseudo-stereophonic sound produced can be listened to by a stereophonic headphone, and when the stereophonic headphone is not attached, a selecting circuit automatically mixes the two channel outputs to provide the internal speaker in a monophonic form. The microcomputer produces sounds and music based on the pitch, duration and score data structures stored in the cartridge, the score data structures specifying the pitch, duration and other characteristics in the form of address offsets.

Description

Electronic game device capable of producing pseudo-stereo sound

This invention relates to electronic gaming devices, and more particularly to microprocessor controlled electronic gaming devices having two-dimensional graphical displays. More particularly, the present invention relates to the generation of pseudo-stereo music and sound effects in such electronic game devices. More particularly, the present invention relates to pseudo-stereo sound generation for producing music, sound effects, and other sounds in gaming devices using external memory cartridges, such as electronic television gaming devices or portable handheld electronic liquid crystal display type gaming devices. Apparatus and methods.

Conventional electronic televisions and other gaming devices produce, for example, music, sounds, etc. based on digital data representing sounds stored in a memory device. However, in the past, the sound signal thus produced was mono rather than stereo for various reasons.

As we all know, "stereo" sound usually has two separate (but related) audio channels (eg "left" and "right" channels). Each audio channel includes independent audio (and other) signal processing circuitry. The signals produced by separate stereo audio channels are typically reproduced by several spatially separated audio transducers (eg "left" and "right" speaker or headphone transducers).

In the recording industry, it is common for different stereo channels to be recorded and/or mixed independently so that upon playback the audio signals present in the two channels are distinct but related. Audiences perceive sound quality as two-dimensional due to phase and other signal relationships between related sounds produced simultaneously (or nearly simultaneously) in different channels. Stereo produces a more pleasing listening experience, since the listener feels immersed in the envelope of sound radiating from multiple spatially separated sources. This effect is especially enhanced when listening to stereo sound through stereo headphones.

As is well known, using conventional computer technology, it is possible to synthesize stereophonic sound by generating sound sources for left and right channels respectively controlled by left and right channel data stored in digital memory. However, the memory required to produce this stereophonic sound is usually doubled compared to the occasion where only the monophonic effect is produced. Furthermore, separate sound synthesis circuits ("sound sources") must be provided for the left and right channels, thereby increasing the complexity and cost of the synthesis circuit structure.

A pseudo-stereo generator is disclosed in Japanese Utility Model Publication No. 66800/1983. This reference discloses the use of an AM broadcast receiver (tuner) to receive an AM broadcast signal and enhance the received AM signal (mono) to produce a pseudo-stereo effect. This document does not address the problem of creating stereo sound in gaming devices with limited memory resources.

The present invention provides a stereophonic generating apparatus and method for producing pseudo-stereophonic sound with inexpensive and relatively simple circuitry that substantially reduces memory requirements.

The present invention also provides a novel memory cartridge usable in a video game device with a pseudo-stereo sound generating circuit.

The present invention further provides a novel handheld video game device including a pseudo-stereo generator.

Another important superior feature provided by the present invention is that stereo sound effect can be produced through stereo earphones in the handheld game device.

According to one method of the present invention, a plurality of independent sound synthesis circuits are provided. Some sound synthesizing circuits can be used to generate a left channel output signal, while other sound synthesizing circuits can be used to generate a right channel output signal, and still other sound synthesizing circuits can be used to generate audio signals that are applied to both left and right audio output channels. However, in the preferred embodiment of the present invention, the sound synthesis circuit is not permanently assigned as an audio output channel. Instead, an audio switching circuit is provided at the output end of the sound synthesis circuit to selectively send the output signals of various synthesis circuits to the required left or right audio output channel. The state of the analog switch circuit can be changed under program control, thereby changing the audio output channel to which the signal generated by the specific sound synthesis circuit is directed.

For example, according to a feature of the present invention, a left channel audio signal bus and a right channel audio signal bus are provided. The left channel audio signal bus provides the left channel audio signal to a left channel audio signal amplifier and an associated sound transducer (eg, the left channel transducer of a stereo headset). Likewise, the right channel audio signal applies the right channel audio signal to a right channel audio amplifier and associated sound transducer (eg, the right channel transducer of the same stereo headphone). Also equipped with multiple sound synthesis circuits (sound sources). The sound sources in the preferred embodiment independently generate various audio signals (eg, pitch, sound effects, etc.) under program control. Each (any) output signal of the plurality of sound sources may be coupled to a left channel audio signal bus via a left channel analog switch and/or coupled to a right channel audio signal bus via a right channel analog switch. The state of the analog switch is controlled by program instructions so that it can be changed dynamically as required.

In this way, the output signal of a specific sound source can be added only to the left channel audio signal bus and only to the right channel audio signal bus by simply selecting the state of the analog switch connected to the output terminal of the specific sound source, Or add to the two buses of the left and right audio signals (and these states can be changed as required under program control). Audio signals may be routed to one, the other, or both audio output channels by simultaneously or selectively opening or closing left or right channel analog switches associated with particular sound sources.

Since it is possible according to the invention to select the channel to which the output signal of a particular sound source is added, there is no need to store completely different sets of sound generation data (left and right channels) corresponding to two stereophonic music programs. That is, it is only necessary to store different sound generation data for controlling a plurality of sound generation sources to be activated within a certain time. The additional data used to selectively add the output signals of various sound sources to the audio channel requires only a small amount of additional storage space, and pseudo stereophonic sound can be provided with only a small amount of additional storage. Since it is possible to select which channel a particular sound source signal is to be applied to, there is essentially no increase in memory requirements (this is very different from storing the left and right channel signals separately in memory, which usually requires a single twice the amount of storage required for the audio information of the channel). Furthermore, the present invention provides a more versatile and less complex circuit configuration, making it particularly suitable for producing sound effects in miniaturized portable video game devices.

In the above-mentioned video game device, the sound source signal generated by the sound source signal generating means is then selectively output to the first and second (for example, left and right) sound sources through the switching action performed by the analog switch means. signal channel to produce pseudo-stereo sound.

The present invention also provides a memory cartridge removably engageable with a video game apparatus for generating stereo control signals. The video game apparatus includes sound source signal generating means for generating sound signals in accordance with data supplied from the memory cartridge. The switch means can connect the output of the sound signal generating means to one or both of the first and second sound output channels and selectively add the output of the sound source signal generating means to the first and/or second sound signal output channel. For music production, the memory cartridge preferably stores data representing the duration (length of time) of a note or rest, data associated with a pitch, and a description of the direction in which the sound produced at the specified pitch and duration is directed. Which audio output channel's "direction" data.

The memory cartridge stores a sequence of data sets corresponding to the sequence of the musical or acoustic signal (i.e., notes and rests), and, in the preferred embodiment, in the order of the sequence (access to the different data sets in the sequence in time separate case) to access data sets for describing sequences of music or sound signals. In a preferred embodiment, the memory cartridge stores multiple data sets corresponding to a given moment in the musical sound signal sequence, thus providing simultaneous control of multiple sound sources.

The memory cartridge in the preferred embodiment also stores program control instructions for separately reading out sound data representing predetermined timings, thereby providing length (duration) related data, pitch related data, and left/right channel specifiers ("Direction") The mechanism by which data is sent to the video game device according to program control instructions read from the memory cartridge.

The memory cartridge in the preferred embodiment of the present invention preferably stores multiple data structures representing different aspects of the sound to be produced. In particular, the cartridge preferably stores a score data table for representing information typically represented by sheet music (eg, pitch and duration of notes in a sequence of notes and rests, and rest times). Such a score data table preferably in turn provides offset addresses to the duration data structure, maps the durations of the different notes and rests stored in the score table to timing control signals for appropriate sound generation circuits, and provides frequency data The offset address of the structure maps the different pitches to the appropriate pitch control signal for the sound generation circuit.

Along with the carrying out of the stored computer program in this memory card box, read out sound length relevant data, pitch relevant data and the data of explanation left/right channel direction (these timings are determined by program flow in addition) of). The pitch of the generated sound is determined according to the pitch-related data, and the time period (ie, sound length or duration) for which the pitch is maintained is determined according to the sound length (duration) related data. The output multiplexing operation as described above is performed according to the data specifying the left/right channel direction to obtain the desired right-channel sound output or left-channel sound output. In this way, the sequence of notes stored in the score sheet can be produced in pseudo-stereo form. It is possible to generate Or form a pseudo-stereo like music or sound.

According to another feature of the present invention, the stereo/mono conversion circuit is connected to a stereo source from which left and right channel sound signals are independently output. The stereo/mono conversion circuit preferably includes a headphone jack which accepts a universal stereo audio plug. The headphone jack includes at least one switch contact and left and right channel audio contacts. The left channel audio contact directs the left channel audio signal to the earphone left channel audio transducer, while the right channel audio contact similarly directs the right channel audio signal to the earphone right channel audio transducer. In addition, a mono audio transducer (eg, a speaker in a video game console) is also provided.

When no earphone plug is inserted into the earphone jack, the switch contacts automatically de-energize the independent left and right channel audio signal paths connected to the left and right channel output terminals of the earphone jack and automatically activate the left and right channel audio signals. The signals are combined together into a control signal for a combining ("mixing") circuit of the mono signal. The combining circuit applies the combined mono signal to the internal speaker of the video game unit. On the other hand, the insertion of an earphone plug in an earphone jack changes the state of the control signal generated by the opening and closing contacts of the earphone jack, i.e. deenergizes the combined circuit (and thus automatically deenergizes the internal speaker) instead of With completely independent signal paths for left and right channels to the left and right channel contacts of the headphone socket.

In this way, when the earphone plug is not inserted into the earphone jack, the synthesized monaural sound signal is supplied to the internal speaker. On the other hand, when the headphone plug is inserted into the headphone socket, instead of disabling the signal paths of the left and right channels, they are respectively output to the contacts of the left and right channels of the headphone socket, and thus stereo output to the plugged-in headphones Socket for stereo headphones. In this way, the user can easily play the video game device as a completely separate unit and listen to the mono sound produced by the internal speaker. On the other hand, if the gaming machine user wants to experience the sound enhancement effect provided by the above-mentioned pseudo-stereo sound generation capability, he only needs to plug the plug of the stereo earphone into the earphone jack and put the earphone on his head.

Thus, even though the sound generating data stored in the data cartridge controls the sound generating circuit to generate pseudo stereo, this feature of the present invention provides a novel stereo/mono conversion circuit capable of selecting between stereo and mono. This stereo/mono selection circuit is very effective for producing sound in a handheld video game machine.

These and other objects, features, aspects and advantages of the present invention will become more apparent and understandable from the following detailed description of the presently preferred embodiment of the present invention in conjunction with the accompanying drawings, in which:

1 is a side perspective view of an exemplary handheld liquid crystal display type video game device that may advantageously utilize the present invention;

Fig. 2 is a functional block diagram of the electronic circuit included in the game device of Fig. 1;

Figure 2A is a more detailed schematic diagram of the microcomputer architecture shown in Figure 2;

3A-3D are schematic diagrams of exemplary maps of the CPU address space shown in FIG. 2;

Figure 4 is a functional block diagram of the exemplary sound generator shown in Figure 2;

Fig. 4A is the exemplary content in register NR50, NR51 and NR52 shown in Fig. 4;

Figure 5 is a more detailed circuit diagram of an illustrative example of the sound generating circuit shown in Figure 4;

5A-5D are schematic diagrams of exemplary contents of the sound control register in the sound generating circuit shown in FIG. 4;

Figure 6 is a graphical illustration of an exemplary musical notation, also showing some control parameters for controlling the various sound generating circuits shown in Figure 4;

Figures 7A-7B are collectively a schematic flow diagram of exemplary program control steps executed by the microcomputer of Figure 2 in a preferred embodiment for producing the music represented by the musical score of Figure 6;

Fig. 8 is the schematic circuit diagram of the exemplary stereo/mono selection circuit of structure shown in Fig. 4; And

9A-9D are schematic diagrams of exemplary contents of the memory cartridge shown in FIGS. 1 and 2 .

The complete electronic game device provided by the presently preferred exemplary embodiment of the present invention will first be described. A more detailed description of the architecture of the microcomputer in the preferred embodiment is given next, including an exemplary architecture of the microcomputer and an exemplary memory organization of the microcomputer. Then, a detailed description of the sound generator of the preferred embodiment is given. With respect to the sound generator, the general structure and operation of the preferred embodiment sound generator will first be described, including the better use of multiple independent sound generating circuits in cooperation with each other to produce pseudo-stereo sound. Next, a detailed description of an exemplary structure and operation of multiple independent sound generating circuits is given. A description follows of exemplary program control steps executable and associated exemplary data structures accessible by the microcomputer of the preferred embodiment to generate a line of music. Finally, a description is given of an exemplary stereo/mono sound conversion circuit.

FIG. 1 is an elevational view showing a casing of an exemplary handheld liquid crystal electronic game machine according to the presently preferred exemplary embodiment of the present invention. The handheld liquid crystal game machine (hereinafter "game machine") 10 includes a case 12 equipped with a liquid crystal display (LDC) screen 14 comprising dots arranged in a dot matrix on its front or upper surface. Display segment.

An insertion port 68 is formed on the back or lower surface of the case 12 at a portion opposite to the LCD panel 14 . An external ROM cartridge 16 can be plugged into the insertion opening 68 . More specifically, the 32-pin connector 20 is disposed in the insertion opening 68 . By inserting the external ROM cartridge 16 into the insertion port 68, a connector (not shown) formed on the edge of the printed circuit board of the external ROM cartridge 16 is electrically and mechanically connected to the connector 20. Thus, the external ROM cartridge 16 is attachable/detachable attachable to the game machine 10 .

As described above, the external ROM cartridge 16 is a "memory cartridge", and the game device 10 into which the memory cartridge is inserted is a "master device". The combination of the cartridge 16 and the main device 10 constitutes an electronic game device. Different memory cartridges 16 can be inserted into the slot 68 to provide different program control instructions, thereby changing the game being played.

An external ROM 16a is included in the external ROM cartridge 16 (see FIG. 9A). A game program is stored in the program control command area 310 of the external ROM 16a. In addition, as is well known, the cartridge may also include additional memory devices (eg, expansion RAM, memory bank controller (MBC), etc.). When the external ROM cartridge 16 is inserted into the game machine 10, the game program will be executed, so that images will be displayed on the LCD screen 14, and game music will be produced by the loudspeaker 11 or by the earphones connected with the socket 64.

Also dispose 6 pin connectors 65 in box 12, utilize this connector to be able to connect this game machine with other machines by suitable cable, make when external card box comprises multi-player game program, just can carry out the competition among many players.

In the preferred embodiment, the user input device including the cross key switch 18 is arranged on the front of the box 12 or on the left side below the upper LCD screen 14, as shown in FIG. 1 . The cross key switch 18 has four direction designating parts or contacts, and pressing any one of them, for example, may cause the characters displayed on the display 14 to move up, down, left, or right. In addition, as shown in FIG. 1 , two push button switches 70 a and 70 b are disposed on the front of the box 12 or on the right side below the upper LCD screen 14 . These two buttons 70a and 70b can be manipulated when it is necessary to control the game characters displayed on the LCD screen 14 to perform various predetermined functions. For example, when the button switch 70a is pressed, the displayed character may jump, or when the button switch 70b is pressed, the character may appear to throw a stone, or throw a ball, or throw various other objects. The cross key switch 18 is arranged so that it can be operated by the thumb of the left hand, the right hand and the right hand cooperate to hold the box 12 in the hand, and the push button switches 70a and 70b are arranged to be operated by the thumb of the right hand.

Also, an activation switch 72 and a selection switch 74 are mounted on the front or top of the box 12 of the game machine 10 . The start switch 72 and the selection switch 74 as seen from FIG. 1 are installed in an area 78 below the cross key switch 18 and the push button switches 70a and 70b. These switches 72 and 74 are installed collectively so that they can be operated with the thumbs of either of the left and right hands (while holding the case 12 of the game machine 10 with the left and right hands). In other words, switches 72 and 74 can be operated without appreciable changes in hand position. For example, the operation mode of the displayed game is selected by using the selection switch 74 by using the menu screen. About this. A selection switch 74 may be used to select one of several game play levels. In addition, a function of selecting "weapons" available to game characters may be assigned to the selector switch 74 .

The start switch 72 is operated to start the selected game. Therefore, it is generally not necessary to operate the activation switch 72 and the selection switch 74 during the game. However, since a pause (PAUSE) function is also assigned to the start switch 72, the start switch 72 can be pressed when a temporary stop of the game is required. To start the game after such a pause, the start switch 72 can be pressed again. Furthermore, it is possible to program enable switch 72 and select switch 74 to have many other functions, so that the functions assigned to these switches can be dynamically changed during game play.

In addition, an on/off switch 1, a battery level lamp 13, a contrast adjustment 50 and a volume adjustment 66 are also installed on the box 12.

The core of the game device 10 is the microcomputer 22 shown in FIG. 2 (detailed schematic diagram of the electronic circuit in the game device). Microcomputer 10 includes CPU 24, which may be implemented by way of example only of a commercially available microprocessor such as a VLSI integrated circuit microprocessor chip of the Z80 type. The CPU 24 passes through the timing unit 25a, control bus 26a, address buffer 25b and address bus 26b, data buffer 25c and data bus 26c (these buses and related devices also connect the CPU to the working RAM or temporary storage 23) and the 32-pin cartridge Connector 20 is connected (and thereby connects to memory and other components within cartridge 16). When the external ROM cartridge 16 is engaged with the game machine 10, the CPU 24 is integrated and cooperates with the external ROM cartridge 16.

Referring now more specifically to FIG. 2A, CPU 24 cooperates with address decoder 33 and memory select (bank switch) circuitry 32 in the preferred embodiment to gate various devices (e.g., cartridge 16) within the address space of the CPU. In the internal ROM30, internal RAM28, and external ROM16a). In addition, address decoder 33 can be used to allow CPU 24 to select various external control registers contained in other blocks shown in FIG. 2 (for example, the control register in sound generator 58) or can be implemented by other similar address decoders The function.

As shown in FIG. 2A, CPU 24 preferably includes internal 8-bit general and special purpose registers, a 16-bit program counter PC and a 16-bit stack pointer SP. Register A can be used as an accumulator and another register F can be used as a flag register. The CPU 24 preferably has an associated instruction set that allows for the inclusion of: various 8-bit and 16-bit transfer instructions between registers or pairs of registers; various 8-bit and/or 16-bit arithmetic instructions (e.g., ADD, SUB, AND/OR, INC, DEC, etc.), various shift/circle operation instructions (such as rotating the specified register content to the left/right), various bit control operation instructions (for example, in the Set the specified bit in the specified register), conditional and unconditional transfer instructions, subroutine call and return operations, and various program control operations (such as start, stop, empty operation, etc.) well known.

In the preferred embodiment, CPU 24 performs operations under the control of program control instructions stored in memory cartridge 16 to provide a display of game play on display 14 in response to user input signals formed by the user via user input device 18. . In addition, the CPU controls the sound generator 58 to generate music and/or sounds corresponding to the game being played under the control of the same program control instructions stored in the cartridge 16 .

Referring again to FIG. 2, clock pulses are supplied to the CPU 24 by an oscillating circuit 24b responsive to a quartz crystal element 24a. Clock divider 24c generates one or more clock rates and is programmable by CPU 24 to divide the clock generated by oscillator circuit 24b at the desired rate.

A programmable external hardware timing circuit 24d may also be provided to enable the CPU to determine when the current desired time interval has elapsed. In the preferred embodiment, CPU 24 may incorporate timer circuit 24d with a value representing the length of the time interval and start the timer. The timer circuit 24d can automatically measure the time interval and when the time interval elapses, the timer circuit can generate an interrupt signal and add the interrupt signal to the CPU 24 (e.g., through the interrupt controller 24i) to alert the CPU that the time interval has elapsed. past. In this way, the CPU has timing capabilities without using a software timing loop (which may consume CPU processing time and resources). If desired, the timing circuit 24d can also be used for timing the notes produced by the sound generator 58 (to be described shortly).

In the preferred embodiment, CPU 24 outputs display data through line buffer 36 to LCD controller 38 under the control of DMA controller 34 . LCD controller 38 is connected to display RAM 42 through LCD display RAM interface 40 and control address and data bus.

LCD controller 38 operates under the control of CPU 24 through various addressable control/status registers located in the CPU address space generally shown in Figures 3A-3D. These registers may include, for example, the following registers: LCD display registers, LCD controller status registers, horizontal and vertical scroll registers, LCDC (LCD controller) vertical row identification registers, and moving objects and background panels (e.g., 2-bit identifiable One of the shades of four tone colors) data register. The LCD display registers control the nature of the display, while the status registers indicate the current state of the LCD controller. By changing the data of the horizontal and vertical roll-up registers, the data corresponding to each point of the background display data is valid. The vertical row identification register indicates and controls the vertical row on which the data currently being transferred by the display driver will be displayed. The X and Y window position registers control the portion or window of the LCD display area in which OBJ (movie) characters and BG (background) character data are presented.

The LCD controller 38 converts display-related data output from the CPU 24 into LCD drive signals output from the display RAM 42 . More specifically, the display data from the CPU 24 specifies the addresses of the character RAM and VRAM (image RAM), so that character (or object) signals and background signals are output from the character RAM and VRAM. The corresponding LCD drive signals are synthesized by the LCD controller 38 .

The LCD drive signal is applied to LCD common driver 46 and LCD segment driver 48 through LCD drive signal buffer 44 . Therefore, by means of the LCD common driver 46 and the LCD segment driver 48, graphics can be displayed on the LCD panel 14 in accordance with display related data from the CPU 24. For example, an LCD panel may define a matrix of 144 x 160 pixels or dots, each pixel or dot having a corresponding unique "crossed" common electrode/segment electrode combination. The LCD common driver 46 drives the rows connected to the common electrodes, for example, this driver can be a Sharp company LH5076F integrated circuit. LCD segment driver 48 may be, for example, an integrated circuit of the type LH5077F from Sharp Corporation. These display drivers receive data from LCD drive signal buffer 44 which in turn receives data from CPU 24 indirectly through display RAM 42 , LCDRAM interface 40 and LCD controller 38 .

In addition, intensity level control 50 is coupled to LCD buffer amplifier 52 to allow adjustment of the intensity of the display produced by LCD panel 14 .

Referring again to FIG. 2A , a reset signal from reset circuit 55 is applied to CPU 24 and memory selection circuit 32 . When the power switch of game machine 10 was turned on (see FIG. 1), a reset signal was output, so CPU24 and memory selection circuit 32 were reset initially. Then, a read signal RD and a write signal WR are output from the CPU 24 , and these signals are input to the external ROM cartridge 16 , internal RAM 28 , internal ROM 30 , and memory selection circuit 32 as appropriate. In addition, the address decoding signal is added to the memory selection circuit 32 through the address decoder 33.

Referring now to FIGS. 3A-3B , an exemplary CPU address space, the nature of data stored in internal memory 30 and external memory cartridge 16 is described in detail. As shown in FIGS. 3A and 3B, the internal ROM 30 has a first storage area designated by addresses "0000H-00FFH", corresponding to a first relatively small address space. "H" indicates that these addresses are represented by hexadecimal numbers. A first character for display, such as a logo "Nintendo", and an external memory reliability determination program are stored in the first storage area.

The external ROM cartridge 16 includes an external ROM 16a. 3C and 3D, the memory space of the external ROM 16a is divided into the second storage area specified by the address "0000H-0FFH" (it also corresponds to the address defined by the above-mentioned first address space), and The third storage area (second address space) designated by "0100H-7FFFH". Second character data (which is the same as the first character data) is stored in an area starting from address "0100H" of the third storage area in the approved external memory cartridge. Game programs are stored in the remaining area of the third storage area. Preferably, auxiliary data such as a code identifying a manufacturer, game name, cartridge type, memory capacity, etc. are stored in several bytes after the second character data storage area. In addition, when the storage amount required by the game program is large, the second storage area ("0000H-00FFH") of the external ROM 16a can be used to store such program data for the game.

The sound generator 58 shown in FIG. 2 can also be controlled by the CPU 24 according to program control instructions stored in the cartridge 16. In the preferred embodiment, the sound generator 58 includes a plurality of independent sound generating circuits which can be controlled individually or in combination by the CPU to generate multiple sounds simultaneously. These registers reside in the section of "various registers" between units FF00 (hexadecimal) and FF80 (hexadecimal) in the storage space shown in FIG. 3B. The CPU 24 controls the sound generator 58 by writing appropriate control data into 8-bit registers located physically within the sound generator, but directly addressable by the CPU, within the CPU address space.

In a preferred embodiment, the register interface of the sound generator occupies addresses FF10-FF26 in the CPU address space, and the specific occupancy is as follows:

Register NR10-NR15 (the control first sound generation circuit is located at address FF10-FF14;

Register NR21-NR24 (controlling the second sound generating circuit) is located at address FF16-FF19;

Registers NR30-NR34 (controlling the third sound generating circuit) are located at addresses FF1A-FF1E;

Registers NR41-NR44 (controlling the fourth sound generation circuit) are located at addresses FF20-FF23; and

Registers NR50-NR52 (which provide overall sound control for the output of each sound generating circuit) are located at addresses FF24-FF26.

Some registers mentioned above are writable only and others are read/write. CPU 24 can control various parameters of sound generation (for example, frequency range parameters of a particular sound generating circuit, waveform duty cycle, sound duration, etc.) by directly writing control data into appropriate sound control registers (described briefly below). time, envelope characteristics, sound frequency, polynomial count parameters of a particular sound generating circuit, assignment of a particular sound to a particular output channel, and sound output level).

FIG. 4 is a more detailed schematic diagram of the sound generator block 58 shown in FIG. 2 . The sound generator block 58 in the preferred embodiment includes: a plurality of sound generator circuits 541-544, an analog multiplexer block 200, left and right solid state volume control blocks 72L, 72R, left and right channel Audio amplifiers 60L, 60R and stereo/mono selection circuit 202 .

In the preferred embodiment, sound generator circuits 541-544 each independently generate audio signals under the control of the contents of control registers NR10-NR44 within the address space of CPU 24 as described above. Analog multiplexer 200 is controlled by registers NR50-NR52 in the address space of CPU 24 to route the output signal of each sound generator circuit 541-544 to one or both of left channel volume control 72L and right channel volume control 72R. By. As will be described in more detail shortly, the analog multiplexer 200 provides independent multiplex control of the output of each sound generator circuit 541-544 under program control. As an example, the output of one sound generating circuit may be routed to left channel volume control 72L and the output of another sound generating circuit may be routed to right channel volume control 72R, while the output of yet another sound generating circuit may be routed to The volume controls for the left and right channels, and the output of another sound generating circuit may not gate either of the two volume controls (all these assignments can be changed under program control).

The output signals of volume controls 72L, 72R are amplified by left channel audio amplifier 60L and right channel audio amplifier 60R, respectively. The output of audio amplifier 60 is then sequentially applied to stereo/mono selection circuit 202 for use with internal mono speaker 120 or with optional external stereo headphones 64 via headphone socket 122 .

The analog multiplexer 200 receives respective output signals (ie, sound source signals) of the sound generating circuits 541-544. Analog multiplexer 200 includes a pair of analog switches for respective sound generating circuits 541-544. For example, the analog switches 681L, 681R correspond to the sound generating circuit 541; the analog switches 682L, 682R correspond to the sound generating circuit 542; the analog switches 683L, 683R correspond to the sound generating circuit 543; The output of one analog switch in each pair (eg, analog switches 681L, 682L, 683L, 684L) is typically connected to the left audio bus 300 . The left audio bus 300 is in turn connected to the input of the volume control block 72L. Similarly, the output of the other analog switch in each pair (e.g., analog switches 681R, 682R, 683R, 684R) is then connected to the right audio bus 302 (i.e., such that all of these mentioned analog switches have outputs with public connection). The right audio bus 302 is in turn connected to the output of the right channel volume control block 72R. Respective outputs (ie, two sound signals) of solid volume control blocks 72L, 72R are amplified by left and right channel amplifiers 60L and 60R respectively and thereafter output as first and second sound outputs S01, S02. In the illustrated embodiment, output S01 from amplifier 60L may be used as the left channel sound signal, while output S02 from amplifier 60R may be used as the right channel sound signal.

FIG. 4A is a functional block diagram illustrating exemplary registers NR50 , NR51 , and NR52 shown in FIG. 4 . Registers NR50-NR52 are used in the preferred embodiment to control certain operating parameters of sound generating circuits 541-544, analog multiplexer 200 and volume controls 72L, 72R. Although multiple registers NR50A-NR50C are depicted in FIG. 4, NR50A-NR50C actually comprise a single multi-bit register (e.g., 8 bits) as shown in FIG. 4A. Similarly, multiple registers shown in FIG. 4 NR52A-NR52B actually comprise a single multi-bit data register NR52 as shown in FIG. 4A.

Registers NR52A-NR52B (consisting in the preferred embodiment of a single 8-bit register operatively coupled to CPU 24) are used to control the enabling/disabling of sound generating circuits 541-544. As shown in Figure 4A, the most significant bit D7 of register NR52 can be used to enable/disable all sound generating circuits 541-544. If the most significant bit D7 of register NR52 is set to a logic level 1, then all sound generating circuits 541-544 become operational, similarly, if a logic level "zero" value is written to the most significant bit D7 of register NR52 , all the sound generating circuits 541-544 are prohibited. The lowest 4 bits D0-D3 of the register NR52 are used as the connection flags of the sound generating circuits of the respective sound generating circuits 541-544, and can be individually enabled according to the logic level values written in these 4 bits D0-D3 Or prohibit each sound generating circuit.

In the preferred embodiment, the states of the analog switches 681L-684L, 681R-684R are controlled by register NR51, a detailed schematic diagram of which is also shown in FIG. 4A. In the preferred embodiment, register NR51 is also 8 bits wide. The lowest 4 bits D0-D3 of the register NR51 correspond to the analog switches 681L-684L respectively and control these analog switches to turn on or off (that is, pass or not pass) the outputs of the sound generating circuits 541-544 corresponding to the left audio bus 300 respectively. Similarly, the highest 4 bits D4-D7 of the register NR51 respectively control the analog switches 681R-684R to be turned on or off (so that the outputs of the sound generating circuits 541-544 are sent or not sent to the right audio bus 302 respectively).

For example, assume a logic level zero value is written to bits D0 and D4 of register NR51 (eg, which correspond to analog switches 681L and 681R, respectively). A logic level zero value stored in the lowest bit D0 controls the analog switch 681L to close - thereby effectively disconnecting the output of the sound generation circuit 541 from the input of the left channel solid state volume control block 72L. Likewise, the logic level zero stored in bit D4 of register NR51 effectively controls analog switch 681R to disconnect sound generation circuit 541 from the input of right channel solid state volume control block 72R. Therefore, as long as the value of these two "zero" bits is stored in register NR51, the output of the sound generating circuit 541 is sent to neither the left channel output S01 nor the right channel output S02. Write logic level 1 to bit D0 of register NR51 to control analog switch 681L to send the output of sound generating circuit 541 to left channel output S01; write logic level 1 to bit D4 of register NR51 to control analog switch 681R to generate sound The output of the circuit 541 is sent to the right channel output S02; the value of logic level 1 is written into bits D0 and D4, then the analog switches 681L and 681R are controlled to send the output of the sound generating circuit 541 to the left and right sound signal output terminals S01 respectively , S02.

Briefly, register NR51 in the preferred embodiment stores two bits corresponding to each of the sound generating circuits 541-544 which control an analog switch 681 connected to the sound generating circuits, optionally The output of the sound generating circuit is sent or not sent to the output terminals S01 and S02. If both bits are logic level zero, then the output of the sound generating circuit is not sent to either of the sound output terminals S01, S02. If one of them is logic level 1 and the other one is logic level zero, then the output of the sound generating circuit is only sent to one of the sound output terminals S01 and S02 (which one of the sound signal output terminals S01 and S02 receives The output of the sound generation circuit depends on which bit is logic level 1). On the other hand, if both bits are set to logic level 1, the sound signal output terminals S01, S02 both receive output signals from corresponding sound generating circuits.

In a preferred embodiment (as shown in FIG. 4A), registers NR50A-NA50C shown in FIG. 4 actually comprise a single 8-bit register NR50. The two bits D3, D7 of the register NR50 are used to switch on and off another set of analog switches 70L, 70R whose inputs are connected to the signal VIN obtained from an external sound source. For example, in the preferred embodiment, additional sound source signals may be provided by sound generating sources other than sound generating circuits 541-544. The externally provided sound source signal is input as signal VIN, which can be selectively sent to left audio bus 300 and right audio bus 302 by analog switches 70L, 70R, respectively. The on/off states of the analog switches 70L and 70R are respectively selected by bits D3 and D7 of the register NR50 in sequence.

The remaining six bits of register NR50 in the preferred embodiment are used to control the degree of amplification/attenuation applied by the solid state volume controls 72L, 72R. Thus, in the exemplary embodiment, register NR50B shown in FIG. 4 contains the least significant bits D0-D2 of register NR50, and register NR50C shown in FIG. 4 includes bits D4-D6 of register NR50 shown in FIG. 4A. By setting binary values "000"-"111" to these three-bit fields, it is possible to control the output levels of the solid-state volume control blocks 70L, 72R in 8 steps from minimum to maximum. Thus, for example, writing the value "000" to the least significant bits D0-D2 of register NR50 in the preferred embodiment controls the solid-state control block 72L to provide a level of minimum magnitude to the input of the left channel amplifier 60L (which, if desired, may be zero magnitude). Similarly, if the value "111" is written to register NR50 bits D4-D6, then the right channel solid-state volume control block 72R is controlled so that the enhancement degree of the left channel solid-state volume control block signal supplied by the right channel audio bus 302 is the minimum, thereby providing The output of the maximum (loudest) signal level of the right channel sound signal output terminal S02.

Referring now to FIGS. 4 and 6 together, as an example, the sound generation circuit 541 may be used as a melody source ("Sound 1") to provide the first verse or first line of the exemplary musical piece shown in FIG. The remaining sound generation circuits 542-544 can be used to produce the rhythm sounds of the lower three music bars shown in FIG. 6 . Of course, the sound generating circuits 541-544 may be used in any desired combination to generate multiple melodies (ie, counterpoint), melodies and harmonies together, combinations of music and sound effects, and the like.

In the musical notation shown in FIG. 6, the musical line marked S01 corresponds to the sound appearing on the left channel, and the musical line marked S02 corresponds to the sound appearing on the right channel. Fig. 6 shows a standard musical notation with notes and rests described in a conventional manner. The 4-bar music shown is used as an example (although it should be understood that the system described herein can play any length of music required, limited only by memory capacity).

As for the 4-bar music (“sound 1”) shown in the first section of FIG. 6, the analog switches 681L and 681R are controlled to be connected during all 4 bars; so that the melody output signal generated by the sound generating circuit 541 is output during all 4 bars. to two amplifiers 60L, 60R. Thus, during all 4 bars, the data value "1" will be written to bits D0 and D4 of register NR51.

Instead, the output of the sound generation circuit 542 alternates between left and right channels S01, S02, as shown in the section labeled "Sound 2" in FIG. Like this, the output of sound generation circuit 542 is provided to sound output end S01 instead of sound output end S02 during the 1st bar; Provided to the sound output S02 instead of the sound output S01, during the 4th bar to both outputs S01, S02. Therefore, in subsection 1, the CPU writes the data value "1" into bit D1 of register NR51 and writes the value "0" into bit D5 of register NR51. In the second subsection, write the value "1" into the bit D1 and bit D5 of the register NR51, so that the analog is turned on and both 682L and 682R are turned on and the output of the sound generating circuit 542 is sent to the two output channels S01, S02. During bar 3, contrary to bar 1, "0" is written into register NR51 bit D1 and "1" is written into register NR51 bit D5, analog switch 682L is turned off and analog switch 682K is turned on (so that the sound The output of generating circuit 542 is supplied to output channel S02 instead of output channel S01).

Likewise, the line "Sound 3" of the musical score shown in FIG. 6 indicates that the output of the sound generating circuit 543 alternates between channels S01 and S02. That is, during the first bar, analog switch 683L is turned on (by writing a logic level "1" to register NR51 bit D2) and analog switch 683R is turned off (by writing a value of logic level "0" to register NR51 bit D2). D6). Therefore, in the first section, the output of the sound generating circuit 543 is applied to the sound output channel S01 instead of the sound output channel S02. But during the second subsection, on the contrary, the values "0" and "1" are respectively written into bits D2 and D6 of register NR51 to close the analog switch 683L and turn on the analog switch 683R. Therefore, only the The output is provided to the sound output channel S02 but not to the sound output channel S01.

In a similar way, by writing the values "1" and "0" to bits D3, D7 of register NR51 during the first bar, followed by writing the values "0" and "1" respectively to bits of register NR51 during the second bar D3, D7, and writing values "1" and "0" to bits D3, D7, etc. during bar 3, thereby gating the output of the sound generating circuit 54 as shown in the lowermost row of music in FIG.

Clearly, registers NR50-NR52 are normally written in parallel so that, for example, all bits D0-D7 of register NR51 are normally rewritten each time any channel assignment bits will be changed.

Like this, the melody sound produced by the sound generating circuit 541 according to the exemplary music shown in FIG. 6 and the rhythm sound produced by the sound generating circuits 542-544 according to the exemplary music are selectively connected and Disconnected, the four source signals are appropriately mixed by the left and right audio buses 300, 302 and provided to the solid state volume controls 72L, 72R, respectively. The output levels of these mixed signals are independently controlled by the solid-state volume control blocks 72L, 72R according to the content of register NR50 bits D0-D2, D4-D6 so that the separate sound output signals S01 and S02 of the left and right audio channels (where combined or synthesized melodic and rhythmic sounds) can be output from the amplifiers 60L, 60R. By varying the amount of amplification in one volume control block 72 relative to the amount of amplification in the other volume control block, it is possible to change the spatial relationship perceived by the wearer of the headset (64) (so that the sound source position of the head).

FIG. 5 is a detailed block diagram of an exemplary structure of exemplary sound generating circuits 541-544. Although only one sound generating circuit is shown in Fig. 5, in terms of structure and operation, the four sound generating circuits 541-544 can be similar to each other, and in any case, the description of one of the sound generating circuits is useful to the field For a general skilled person, it is sufficient to provide details about all 4 circuits. Therefore, this article only needs to describe in detail one of the four sound generation circuits. In the preferred embodiment, the sound generating circuits 541-544 are not actually identical to one another, as some of them include enhanced capabilities for producing various sound effects. For example, sound generating circuit 541 may include a sweeping oscillator, sound generating circuit 543 may not include a duty cycle control, and sound generating circuit 544 may include a polynomial counting clock type frequency selection circuit, all of which are well known to those skilled in the art. .

Referring now to FIG. 5, the sound generating circuit 542 includes various counters, dividers and other components controlled by control registers NR21-NR24. Briefly, elements 74-94 provide a clock signal for enabling/disabling the conversion process by D/A converter 96 of the contents of envelope counter 102 into an audio output signal. Thus, elements 74-94 control the timing parameters associated with the audio output signal, envelope counter 102, while associated elements 98-106 control the amplitude of the audio output signal. As will be explained, the decoder 108 is used to reset the sound generation circuit 542 .

A reference clock signal of frequency f (which in the preferred embodiment is preferably provided by controlled crystal oscillator 24a and associated components shown in FIG. 2) is provided to the time base of sound generation circuit 542 shown in FIG. For example, the clock frequency signal may be 4.194,304 MHz in the preferred embodiment. In addition, an additional fixed-frequency clock signal (eg, having frequencies of 64 Hz and 256 Hz) obtained by dividing the clock frequency f may also be supplied to the sound generation circuit 542 , for example.

In the preferred embodiment, the reference clock signal f is applied to the input of divide-by-4 circuit 74 (eg, may comprise a pair of flip-flops forming a 2-bit counter). Divide-by-four circuit 74 divides clock frequency f by four and applies this divided frequency signal to an input of AND gate 76 in a well known manner. The other input of AND gate 76 is connected to the Q output of flip-flop 80 . In the preferred embodiment, flip-flop 80 is used to enable and disable sound generating circuit 542 by effectively gating (via AND gate 76) the divided clock frequency f to the input of frequency counter 82. The flip-flop 80 is set according to the value of the most significant bit D7 of the register NR24 (see Fig. 5b). In this way, when a logic level "1" is written into the highest bit D7 of the register NR24, the flip-flop 80 is set, thereby making the "AND" gate conduct, so that the divided clock frequency signal output from the divider 74 is passed. To the clock input of the frequency counter 82. In the preferred embodiment, flip-flop 80 is reset in response to the output of decoder 108, as will be described.

In the preferred embodiment, frequency counter 82 controls the frequency (pitch) of the audio output signal to be generated. In the preferred embodiment, frequency counter 82 comprises a programmable frequency divider of conventional construction. The frequency division ratio performed by frequency counter 82 is determined by frequency data contained in registers NR23 and NR24. In particular, the lowest 3 bits D0-D3 of register NR24 contain the three highest bits of the 11-bit frequency data value, while all 8 bits D0-D7 of register NR23 are used for the lower 8-bit portion of the frequency data value. In the exemplary circuit shown, an 11-bit frequency data value stored in registers NR23, NR24 controls a frequency counter 82 to generate an output signal of frequency fd.

fd=4194304/(4*2 ³ (2048-X)) where fd is in Hz, and X is an 11-bit frequency value. The frequency data value X controls the pitch (ie, "pitch") of the signal generated by the sound generation circuit 542 .

The output of frequency counter 82 is applied to the input of duty cycle 88 . The duty circuit 88 controls the duty cycle of the audio output signal generated by the sound generating circuit 542 according to the content of the duty cycle setting register 86 . In the exemplary circuit shown, the duty cycle is specified by the two most significant bits D6-D7 of register NR21. As is well known, the duty cycle of a waveform relates to the amount of time that a periodic waveform is ON relative to the amount of time that the periodic waveform is OFF. Therefore, a 50% duty cycle (use the value "00" to set the highest bit D6-D7 of the register NR21) means that the on-time and off-time of the periodic waveform are the same. In the preferred embodiment, the value "11" is written into the highest bit D6-D7 of the register NR21 to select a waveform duty cycle of 75% (the output waveform generated in this way has an on-time of 1.5 times the off-time). In a similar way, write the value "01" into the highest bit of register NR21 (D6-D7), and a waveform with a duty cycle of 25% can be generated (that is, the on-time of the waveform is half of the off-time), and Write the data value "01" into these two most significant bits to generate a waveform with a duty cycle of 12.5%. It is well known that changing the duty cycle of an audio signal changes the timbre of the audio signal, thereby having the potential to provide many different sounds for the same frequency signal.

In the preferred embodiment, the duty cycle 88 is of conventional circuit configuration, which can vary the duty cycle of the periodic signal provided by the frequency counter data unit 82 to provide one of the four duty cycles described above.

The output of duty circuit 88 is provided to one input of AND gate 90 which gates the output of the duty circuit under the control of a length duration gate signal generated by length counter 94 . The length counter 94 generates the continuous strobe signal according to the content of the length setting register 92 . In the preferred embodiment, length setting register 92 actually contains the least significant bits D0-D5 of register NR21 shown in FIG. 5B. The contents of the length setting register 92 control the divisor of the length counter 94, which acts as a conventional programmable divider to divide the 256 Hz length clock frequency signal. In the preferred embodiment, the sound length fields D0-D5 of the register NR21 control the duration of the sound generated by the sound generating circuit 542 in a 64-tone scale according to the following relational expression.

Duration=(64-T1)*(1/256) second Wherein "duration" is the length of the music sound, and T1 is the value specified by the bits D0-D5 of the register NR21. Length counter 94 controls the duration of the sound produced by sound generating circuit 542 by gating the output of duty circuit 88 through AND gate 90 . In this way, the sound generating circuit 542 can be automatically "turned off" at the end of each note to save the CPU the cost of turning off the sound generating circuit at a suitable time. By writing a suitable numerical value into the length setting register 92, the CPU can control the sound generating circuit 542 to produce, for example, any note of required sound length (for example, 1/16 note, 1/8 note, 1/4 note, half note, etc.) note or whole note), and similarly, the length of musical rests can also be set in this way.

The resultant strobe signal developed at the output of AND gate 90 is applied to the enable input of a digital-to-analog (D/A) converter 96 . The D/A converter 96 actually produces an analog output level corresponding to the sound output of the sound generating circuit 542, the timing of which is generated is controlled by the output signal of the AND gate 90 (and depends on the selected frequency, duty cycle, and duration). The amplitude of the signal produced by D/A converter 96 can be fixed for certain notes, but can be automatically increased or decreased to produce other notes or sounds in the preferred embodiment.

Envelope counter 102 and associated components 98-108 provide parallel data to the parallel data input of D/A converter 96 for automatic control over time of the amplitude "level" of the acoustic output signal produced by the converter (The "envelope" of a sound refers to the amplitude envelope that contains the sound).

A relatively slow (eg, 64 Hz) envelope clock signal is applied to the input of programmable 1/N divider 100 in the preferred embodiment. The divisor provided by 1/N divider 100 is selected by the contents of envelope number register 98 . In the preferred embodiment, Envelope Interval Number Register 98 contains the least significant 3 bits D0-D2 of register NR22. In the preferred embodiment, 1/64th of a second is the fastest speed to change the "amplitude" of the sound envelope. However, the contents of the envelope number of intervals register 98 selects the rate of change of the sound output amplitude for each interval according to the following relation.

Interval duration=N*(1/64) second Wherein N is the numerical value stored in the position D0-D3 in the register NR22. In the preferred embodiment, a value of "000" stored in these bits stops the envelope counting operation (so that the amplitude of the audio output produced by D/A converter 96 remains constant).

The output signal of 1/N divider 100 controls the rate at which envelope counter 102 counts up or down. Envelope counter 102 is loaded in parallel with a 4-bit initial value from envelope initial value register 104 (in the preferred embodiment, this initial value register contains the four most significant bits D4-D7 of register NR22). In addition, up/down register 106 (which in the preferred embodiment contains bit D3 of register NR22) selects whether envelope counter 102 counts up or down (this provides two options: it starts at an initial value and increments to a maximum value, and starts at an initial value and decreases to zero). In the preferred embodiment, up/down register 106 controls the counting direction of envelope counter 102, or alternatively generates an input signal to D/A converter 96 indicating how the D/A converter interprets the envelope counter 102. The value added to it by network counter 102 (i.e., fade or boost).

Thus, envelope counter 102 starts counting from an initial value provided by envelope initial value register 104 and increments (or decrements) at a rate determined by the output frequency of 1/N divider 100 . As the envelope counter 102 counts, its parallel output value changes, and since the parallel value is converted to analog signal levels by the D/A converter 96, the amplitude of the acoustic output signal produced by the converter also changes.

Decoder 108 receives parallel data provided by envelope initial value register 104 and data provided by up/down register 106 . Decoder 106 decodes the data, and, when the initial value of the envelope is zero and specifies the decreasing direction, decoder 108 adds the decoded output to the reset input of flip-flop 80 and the D/A converter 96. The effect of this reset signal is to disable the operation of the D/A converter 96 (so that it does not output sound) and to disable the AND gate 76 (and thereby disable the entire sound generating circuit 542).

Exemplary program control steps and associated data structures for controlling the operation of the exemplary sound generator 58 are described below in connection with FIGS. 7A-9D.

Referring now more specifically to FIG. 9A , controls for controlling sound generation (in addition to other aspects of the video game, such as display of the video game by the LCD display 14, in response to user input provided by the controller 18, etc. ) are stored in external read-only memory (ROM) 16a in memory cartridge 16.

In addition, in the preferred embodiment, ROM 16a stores three data structures related to sound generation: frequency data table 312, sound length data table 314 and score data table 316. Briefly, the score data table 316 provides each sound generating circuit 541-544 with pitch, duration and "sound direction" (left channel, right channel or both) shown in FIG. The frequency data table 312 performs the mapping or conversion between the pitch information stored in the score data table 316 and the digital values that need to be loaded into the frequency setting registers 84 of the sound generation circuits 541-544 to produce the pitch information specified by the score data table 316. pitch. The sound length data table 314 provides mapping or conversion between the duration information stated in the score data table 316 and the sound length data that needs to be written into the sound length setting register 92 .

FIG. 9B is an exemplary functional block diagram of the contents of the frequency data table 312 shown in FIG. 9A. In the preferred embodiment, each pitch is defined by a sequence of four hexadecimal values stored in frequency data table 312. For example, a musical rest (ie, no sound) may be represented by the value "0000", a key of C may be represented by "AB01", a major C key may be represented by "0193", and so on. In the preferred embodiment, the frequency data table 312 stores these values in chromatic notation order, i.e., starting with the musical body stop, followed by the key of C, by increasing the pitch every semitone (e.g., C, C ^# , D, E ^b (D ^# ), E, F, etc.). The hexadecimal data values stored in the frequency data table 312 correspond to the digital values that when these digital values are loaded into the frequency data registers associated with the sound generating circuits 541-544 (for example, as previously mentioned, the register Bits D0-D7 of NR23 and bits D0-D2 of register NR24) will cause the frequency corresponding to the defined pitch to be generated by the associated sound generating circuit. That is to say, for example, when the hexadecimal value "AB01" is written into the registers NR23, NR24, the sound generating circuit 542 will generate a sound with frequency (pitch) C. By storing the numerical values in the frequency data table 312, the programmer writing the program control instructions 310 need not worry about the specific numerical values that must be loaded into the sound control registers in order to form the desired pitch. It will be readily apparent that the programmer need only specify the appropriate address index from base address FREQD, (frequency data table 312 begins at base address) to specify the appropriate tone required. Automatic conversion of this address type value into appropriate data for writing into eg registers NR23 and NR24 is then provided by frequency data table 312 .

Likewise, the length data table 314 stores the duration of the rhythmic tone commonly used (for example, 16th note or rest, 8th note or rest, quarter note or rest, half note or rest, whole note or rest, dotted quarter note or rest, dotted half note or rest, etc.). In the exemplary embodiment shown, the sound length data table 314 starts storing from the base address ONPU, and the first entry of the duration data table stores the hexadecimal value "06" corresponding to the sound length of a 16th note . That is, in the preferred embodiment, when the duration of the value "06" is loaded into the lowest 6 bits of the aforementioned register NR21, the sound generating circuit 542 will be generated at a predetermined fixed rate and its length corresponds to 16 A note or rest of a diaeresis. Different commonly used sound lengths are stored in the duration data table 314 in a predetermined order. Therefore, the programmer need not worry about the exact value of the sound length bits D0-D5 of register NR21 (for example) that must be written to obtain the desired sound length. On the contrary, he only needs to specify the appropriate offset in the duration data table 314, and then he can choose the length of the sound he wants to use among the common sound lengths.

FIG. 9D is an exemplary schematic diagram of the score data table 316 . The score data table 316 shown in FIG. 9D corresponds to the "sound 2" (second) row of the exemplary music shown in FIG. 6 . Obviously, the data provided for the other 3 lines is preferably similar, and the corresponding data of all these 4 lines of music are read out from ROM 16a substantially in parallel to generate 4 lines of music at the same time. In the preferred embodiment, the score data table 316 starts at the base address BASE and includes 3 entries consisting of 2 hexadecimal numbers, each of which is used for each note or rest represented by the score in Figure 6 . The first 2 digits of hexadecimal data correspond to the offset in the duration data table 314 that corresponds to the duration of the note or rest. The second 2-digit hexadecimal number corresponds to the offset in the frequency data table 312 corresponding to the desired pitch. The last 2 bits of hexadecimal data (in the preferred embodiment, can actually be a binary value since only 4 states are represented) specify the "direction" of the sound (i.e., left channel, right channel, dual channel or no channel).

Like this, for example, the first note of the first measure of the "sound 2" music line shown in Fig. 6 is a quarter-cent rest. Therefore, the first entry of the music score data table 316 indicates that the offset in the pitch data table 314 is "02", which corresponds to a quarter note or a rest. The second entry of the musical score data table 316 describes the zero offset of the audio data table 312 to designate 1 rest (as opposed to a musical note). The third and last entry corresponding to the first note of the first bar is the value "01", specifying that the sound is only to be sent to the output sound channel S01 and not to the output sound channel S02.

The score data table 316 provides a sequence of such data sets corresponding to a sequence of notes of a melody or rhythm line. Thus, for example, the following three 2-digit hexadecimal values stored in the score data table 316 correspond to the second note of the first measure in the row "Sound 2" shown in FIG. The first 2-digit hexadecimal number of the data set is "02", specifying the length of a quarter note, which corresponds to the offset in the length data table 314 . The second 2-digit hexadecimal number of this data set specifies the offset "OA" in the frequency data table 312, which is equivalent to the E tone. The last value of the data set corresponds to the sound direction "01", specifying that the note is only intended to be given to the sound output channel S01 and not to the sound output channel S02.

Obviously, the entire music line can be converted and stored in the score data table 316 in the form shown in FIG. 9D. To "play" the music represented by the score, simply read the data set in the order presented in the score data table 316, refer to the length data table 314 and the frequency data table 312 in order to map the length and pitch information to the Load the corresponding values of the appropriate sound control registers, then load the sound registers with the actual synthesized data. Once the note is terminated, the data set corresponding to the next note in the musical sequence can be read from the score data table 316 and the whole process repeated again to generate the next note. This entire process can be repeated continuously until the end of the score data table 316 is reached (at which point, if desired, the score data table 316 can be read from the beginning again, resulting in a repetition of the song over and over).

7A and 7B together are a schematic flow diagram of exemplary program control steps implemented in the program control instructions 310 shown in FIG. sound control. Obviously, several replicated programs of the exemplary program control steps shown in FIGS. 7A-7B are preferably executed simultaneously (substantially in parallel) to generate multiple lines of music by respective sound generating circuits 541-544. In other words, the exemplary program control steps shown in FIGS. 7A-7B control only a single sound generating circuit (eg, circuit 542). Other iterations of the exemplary steps should be performed by CPU 24 to control other sound generating circuits (eg, 541, 543, 544).

Upon initiation of the routine shown in FIGS. 7A-7B, the base address (i.e., the start address) of the appropriate score data table 316 is obtained and written to the memory pointer register specifying the particular score data table (block 350 ) (obviously, more than one score data table 316 can be stored in the program ROM16a to provide reproducible multiple different possible musical sections or sounds). The note tracking counter CNT (preferably a register within CPU 24 or a location in RAM) is then cleared and a timer (eg, timer 24d shown in FIG. 2) initialized (block 352). Initially, this timer can be set to a value of "01" so that it can be decremented immediately and execute the remainder of the shown routine. The timer is then decremented (block 354) and it is determined whether the value is zero (decision block 356). If the timer is greater than zero, control returns to block 354 to decrement the timer again, and blocks 354, 356 are repeated until the timer value is decremented to zero. The loop formed by blocks 354, 356 counts the duration of the current note or rest. Obviously, this timing can, if desired, be interrupted by hardware timer 24d driven interrupts in a well known manner.

Then access the first 2-digit hexadecimal data stored in the score data table 316 by adding the base address to the current CNT value, access the program ROM 16a to read out the contents stored in this unit, and store these contents in A scratchpad location called H (block 358). Then, the content of H is compared with the "FF" value to determine whether the end entry of the music score data table 316 has been reached (decision block 360), (in the preferred embodiment, this can be done by assigning the value "FF" or other tones long data table 316 invalid offset to mark the end of the table). Assuming that the content of H is an effective offset of the sound length data table 314, then use H as the address in the offset calculation duration data table from the base address ONPU of this table, and read the sound length with the address synthesized and calculated The contents stored in the data table 314 are loaded into the timer (block 362). In this way, the timer is initialized with the duration of the next note or rest to be produced. The search value can also be loaded into the sound length data field of the sound control register (such as NR11 bits D0-D5) so that the CPU 24 does not need to close the sound generating circuit when reaching the note end item.

The counter CNT is then incremented (block 364 ) to access the next 2-digit hexadecimal number in the score data table 316 . Access the next cell in the score data table, (eg, calculate an address based on the sum of the base address and CNT), read its content and store it in temporary storage cell Q (block 366). The frequency data table 312 is accessed using the offset now stored in the frequency data table 312 at temporary storage unit Q (blocks 368, 370). In the preferred embodiment, two consecutive locations of frequency data table 312 need to be read at this point to retrieve sufficient information to account for the 11 bits of frequency data stored, for example, in NR13-NR14. These values are retrieved from the frequency data table 312 and stored in temporary storage locations X, Y (blocks 368, 370), and then the contents of temporary storage locations X, Y are tested to determine whether they are all zeros, which It is indicated that the sound currently to be produced is a rest rather than a note (decision block 372). If the current sound is a rest, then the envelope initial value register and the increment/decrement registers 104, 106 of the corresponding sound generating circuit (eg, 542) are cleared to disable the sound generating circuit from generating sound (block 374). On the other hand, if the search value corresponding to a certain pitch replaces the rest ("N" exit of decision box 372), then the frequency setting register 84 is set with the value stored in the temporary storage unit X, Y (box 376), to determine the pitch of the note to be produced.

The CNT counter is then incremented (block 378), and the third value stored in the score data table 316 corresponding to "sound direction" is read (block 380). The retrieved data is then tested to see if it corresponds to new output direction data (decision block 382). In the preferred embodiment, although left or right "sound direction" data as shown in Fig. memory) only accounts for sound direction data when the sound direction corresponding to a particular sound generating circuit has changed relative to previous notes in the sequence. Like this, in the preferred embodiment, since some data sets stored in the score data table 316 have only 2 2-digit hexadecimal numbers instead of 3 (if the sound direction is the same as the last played note, then omit the sound direction data). Judgment frame 382 shown in Figure 7B judges whether to have read out new sound direction data, as read out, according to the value obtained by frame 380, the appropriate position of appropriate sound control register is set (for example, register NR51 bit D1, D5 ), (block 384) and increment the counter CNT (block 386) to point to the beginning of the next data set stored in the score data table 316. On the other hand, if the value read by block 380 is not new sound direction data, then block 386 does not perform an increment of counter CNT and control returns to blocks 354, 356 as shown in FIG. 7A.

Once control returns to blocks 354, 356, the countdown timer clocks the current note or rest. Once the duration has elapsed, the processing of blocks 358-386 is repeated again for the next note or rest to be produced.

FIG. 8 is a schematic schematic diagram of the stereo/mono selection circuit 202 shown in FIG. 4 . The selection circuit 202 receives the left channel sound signal S01 from the amplifier 60L and the right channel sound signal S02 from the amplifier 60R, and sends the appropriate signal to the speaker 120 or to the stereo earphone 64 . Especially, if the plug of the stereo earphone 64 is not connected to the earphone jack 122, then the stereo/mono selection circuit 202 mixes the sound signals S01, S02 of the left and right channels to provide a mono signal, and the mono signal The channel signal is applied to the speaker 120. On the other hand, if a stereo earphone 64 is connected to the earphone socket 122, the stereo/mono selection circuit 202 couples the left channel sound signal S01 to the left ear transducer of the earphone, and couples the right channel sound signal S02 to the earphone's ear transducer. Right ear transducer.

In the preferred embodiment, the output of amplifier 60L shown in FIG. 4 is coupled to the input of amplifier 114L through series resistor 112L. Similarly, the output of amplifier 60R shown in FIG. 4 is coupled to amplifier 114R through series resistor 112R. input terminal. Resistors 116L, 116R are connected in series across the input terminals of amplifiers 114L, 114R. The junction of resistors 116L, 116R is coupled to the input of mono amplifier 118 . Resistors 116L, 116R function to mix the S01 and S02 signals together and provide the resulting mixed (mono) signal to amplifier 118 . Amplifier 118 drives speaker 120 .

The earphone jack 122 includes a left channel audio contact 122L, a right channel audio contact 122R and a pair of switch contacts 122P. A headphone plug 124 coupled to a headphone 124 is intended to be received and mated by the headphone jack 122 . The earphone socket 122 can be, for example, a female fitting that cooperates with the earphone plug 124 as a plug-in fitting. Thus, the headphone plug 124 can be inserted into the headphone socket 122 to connect the headphones 64 to the outputs of the amplifiers 114L, 114R, and can be later removed from the socket to disconnect the headphones from the amplifier. For example, sometimes the user may wish to use the earphone 64 to listen to the sound generated by the sound generating block 58 (at this time, the earphone plug 124 can be inserted into the socket 122). At other times, the user may not wish to use the earphones and unplug the earphone plug 124 from the earphone socket 122 (in order to listen to the sound through the speakers 120 instead of the earphones 64).

The earphone plug 124 includes a left channel contact 124L and a right channel contact 124R. When the plug is mated with the socket, the right channel contact 124L forms electrical contact with the left channel audio contact 112L of the earphone plug, and at the same time, the right channel contact 124R contacts with the The earphone plug left channel audio contact 112R makes electrical contact. Ground portion 124G is preferably connected to ground. Plug left channel contact 124L is connected to the left channel transducer of earphone 64 by left channel wire 126L, while plug right channel contact 124R is connected to the right channel transducer of earphone 64 by right channel wire 126R.

Whenever the earphone plug 124 is inserted into the earphone jack 124 , the contacts 122P are in contact with each other to form an electrical connection between the input ends of the inverting amplifier 130 and the non-inverting amplifier 132 . This ground connection causes inverting amplifier 130 to generate a logic level "1" signal, which signal is used to allow amplifiers 114L, 114R to operate. This ground connection also causes non-inverting amplifier 132 to generate a logic level "0" signal that disables amplifier 118 from operation. In this state, stereo signals are supplied by amplifiers 114L, 114R to earphone 64 via contacts 122L, 122R and 124L, 124R and speaker 120 is disabled.

On the other hand, once the earphone plug 124 is disconnected from the earphone socket 122, the contacts 112P are no longer connected to each other. The pull-up resistor 128 connected to the power supply emf pulls up the input of the inverting amplifier 130 and the input of the non-inverting amplifier 132 to logic level "1". A high level of this logic level causes inverting amplifier 130 to apply a logic level "0" signal to amplifiers 114R, 114L (thus disabling both amplifiers) and causes non-inverting amplifier 132 to apply a logic level "0" signal to amplifiers 114R, 114L (thus disabling both amplifiers from operation) The 1" signal is applied to amplifier 118 (thus enabling the amplifier to operate). In this case, a mono signal is synthesized (mixed) by amplifier 118 and applied to speaker 120 . Since the earphones are not connected to the socket, the amplifiers 114L, 114R do not apply signals to the earphone socket contacts 112L, 112R.

While the invention has been described in connection with what are presently considered to be the most practical and best embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, the invention is intended to cover the spirit and scope of the invention contained in the appended claims. Variations and equivalent structures within the range.

Claims (9)

1, pseudostereo generating means is characterized in that including:

Be used for producing the sound source signal generating device of sound-source signal at its output,

First switching device, its input links to each other with the output of described sound source signal generating device and is coupled to first audio signal output terminal, described first switching device is used for the output of described sound source signal generating device is coupled with described first audio signal output terminal selectively by its switching manipulation

The second switch device, its input links to each other with the output of described sound source signal generating device and is coupled to the second sound signal output, described second switch device is used for the output of described sound source signal generating device is coupled with described second sound signal output selectively by its switching manipulation, and

The switch controlling device that is coupled with described first and second switching devices, be used for producing selectively with described first switching device and at least one switching signal that switches on and off of described second switch device, and these signals are added to described first switching device and described second switch device.

2, according to the pseudostereo generating means of claim 1, it is characterized in that:

Described sound source signal generating device comprises the sound signal generation circuit of a plurality of each self-forming independence sound signal, and

Corresponding respectively a plurality of first switching circuits and a plurality of second switch circuit of each self-contained and described a plurality of sound-source signal generation circuit in described first and second switching devices, its output of described a plurality of first switching circuit links to each other with described first audio signal output terminal usually, and its output of described a plurality of second switch circuit links to each other with described second sound signal output usually.

3, according to the pseudostereo generating means of claim 1, it is characterized in that also comprising:

First level controller with described first audio signal output terminal coupling, be used for the level that is added to described first audio signal output terminal by described first switching device is controlled, and be used for described controlled level signal is added to another first output, and

Second level controller with described second sound signal output coupling is used for the level that is added to described second sound signal output by described second switch device is controlled, and is used for described controlled level signal is added to another second output.

4, according to the pseudostereo generating means of claim 1, it is characterized in that, also include:

Operationally with the storage device of described switch controlling device coupling, in order to store the switch control data of the switching manipulation of specifying described first switching device and described second switch device, described switch controlling device produces described switching signal according to the described switch control data that is stored in described storage device.

5, in the electronic game computer that comprises the main frame type; Described main frame comprises with the control two dimensional display and by the steerable input unit reception of user imports the digital processing unit that is associated; Described main frame removably is coupled with interchangeable memory cartridge; Described memory cartridge provides program control instruction for described digital processing unit; The described digital processing unit described input that receives of response and described program control instruction; Forming the game that changes at described two dimensional display at least in part shows

In described electronic game computer, be used to produce the method for stereophonic effect, it is characterized in that may further comprise the steps:

(a) provide the data of representing sound signal,

(b) the described data that provide of response produce described sound signal,

(c) provide and specify described sound signal whether to supply with the output of first audio channel and specify described sound signal whether to supply with the audio direction data of second audio channel output, and

(d) the described audio direction data of response are for described sound signal selects the path to output of described first audio channel and/or the output of described second audio channel.

6,, it is characterized in that describedly step (a) is provided and (c) may further comprise the steps separately according to the method for claim 5:

In described memory cartridge, stored data in advance, and

To supply with described digital processing unit from the data of the described storage of described memory cartridge.

According to the method for claim 6, it is characterized in that 7, the step that the described datagram ground that provides of response synthesizes described sound signal is provided described generation step (b).

According to the method for claim 5, it is characterized in that 8, described selection path step may further comprise the steps:

Respond the described first audio direction data manipulation, first switch element, described sound signal is coupled to the output of described first audio channel, and

Respond described second sound bearing data operation second switch element, described sound signal is coupled to the output of described second audio channel.

9, in the method that in electronic game computer, is used to produce stereophonic effect according to claim 5, it is characterized in that, step (a) and step (c) are all carried out in described cartridge, promptly, in described cartridge, first data of expression sound property are provided and select the output of first audio channel arbitrarily and the audio direction data of second audio channel output.

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