CN103137189A

CN103137189A - Distributed self-timing circuit

Info

Publication number: CN103137189A
Application number: CN2012105635524A
Authority: CN
Inventors: 拜福君; 付妮
Original assignee: Xian Sinochip Semiconductors Co Ltd
Current assignee: Xian Sinochip Semiconductors Co Ltd
Priority date: 2012-12-21
Filing date: 2012-12-21
Publication date: 2013-06-05
Anticipated expiration: 2032-12-21
Also published as: CN103137189B

Abstract

The invention relates to a distributed self-timing circuit applied to a static random storage. The distributed self-timing circuit comprises a redundant row containing at least one redundancy, and a pull-down discharge circuit row is arranged adjacent to the redundant row. Pull-down discharge circuits in the pull-down discharge circuit row are the same as the redundancies in the redundant row in number, and the pull-down discharge circuits and the redundancies are arranged in one to one correspondence. Each pull-down discharge circuit is connected to a duplication bit line segment of a redundancy corresponding to each pull-down discharge circuit. The distributed self-timing circuit is high in stability, and saves distribution space.

Description

Distributed self-timing circuit

Technical field

The present invention relates to a kind of self-timing circuit, relate in particular to the distributed self-timing circuit of using in a kind of static RAM.

Background technology

Often use in the static RAM design based on the self-timing circuit technology that copies bit line.Common drop-down discharge circuit is used for the discharge of simulating normal storage unit pairs of bit line.Voltage detector be used for to be surveyed and to be copied on bit line all voltage, produces feedback signal when it reaches the magnitude of voltage of setting, and indication control circuit array neutrality line voltage difference meets the demands, sense amplifier can start working (as Fig. 1).Although mainly by the power decision of the load that copies bit line and drop-down discharge circuit, the position of drop-down discharge circuit is also influential to length regularly for the length of whole timing.Due to the restriction of chip layout, general drop-down discharge circuit is placed on the two ends of redundant columns, no matter is placed on which end, self-timing circuit simulation be all discharge process from the nearest storage unit of drop-down discharge circuit.Say exactly time-delay that self-timing circuit produces and mate most from the needed time-delay of the normal read-write of own nearest storage unit, and more do not mate with the time-delay that distance storage unit far away needs.This loss capability error even that may cause chip performance that do not mate.

Summary of the invention

In order to solve existing technical matters in background technology, the present invention proposes a kind of distributed self-timing circuit.Can simulate exactly the discharge process of each line storage unit, guarantee time-delay that self-timing circuit the produces delay match required with read-write all the time, thereby improve the stability of chip.

Technical solution of the present invention is:

A kind of distributed self-timing circuit comprises redundant columns, and its special character is: redundant columns comprises at least 1 redundancy, and redundant columns is adjacent is provided with drop-down discharge circuit row; And the one by one corresponding setting identical with the redundancy number in redundant columns of drop-down discharge circuit in drop-down discharge circuit row; Each drop-down discharge circuit is connected to copying on the bit line fragment of the redundancy corresponding with it.The bit line fragment that copies in each redundancy connects and composes successively and copies bit line DBL.Distributed self-timing circuit also comprises and copies column selection and precharging circuit, voltage detector.Redundant columns is connected to and copies column selection and precharging circuit through copying bit line DBL.

Advantage of the present invention is:

1. improve stability.Due to each drop-down discharge circuit and the adjacent setting of redundancy, and be connected at this redundancy place and copy bit line DBL.Therefore the discharge process that can simulate exactly each line storage unit guarantees time-delay that self-timing circuit the produces delay match required with read-write all the time, thereby improves the stability of chip.

2. saving arrangement space.Adopt the circuit structure of the discharge path that is similar to storage unit due to drop-down discharge circuit, thus can be easily drop-down discharge circuit of each line storage unit coupling in domain, and can not cause larger chip area to increase.Due to the drop-down discharge circuit that does not need to be positioned at the redundant columns two ends, can save chip area in addition.

Description of drawings

Fig. 1 is the self-timing circuit figure of the former static RAM of the present invention.

Fig. 2 is self-timing circuit figure of the present invention.

Fig. 3 is a drop-down discharge circuit figure of the present invention.

Fig. 4 is column selection and the precharging circuit of copying of the present invention, the circuit diagram of voltage detector.

Embodiment

Referring to Fig. 2, the present invention increases drop-down discharge circuit row near the redundant columns of normal memory cell array.Each drop-down discharge circuit in drop-down discharge circuit row can both independently be worked and be completed regularly.Each drop-down discharge circuit and with array in each row alignment of being adjacent.The drop-down discharge circuit of each after alignment is corresponding with the delegation of memory cell array, how many row are storage unit have how many drop-down discharge circuits just need to be arranged: the unlatching of the drop-down discharge of one side will be by the word line (WL_0 of this row of correspondence, WL_1, WL_N) independent control, rather than by copying word line DWL co-controlling; Drop-down discharge circuit and the position that also is positioned at this row that is connected of copying bit line DBL on the other hand, rather than the two ends of redundant columns.No matter which is read and write, the discharge process that can simulate the one's own profession normal memory cell with the drop-down discharge circuit corresponding with this row, thus guarantee that the time-delay that self-timing circuit produces mates all the time.In addition, copy word line DWL or necessary, only be used for controlling the preliminary filling that copies bit line DBL: no matter which in drop-down discharge circuit row started working, and all needs to stop copying the preliminary filling of bit line DBL.Copy column selection and precharging circuit and be connected to and copy bit line DBL, control DBL is carried out precharge by copying word line DWL, DBL is connected to voltage detector through copying column selection.

Referring to Fig. 3, a drop-down discharge circuit of the present invention adopts the circuit structure of the discharge path that is similar to storage unit.Pull-down circuit is effective when DWL is ' 1 '.Because structure and the storage unit of drop-down discharge circuit are similar, thus can be easily drop-down discharge circuit of each line storage unit coupling in domain, and can not cause larger chip area to increase.Drop-down discharge circuit adopts the domain structure of the discharge path that is similar to storage unit.The domain height of each drop-down discharge circuit and storage unit is identical.The edge of general storage unit is redundancy unit, we increase a contour drop-down discharge circuit again at the edge of redundancy unit, due to structural similarity, do not need extra cabling just can realize following two purposes on domain: drop-down discharge circuit can be shared same word line with storage unit on the one hand, on the other hand, drop-down discharge circuit can be connected to nearby very easily and copy on bit line.

Referring to Fig. 4, Fig. 4 is column selection and preliminary filling, the voltage detector circuit diagram of copying of the present invention.

Transistor PPRE is precharging circuit, by the DWL signal controlling, when DWL is ' 1 ', stops the preliminary filling to DBL; When DWL is ' 0 ', transistor PPRE conducting, DBL is charged to supply voltage VDD in advance.It is the column selection circuit that transistor NPS and PPS have consisted of a complementary transmission gate, and they are in normally open here.DBL is connected with RDBL through transmission gate, and RDBL is as the input of voltage detector INV.INV is output as feedback signal ST.

Voltage detector adopts the phase inverter of a standard, and circuit structure is simple, saves area.The rollback point of standard phase inverter is probably at 1/2 supply voltage VDD.Work as input signal, namely copy bit line, voltage during lower than 1/2 supply voltage, the feedback signal of phase inverter output is ' 1 ', otherwise is ' 0 ', thereby completes the detecting and identifying that copies voltage on bit line.When regularly beginning, copy bit line and be charged in advance VDD, output feedback signal be ' 0 ', after copying word line DWL and opening, copies bit line and begins to begin to discharge via drop-down discharge circuit, and when copying bit line pulldown to rollback point 1/2*VDD, output feedback signal is ' 1 '.

Claims

1. a distributed self-timing circuit, comprise redundant columns, it is characterized in that: described redundant columns comprises at least 1 redundancy, and described redundant columns is adjacent is provided with drop-down discharge circuit row; And the one by one corresponding setting identical with the redundancy number in redundant columns of drop-down discharge circuit in described drop-down discharge circuit row; Described each drop-down discharge circuit is connected to copying on the bit line fragment of the redundancy corresponding with it.

2. distributed self-timing circuit according to claim 1 is characterized in that: described distributed self-timing circuit also comprises and copies column selection and precharging circuit, voltage detector.

3. distributed self-timing circuit according to claim 1 is characterized in that: the bit line fragment that copies in described each redundancy connects and composes successively and copies bit line DBL.

4. distributed self-timing circuit according to claim 1 is characterized in that: described redundant columns is connected to and copies column selection and precharging circuit through copying bit line DBL.