CN103135296A - Thin film transistor liquid crystal display (LCD) array substrate - Google Patents
Thin film transistor liquid crystal display (LCD) array substrate Download PDFInfo
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- CN103135296A CN103135296A CN2011103917004A CN201110391700A CN103135296A CN 103135296 A CN103135296 A CN 103135296A CN 2011103917004 A CN2011103917004 A CN 2011103917004A CN 201110391700 A CN201110391700 A CN 201110391700A CN 103135296 A CN103135296 A CN 103135296A
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- 239000000758 substrate Substances 0.000 title claims description 55
- 239000010409 thin film Substances 0.000 title claims description 22
- 239000004973 liquid crystal related substance Substances 0.000 title description 3
- 229910052751 metal Inorganic materials 0.000 claims description 57
- 239000002184 metal Substances 0.000 claims description 57
- 238000002161 passivation Methods 0.000 claims description 27
- 238000010276 construction Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 description 25
- 238000000034 method Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 8
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- 239000011521 glass Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000003252 repetitive effect Effects 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 238000002294 plasma sputter deposition Methods 0.000 description 2
- 241001062009 Indigofera Species 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 239000002243 precursor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention discloses a thin film transistor liquid crystal display (LCD) array substrate which comprises two adjacent main pixel areas along a first direction, two gate lines, two common lines, three data lines and an electrode connecting line. Each main pixel area comprises three adjacent sub pixel areas along a second direction, the two gate lines are arranged on a first metal layer along the first direction, the two common lines respectively correspond to the two main pixel areas and are arranged on a second metal layer, the three data lines are arranged on the second metal layer along the second direction, and the electrode connecting line is arranged on a third metal layer and connected with the two common lines in the first direction in a breakover mode. The parts, in a display area, of the common lines are arranged in a parallel connection mode, namely, a mesh-shaped common line structure, the overall resistance of the common lines is reduced, the delay time for a corresponding signal to pass through the common lines is reduced, and therefore the occurrence rate of unhealthy phenomena including flicker, crosstalk and the like of the thin film transistor LCD array substrate is also lowered.
Description
Technical field
The invention belongs to field of liquid crystal display, relate in particular to a kind of thin-film transistor LCD device array substrate.
Background technology
In prior art, the arrangement of three pixel regions of a main pixel region of display panel from left to right is respectively r (red), g (green), b (indigo plant), wherein, each main pixel region is square or circular, each time pixel region is rectangle, and the minor face of each time pixel region is substantially parallel with gate line, and the long limit of each time pixel region is substantially parallel with data line, and the arrangement mode of this pixel region is called longitudinal arrangement usually.
In 3D showed, in order to allow people's right and left eyes see different images, being placed in the front grating grid of display panel needed longitudinal arrangement, and wherein the size of grating grid and a main pixel region is big or small close; Bit errors during due to the glass plate at grating grid place and display panel assembling causes the grating grid may shelter from certain color, such as the part area that has blocked red pixel region, thereby causes serious color deviation and aberration.In order to address this problem, prior art provides transversely arranged dot structure, be about to each color time pixel region transversely arranged, even bit errors is arranged when the glass plate at grating grid place and display panel are assembled like this, the inferior pixel region of three colors all can be blocked identical area, although the light transmission capacity of each time pixel region descends to some extent, three times the formed color of pixel region does not have skew.
Present horizontal Pixel arrangement mode comprises following several: the Pixel arrangement mode of the horizontal use of perpendicular screen that single grid drive, the pixel horizontal mode that the pixel horizontal mode that bigrid drives and three grids drive.But the Pixel arrangement mode of the horizontal use of perpendicular screen that single grid drive need to add buffer that display is transformed anyhow, has increased system cost; When resolution was higher, three grids drove horizontal Pixel arrangement mode and are difficult to reach the driving requirement.So the pixel horizontal mode that prior art generally adopts double grid to drive, as shown in Figure 1, in the pixel horizontal mode that double grid drives with two adjacent main pixel regions as minimum basic structure, each minimum basic structure generally comprises:
Article two, gate lines G 1 and G2, three data line D1, D2 and D3, six thin film transistor (TFT) T1, T2, T3, T4, T5 and T6, six pixel electrode g1, r1, b1, r2, b2 and g2, and two common line (not shown)s.
But the incidence of the flicker of existing display panel structure and the bad phenomenon such as crosstalk is higher.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of thin-film transistor LCD device array substrate, with the flicker that solves existing display panel structure and the higher problem of bad phenomenon incidence such as crosstalk.
This thin-film transistor LCD device array substrate comprises:
Along two adjacent main pixel regions of first direction, wherein, each main pixel region comprises respectively three along the adjacent inferior pixel region of second direction;
Article two, gate line, described two gate lines are arranged on the first metal layer along first direction;
Article two, common line, described two common lines correspond respectively to two main pixel regions, and are arranged on the second metal level;
Article three, data line, described three data lines are arranged on the second metal level along second direction;
The connecting electrode line, described connecting electrode line is arranged on the 3rd metal level, and on first direction the described two common lines of conducting.
Preferably, comprise passivation layer between described the second metal level and the 3rd metal level, the position that described passivation layer is positioned at above common line is provided with the first contact hole, and described common line and connecting electrode line are electrically connected to by the first contact hole.
Preferably, described two common lines are not all not closedly around each time pixel region in its corresponding main pixel region.
Preferably, described the 3rd metal level is transparent metal layer.
Preferably, described first direction is perpendicular to described second direction.
Preferably, described data line comprises:
This tagma of data line, source electrode and drain electrode;
This tagma of described data line and source electrode are an one-piece construction;
Described source electrode separates with drain electrode.
Preferably, be provided with pixel electrode in described the 3rd metal level.
Preferably, the position that described passivation layer is positioned at above drain electrode is provided with the second contact hole, and described drain electrode is electrically connected to by described the second contact hole with pixel electrode.
Because thin-film transistor LCD device array substrate provided by the present invention comprises: along two adjacent main pixel regions of first direction, wherein, each main pixel region comprises respectively three along the adjacent inferior pixel region of second direction; Article two, gate line, described two gate lines are arranged on the first metal layer along first direction; Article two, common line, described two common lines correspond respectively to two main pixel regions, and are arranged on the second metal level; Article three, data line, described three data lines are arranged on the second metal level along second direction; The connecting electrode line, described connecting electrode line is arranged on the 3rd metal level, and on first direction the described two common lines of conducting.
As seen, common line is by the conducting on first direction of connecting electrode line, form pattern in parallel in the viewing area, it is netted common line structure, the overall resistance of common line has reduced, and then reduced corresponding signal through the time delay of described common line, therefore, the incidence of the flicker of this thin-film transistor LCD device array substrate and the bad phenomenon such as crosstalk has also reduced.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or description of the Prior Art, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is existing TFT-LCD array substrate structure schematic diagram;
Fig. 2 is TFT-LCD array substrate structure schematic diagram provided by the present invention;
Fig. 3 is that the present invention forms TFT-LCD array substrate structure gate line structural representation afterwards;
Fig. 4 is that the present invention forms TFT-LCD array substrate structure TFT channel structure structural representation afterwards;
Fig. 5 is that the present invention forms TFT-LCD array substrate structure data line, common line structural representation afterwards;
Fig. 6 is that the present invention forms the passivation layer of TFT-LCD array substrate structure and the structural representation after contact hole.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Just as stated in the Background Art, the incidence of the flicker of existing display panel structure and the bad phenomenon such as crosstalk is higher.
The inventor finds after deliberation, the relevant property of resistance of common line in the generation of flicker and the bad phenomenon such as crosstalk and display panel, the resistance of common line is larger, the incidence of the bad phenomenon such as glimmer accordingly and crosstalk is just higher, so, can improve by the resistance that reduces common line flicker and crosstalk etc. bad.
The invention discloses a kind of thin-film transistor LCD device array substrate, comprising:
Along two adjacent main pixel regions of first direction, wherein, each main pixel region comprises respectively three along the adjacent inferior pixel region of second direction;
Article two, gate line, described two gate lines are arranged on the first metal layer along first direction;
Article two, common line, described two common lines correspond respectively to two main pixel regions, and are arranged on the second metal level;
Article three, data line, described three data lines are arranged on the second metal level along second direction;
The connecting electrode line, described connecting electrode line is arranged on the 3rd metal level, and on first direction the described two common lines of conducting.
Can be found out by such scheme, common line is by the conducting on first direction of connecting electrode line, form pattern in parallel in the viewing area, it is netted common line structure, the overall resistance of common line has reduced, and then reduced corresponding signal through the time delay of described common line, therefore, the incidence of the flicker of this thin-film transistor LCD device array substrate and the bad phenomenon such as crosstalk has also reduced.
It is more than the application's core concept, below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Embodiment one:
The present embodiment discloses a kind of thin-film transistor LCD device array substrate, comprising:
Along two adjacent main pixel regions of first direction, wherein, each main pixel region comprises respectively three along the adjacent inferior pixel region of second direction;
Article two, gate line, described two gate lines are arranged on the first metal layer along first direction;
Article two, common line, described two common lines correspond respectively to two main pixel regions, and are arranged on the second metal level;
Article three, data line, described three data lines are arranged on the second metal level along second direction;
The connecting electrode line, described connecting electrode line is arranged on the 3rd metal level, and on first direction the described two common lines of conducting.
Concrete, (Fig. 2-a is vertical view as shown in Figure 2, Fig. 2-b is the sectional view along A-A ' line), two gate lines G 11 and the G12 of this thin-film transistor LCD device array substrate are set in parallel in the lip-deep the first metal layer of substrate 1 along first direction, be provided with the grid (not shown) on gate lines G 11 and G12, described substrate 1 is glass substrate or the substrate of other materials.
Also be coated with gate insulator 2 on gate lines G 11 and G12 surface, the position corresponding with grid is provided with TFT channel structure (not shown) on gate insulator 2 surfaces, described gate insulator 2 also covers on first substrate 1 surface, and it is made material and is preferably SiNx.
At gate insulator 2 and TFT (Thin Film Transistor, thin film transistor (TFT)) be provided with the second metal level on the channel structure surface, two common line C11, C12 and be arranged on the second metal level along three data line D11, D12, D13 of second direction.Described data line comprises this tagma, source electrode and drain electrode (not shown), and described this tagma and source electrode are structure as a whole, and described source electrode separates setting with drain electrode.Described source electrode, drain electrode and above-mentioned TFT channel structure, grid have consisted of the TFT on the thin-film transistor LCD device array substrate, i.e. T11, T12, T13, T14, T15 and T16 together.Article three, data line D11, D12, D13 and two gate lines G 11, G12 have consisted of two main pixel regions and two six pixel regions that main pixel region is included, in Fig. 2-a, two main pixel regions are arranged along first direction, three pixel regions in each main pixel region are arranged along second direction, article two, common line C11, C12 correspond respectively to two main pixel regions, pass through the metal conduction of the second metal level on second direction, and each common line is not closedly around each time pixel region in its corresponding main pixel region.
Need to prove, described common line can also be closed around each time pixel region in its corresponding main pixel region, but in the situation that common line width is certain, the closed aperture opening ratio that can reduce liquid crystal indicator around each time pixel region in its corresponding main pixel region.So under the prerequisite that satisfies the prior art requirement, common line can be not closedly around each time pixel region in its corresponding main pixel region, to increase aperture opening ratio.
Also be provided with passivation layer 3 on data line and common line and gate insulator surface, position above described passivation layer 3 is positioned at common line is provided with the first contact hole 3-1, position above described passivation layer is positioned at drain electrode is provided with the second contact hole 3-2, be provided with the 3rd metal level on passivation layer 3 surfaces, described the 3rd metal level is filled described the first contact hole 3-1 and the second contact hole 3-2, described the 3rd metal level is transparent metal layer, makes material and is preferably tin indium oxide.Pixel electrode and be arranged on the 3rd metal level along the connecting electrode line L of first direction, and pixel electrode is separately positioned in six inferior pixel regions accordingly, be respectively P11, P12, P13, P14, P15 and P16, pixel electrode is electrically connected to drain electrode by the second contact hole 3-2, connecting electrode line L is electrically connected to common line by the first contact hole 3-1, and makes two common line C11 and C12 conducting on first direction.
Need to prove, described first direction is perpendicular to described second direction, and can be as the case may be the orientation of first direction and second direction be adjusted accordingly.In addition, the structure that is consisted of by two main pixel regions described in the present embodiment, it is only a minimum repetitive in thin-film transistor LCD device array substrate provided by the present invention, each main pixel region comprises three time pixel regions (preferred a kind of red time pixel region, green time pixel region and blue sub-pixels district of being combined as), namely a minimum repetitive comprises pixel region six times, and described thin-film transistor LCD device array substrate also comprises a plurality of similar so minimum repetitives.
Can be found out by such scheme, common line is by the conducting on first direction of connecting electrode line, form pattern in parallel in the viewing area, it is netted common line structure, the overall resistance of common line has reduced, and then reduced corresponding signal through the time delay of described common line, therefore, the incidence of the flicker of this thin-film transistor LCD device array substrate and the bad phenomenon such as crosstalk has also reduced.
In addition, each common line forms the common line of annular not closedly around each time pixel region in its corresponding main pixel region, has increased memory capacitance, and the aperture opening ratio of device has also improved accordingly.
Embodiment two:
The present embodiment discloses a kind of method for making corresponding with the described thin-film transistor LCD device array substrate of above-described embodiment, and as Fig. 2-shown in Figure 6, the method comprises:
Concrete, described substrate is glass substrate or the substrate of other materials.
Forming gate line on described substrate surface specifically comprises:
Adopt the plasma sputtering mode to form the first metal layer on described substrate surface, namely at first described substrate is put into reaction chamber, energetic particle hits has highly purified target material solid plate, by the physical process knock-on atom, these are passed vacuum by knocking-on atom, be deposited at last substrate surface, obtain the first metal layer.But the formation of the first metal layer is not limited in the plasma sputtering mode, can also utilize other physical vapor deposition mode to form, and is not described in detail at this.And then the first metal layer is carried out photoetching, i.e. spin coating photoresist on described the first metal layer, form photoresist layer, the mask that utilization has gate line pattern exposes, and forms gate line pattern on photoresist layer, after developing, form the gate line figure on photoresist layer, take photoresist layer with gate line figure as mask, obtain gate line through techniques such as dry etching or wet etchings, described gate line is provided with grid.
Structure after completing as shown in Figure 3, wherein Fig. 3 is vertical view, shown in figure, on substrate 1, gate lines G 11 and G12 were arranged on described substrate 1 surface along first direction, the outshot of gate lines G 11 and G12 was grid.
Need to prove, " gate line pattern " described in the present embodiment is the gate line pattern in the lip-deep two dimension of photoresist layer, and area of the pattern is only limited to the photoresist layer surface and not to surperficial downward-extension, does not have three-dimensional shape; Described " gate line figure " for to have the three-dimensional picture of three-dimensional shape, the thickness of this figure is the thickness of photoresist layer.
Concrete, adopt the chemical vapor deposition mode to form gate insulator on described gate line and substrate surface, the substrate that namely at first the surface is provided with gate line is put into reaction chamber, gas precursors is transferred to substrate surface and carries out suction-operated and reaction, then the accessory substance with reaction removes, and obtains gate insulator.But the formation of gate insulator is not limited in the chemical vapor deposition mode, can also utilize other the modes such as physical vapor deposition to form, and is not described in detail at this.Described gate insulator is the SiNx layer, and forms amorphous silicon layer by identical technique on the gate insulator surface, and amorphous silicon layer is carried out photoetching, forms the TFT channel structure in the position corresponding with grid.
Structure after completing as shown in Figure 4, wherein Fig. 4-a is vertical view, not shown gate insulator, as shown in the figure, substrate 1 is arranged on the lip-deep gate lines G 11 of substrate 1 and G12, is arranged on the TFT channel structure 2-1 on the gate surface of gate line; Fig. 4-b is the sectional view along B-B ' line, and shown in figure, substrate 1 covers the lip-deep gate insulator 2 of described substrate 1.
structure after completing as shown in Figure 5, wherein Fig. 5-a is vertical view, shown in figure, the data line D11 that arranges along second direction, D12 and D13 include this tagma, source electrode and drain electrode (not shown), described this tagma and source electrode are structure as a whole, and described source electrode separates setting, described source electrode with drain electrode, drain electrode and above-mentioned TFT channel structure 2-1, grid has consisted of the TFT on the thin-film transistor LCD device array substrate, i.e. T11 together, T12, T13, T14, T15 and T16, three data line D11, D12, D13 and two gate lines G 11, G12 has consisted of two main pixel regions and two six pixel regions that main pixel region is included, and two main pixel regions are arranged along first direction, and three pixel regions in each main pixel region are arranged along second direction, two common line C11, C12 corresponds respectively to two main pixel regions, passes through the metal conduction of the second metal level on second direction, and each common line is not closedly around each time pixel region in its corresponding main pixel region, Fig. 5-b is the sectional view along C-C ' line, and shown in figure, substrate 1 covers the lip-deep gate insulator 2 of substrate 1, is arranged on the lip-deep common line C11 of gate insulator 2, C12 and data line D12.
Step 4, form passivation layer on described data line, common line and gate insulator surface, described passivation layer is carried out etching, form the first contact hole and the second contact hole.
Concrete, adopt chemical vapor deposition method to form passivation layer on described data line, common line and gate insulator surface, afterwards, adopt photoetching process to form the first contact hole and the second contact hole in described passivation layer, described the first contact hole is positioned at the passivation layer of common line top, and described the second contact hole is positioned at the passivation layer of drain electrode top.
Structure after completing as shown in Figure 6, wherein, Fig. 6-a is vertical view, the first contact hole 3-1 is positioned at the passivation layer of common line C11, C12 top, described the second contact hole 3-2 is positioned at the passivation layer of drain electrode top; Fig. 6-b is the sectional view along D-D ' line, shown in figure, substrate 1, cover the lip-deep gate insulator 2 of substrate 1, be arranged on the lip-deep common line C11 of gate insulator 2, C12 and data line D12, cover the lip-deep passivation layer 3 of common line C11, C12 and data line D12 and gate insulator 2, be arranged in passivation layer 3 and first contact hole 3-1 corresponding to common line C11, C12.
Step 5, form the 3rd metal level on described passivation layer surface, described the 3rd metal level is carried out etching, form pixel electrode and connecting electrode line.
Concrete, adopt physical vapor deposition process to form the 3rd metal level on described passivation layer surface, described the 3rd metal level is transparent metal layer, makes material and is preferably tin indium oxide, afterwards, adopt photoetching process to form pixel electrode and connecting electrode line on the 3rd metal level.
structure after completing as shown in Figure 2, wherein, Fig. 2-a is vertical view, connecting electrode line L along first direction is electrically connected to common line C11, C12 by the first contact hole 3-1, and make two common line conductings on first direction, pixel electrode is separately positioned in six inferior pixel regions accordingly, is respectively P11, P12, P13, P14, P15 and P16, and pixel electrode is electrically connected to drain electrode by the second contact hole 3-2, Fig. 2-b is the sectional view along A-A ' line, shown in figure, substrate 1, cover the lip-deep gate insulator 2 of substrate 1, be arranged on the lip-deep common line C11 of gate insulator 2, C12 and data line D12, cover common line C11, the lip-deep passivation layer 3 of C12 and data line D12 and gate insulator 2, be arranged in passivation layer 3 and with common line C11, corresponding the first contact hole 3-1 of C12, be arranged on the lip-deep connecting electrode line of passivation layer 3 L, and connecting electrode line L is by the first contact hole 3-1 and common line C11, C12 is electrically connected to, and make two common line conductings on first direction.
Can be found out by such scheme, the present embodiment has been made the first contact hole in passivation layer, and make the connecting electrode line, common line is electrically connected to by the first contact hole with the connecting electrode line, so common line conducting on first direction in the viewing area, form pattern in parallel, it is netted common line structure, the overall resistance of common line has reduced, and then reduced corresponding signal through time delay of described common line, therefore, the incidence of the flicker of this thin-film transistor LCD device array substrate and the bad phenomenon such as crosstalk has also reduced.
In addition, each common line forms the common line of annular not closedly around each time pixel region in its corresponding main pixel region, has increased memory capacitance, and the aperture opening ratio of device has also improved accordingly.
In this instructions, various piece adopts the mode of going forward one by one to describe, and what each part stressed is and the difference of other parts that between various piece, identical similar part is mutually referring to getting final product.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can be in the situation that do not break away from the spirit or scope of the present invention, realization in other embodiments.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (8)
1. a thin-film transistor LCD device array substrate, is characterized in that, comprising:
Along two adjacent main pixel regions of first direction, wherein, each main pixel region comprises respectively three along the adjacent inferior pixel region of second direction;
Article two, gate line, described two gate lines are arranged on the first metal layer along first direction;
Article two, common line, described two common lines correspond respectively to two main pixel regions, and are arranged on the second metal level;
Article three, data line, described three data lines are arranged on the second metal level along second direction;
The connecting electrode line, described connecting electrode line is arranged on the 3rd metal level, and on first direction the described two common lines of conducting.
2. array base palte according to claim 1, it is characterized in that, comprise passivation layer between described the second metal level and the 3rd metal level, the position that described passivation layer is positioned at above common line is provided with the first contact hole, and described common line and connecting electrode line are electrically connected to by the first contact hole.
3. array base palte according to claim 1, is characterized in that, described two common lines are not all not closedly around each time pixel region in its corresponding main pixel region.
4. array base palte according to claim 1, is characterized in that, described the 3rd metal level is transparent metal layer.
5. array base palte according to claim 1, is characterized in that, described first direction is perpendicular to described second direction.
6. array base palte according to claim 2, is characterized in that, described data line comprises:
This tagma of data line, source electrode and drain electrode;
This tagma of described data line and source electrode are an one-piece construction;
Described source electrode separates with drain electrode.
7. array base palte according to claim 6, is characterized in that, is provided with pixel electrode in described the 3rd metal level.
8. array base palte according to claim 7, is characterized in that, the position that described passivation layer is positioned at the drain electrode top is provided with the second contact hole, and described drain electrode is electrically connected to by described the second contact hole with pixel electrode.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104216183A (en) * | 2014-08-28 | 2014-12-17 | 合肥鑫晟光电科技有限公司 | Array substrate and preparation method thereof as well as display device |
| WO2021227109A1 (en) * | 2020-05-12 | 2021-11-18 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel |
| CN114627831A (en) * | 2022-02-17 | 2022-06-14 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and display panel |
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| US20050041006A1 (en) * | 2003-08-21 | 2005-02-24 | Lee Jae Kyun | Liquid crystal display apparatus and driving method thereof |
| CN101196659A (en) * | 2006-12-05 | 2008-06-11 | 瀚宇彩晶股份有限公司 | Liquid crystal display and method of manufacturing the same |
| CN101364020A (en) * | 2008-09-17 | 2009-02-11 | 友达光电股份有限公司 | Display panel and its pixel structure |
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| CN104216183A (en) * | 2014-08-28 | 2014-12-17 | 合肥鑫晟光电科技有限公司 | Array substrate and preparation method thereof as well as display device |
| US9865623B2 (en) | 2014-08-28 | 2018-01-09 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, and display device |
| WO2021227109A1 (en) * | 2020-05-12 | 2021-11-18 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel |
| CN114627831A (en) * | 2022-02-17 | 2022-06-14 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and display panel |
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