CN103107776A - Ultralow power consumption band-pass frequency detector and frequency discrimination method of the ultralow power consumption band-pass frequency detector - Google Patents
Ultralow power consumption band-pass frequency detector and frequency discrimination method of the ultralow power consumption band-pass frequency detector Download PDFInfo
- Publication number
- CN103107776A CN103107776A CN2011103585672A CN201110358567A CN103107776A CN 103107776 A CN103107776 A CN 103107776A CN 2011103585672 A CN2011103585672 A CN 2011103585672A CN 201110358567 A CN201110358567 A CN 201110358567A CN 103107776 A CN103107776 A CN 103107776A
- Authority
- CN
- China
- Prior art keywords
- rising edge
- frequency
- output
- signal
- state machine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012850 discrimination method Methods 0.000 title claims abstract description 20
- 230000000630 rising effect Effects 0.000 claims abstract description 186
- 238000001514 detection method Methods 0.000 claims abstract description 16
- 238000001914 filtration Methods 0.000 claims abstract description 14
- 230000006870 function Effects 0.000 claims description 17
- 230000037007 arousal Effects 0.000 claims description 11
- 230000002618 waking effect Effects 0.000 claims description 9
- 238000005096 rolling process Methods 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 7
- 230000035945 sensitivity Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 238000012546 transfer Methods 0.000 claims description 3
- 230000000284 resting effect Effects 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 238000004088 simulation Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Landscapes
- Circuits Of Receivers In General (AREA)
Abstract
The invention discloses a frequency discrimination method of the ultralow power consumption band-pass frequency detector. The frequency discrimination method of the ultralow power consumption band-pass frequency detector comprises the following steps: allocating band-pass parameter configuration characters for the band-pass frequency detector; starting detection and counting for input signals; recounting by resetting as abnormal signals are detected, filtering and removing the interference out of board and the noise in board; comparing tested rising edge counting values of normal signals with clock counting values and corresponding arranging values, in the arranging clock period, satisfying parameter arranging value range, producing high level enabled signals, allowing the input signals to output by an enabled strobing gate and achieving a wakening function. The ultralow power consumption band-pass frequency detector comprises a digital frequency comparator and a state machine, wherein the digital frequency comparator allocates the band-pass parameter values through the state machine, based on the input signals detecting values and the clock counting values, compared with the corresponding configuration values, so that the enabled signals are produced, the interference out of board and the noise in board are filtered and removed, and the input signals are judged and strobed. As a wakening receiver, the ultralow power consumption band-pass frequency detector is widely applied in the Internet of things and a wireless sensor network.
Description
Technical field
The invention belongs to radio communication and CMOS integrated circuit (IC) design field, particularly low-power consumption frequency discriminator field is specially a kind of logical frequency discriminator of band and method of super low-power consumption.
Background technology
Wireless communication receiver is in the receiver structure of present main flow, all to take the down-conversion scheme, radiofrequency signal is after low noise amplifier amplifies, deliver to frequency mixer together with local oscillation signal, carry out lower mixing, obtain Low Medium Frequency or zero intermediate frequency signals, after passing through complex filter again, suppress image signal, then after controlling through automatic gain, export to baseband processor through A/D.This scheme receiving sensitivity is good, and signal to noise ratio is high, suppress mirror image and disturb by force, but this structure needs frequency synthesizer that local oscillation signal is provided, and does not wait more than the applicable cases circuit power consumption is from 10mA to 100mA, has the large defective of circuit power consumption.
In using very widely Internet of Things or wireless sense network, a lot of nodes or equipment are all by powered battery, battery need to be kept equipment service time of 5 ~ 10 years, in the application of this super low-power consumption, need the assurance equipment most of the time to close, only when being waken up, main circuit is just opened and is carried out transceiving data, other the time only wake receiver up and work always.Adopt the function of waking receiver up of awakening technology similar with common receiver, from the radio frequency signal of several GHz, demodulate modulation signal or data, judge whether to comprise wake-up signal, be used for determining whether to open main circuit, carry out data transmit-receive work.Wake receiver up and have characteristics of energy saving, but but very harsh to the power consumption requirement that wakes receiver up, circuit power consumption should be below 10uA.Obviously, adopt the wireless communication receiver of top down-conversion scheme can not satisfy the super low-power consumption requirement that employing wakes receiver up at all.
Summary of the invention
An object of the present invention is to provide a kind of logical frequency discrimination method of band of super low-power consumption, lead to the frequency discrimination condition take the frequency discrimination parameter configuration value that arranges for the band to supplied with digital signal, compare by condition, generation wakes enable signal up, control the output supplied with digital signal, otherwise close the output supplied with digital signal, realize waking up the Energy Saving Control of receiver, reach the purpose of super low-power consumption.Another purpose is the logical frequency discriminator of band that discloses a kind of super low-power consumption, it comprises numerical frequency comparator and state machine, adopt the logical frequency discrimination method of band of super low-power consumption, realization wakes the arousal function of receiver up, can inhibition zone outer disturb or outside receive in band noise and due to the noise jamming of low consumption circuit itself, and satisfy the receiving sensitivity requirement, and make to receive the power consumption of function below 10uA, demodulate modulating data or signal from the GHz radio frequency signal.
Purpose and the above-mentioned technical problem of invention are to realize by following technical scheme.
A kind of band of super low-power consumption leads to frequency discriminator, and it is, the logical frequency discriminator of the band of the super low-power consumption of modular structure is called for short the logical frequency discriminator of band and comprises numerical frequency comparator and state machine; Wherein
The input of numerical frequency comparator connects the output that the previous stage radio-frequency front-end is processed comparator, and the input of one-level digital baseband processor after the output of numerical frequency comparator connects is used for gating output from the input data of previous stage output; State machine enable that control end and reseting controling end connect respectively rear one-level digital baseband processor enable control line and the control line that resets, counting and the reseting controling end of the counting of state machine and the control line linking number word frequency comparator that resets, the frequency discrimination parameter configuration end of the frequency discrimination parameter configuration line linking number word frequency comparator of state machine; The logical frequency discriminator output of band is used for one of output and wakes control signal Y up for waking control end up.
Described band leads to frequency discriminator, and it is that described numerical frequency comparator comprises rising edge detector, rising edge counter, reset unit, clock counter, comparator, parameters dispensing unit, enables storbing gate; Wherein
the input data of processing through radio-frequency front-end connect rising edge detector input, an output connect state machine of rising edge detector, this rising edge detects output and is used for making state machine enter count status, and open corresponding rising edge counter and clock counter counting, another output of rising edge detector connects the input of rising edge counter, the digital control configuration words P of the configuration end connect state machine of rising edge detector, the rising edge detector also has an output to connect the input of reset unit, the reset terminal of the output connect state machine of reset unit, be used for the non-homogeneous consecutive hours of rising edge being detected when the rising edge detector, control reset unit and export reset signal to state machine, make the state machine warm reset, the input end of clock of clock counter connects reference clock signal, the starting end of clock counter, stop holding the counting that begins with the reset terminal connect state machine, stop the control signal end counting and reset, the configuration words end connect state machine configuration words ER of parameters dispensing unit, DUP, DDN, be used for completing the parameters configuration control of the logical frequency discriminator of band, an output of parameters dispensing unit connects clock counter, be used for arranging clock counter counting preset value, another output of parameters dispensing unit connects an input of comparator, be used for arranging the comparator preset value, the output of clock counter and parameters dispensing unit parameter configuration end connect respectively two inputs of comparator, the preset value that is used for the count value of clock counter and setting is delivered to comparator and is compared, comparator output connection enables input of storbing gate, the input data also are connected to and enable another input of storbing gate, the output high potential of comparator is as enable signal, be used for control and enable storbing gate, will input data strobe output, the output of comparator simultaneously is used for the output wake-up signal also as the frequency discrimination index signal.
Described band leads to frequency discriminator, and it is that described clock counter comprises frequency divider, the frequency multiplier sum counter that is connected in series successively; Reference clock access frequency divider, frequency division are connected the ER configuration end of parameters dispensing unit with the frequency parameter control end, the beginning counting, stop counting and reset terminal, counter output connection comparator of counter controls end connect state machine; The frequency division of clock counter is connected end and connects the parameters dispensing unit with frequency parameter, the frequency division of clock counter and frequency parameter are configured by parameters dispensing unit ER configuration words, determine that reference clock carries out frequency dividing ratio and times frequency ratio of frequency division, be used for determining the frequency discrimination error precision.
Described band leads to frequency discriminator, it is that described state machine is the microprocessor that is integrated in the logical frequency discriminator sheet of band, state machine connects enable signal EN and the reset signal RES from the outer digital baseband processor of sheet, the output signal that connects simultaneously rising edge detector from the numerical frequency comparator, rising edge counter, reset unit, state machine output begin to count, stop counting and the rising edge counter of the control signal wire linking number word frequency comparator that resets and the control end of clock counter; The operating state of state machine comprises idle IDLE attitude, counting COUNTER attitude, finishes the FINISH attitude, and state machine is realized the conversion of three kinds of operating states according to the frequency discrimination work requirements.
A kind of band of super low-power consumption leads to frequency discrimination method, comprises the following steps:
(1) state machine by the logical frequency discriminator of band configures the frequency discrimination parameter;
State machine by the logical frequency discriminator of band is numerical frequency comparator arrangement frequency discrimination parameter, has the frequency discrimination parameter configuration table in the memory of state machine, state machine according to radio-frequency transmitter the frequency discrimination requirement, by the one group of frequency discrimination parameter configuration word of output of tabling look-up; When chip power or receive reset signal, one group of frequency discrimination parameter configuration word is configured to the numerical frequency comparator;
When radio frequency front end chip powers on or receive reset signal from digital baseband processor, started the frequency discrimination parameter configuration of the logical frequency discriminator of band by state machine, state machine accesses one group of frequency discrimination parameter configuration word and sends to the numerical frequency comparator from the frequency discrimination parameter configuration table by lookup table mode, complete the frequency discrimination parameter configuration of the logical frequency discriminator of band; The frequency discrimination parameter configuration table is to work out with the frequency discrimination parameter setting values of corresponding counting by the frequency discrimination demand of working frequency range scope, frequency discrimination data length and frequency discrimination error precision, one group of frequency discrimination parameter comprises reference clock counting upper limit value and lower limit value, the reference clock maximum count value of a clock cycle and rising edge counting settings;
(2) detect the rising edge of input data;
Detection, begins a rising edge counting number when the first rising edge being detected from the rising edge of the input data of radio-frequency (RF) front-end circuit, detects each rising edge of input data, and count value adds 1; Begin simultaneously reference clock signal is counted;
By the rising edge detector to its rising edge of input Data Detection from radio-frequency (RF) front-end circuit, when first rising edge being detected, the rising edge detector detects and outputs to state machine, state machine enters count status, rising edge counter and clock counter begin counting separately, the rising edge detector is realized the detection of corresponding precision according to the frequency discrimination error precision of setting to the input data, satisfy the frequency discrimination requirement of different demand radio-frequency transmitters; Detect each rising edge of input data and the input data are judged;
(3) detection is inputted each rising edge of data and the input data is judged;
Detect each rising edge of input data and the input data are judged, if the rising edge number of rising edge detector output is discontinuous, detection determines the discontinuous or duty cycle square wave of square-wave signal not to sending a count signal again, state machine resets do filtering, turns step (2) and again detects input data rising edge; Turn if not step (4);
Initial square-wave signal is discontinuous or duty cycle square wave is not right if detect, state machine is made the filtering reset processing, make the input signal that square-wave signal is discontinuous or square wave is not right, can not from being with logical phase discriminator output, realize the bandpass filtering with the noise signal in outer interference signal and band;
(4) judge whether the rising edge count value reaches settings;
The rising edge count value adds 1, and judges whether the rising edge count value reaches settings; If state machine output stops counting controling signal, the reference clock counter stops counting; Otherwise turn step (2);
Lead to the frequency discrimination parameter setting values when rising edge rolling counters forward value reaches band, the rising edge counter also stops counting.
(5) judge that the reference clock count value is whether within working frequency range upper and lower limit respective value scope;
The reference clock count value is sent comparator, with the judgement of making comparisons of corresponding frequency discrimination parameter configuration value; If within the clock cycle of setting, the reference clock count value is within working frequency range upper and lower limit respective value scope, and comparator is exported high level; Otherwise output low level is returned to step (2);
Within the clock cycle of setting, the rising edge count value does not satisfy parameter setting values, and output low level, wake receiver up and do not possess wake-up condition;
(6) the output high level enables gating and controls and realize arousal function;
By enabling the unit, comparator output level and input data are enabled to control processing, when comparator output high level, selected input data, and output wake-up signal realize arousal function; Do not export otherwise block the input data, realize disturbing and the in-band noise filtering function outside band.
The logical frequency discriminator of band can make a good job of as wake module and wake the control function up, and when carrying out not arousal function, other power consumption module of receiver is in resting state, thereby obtains the energy-saving effect of super low-power consumption.Data Modulation is to the carrier transmit of high frequency, after antenna reception, demodulate through the RF envelope wave detector and comprise noise at interior envelope signal, envelope signal is after amplifier amplifies, be converted to through comparator and contain noise at interior data-signal, through after the logical frequency discriminator frequency discrimination of band, the interference noise that the filtering band is outer is exported baseband signal and is processed to digital baseband processor again.
Described band leads to frequency discrimination method, and it is that the described state machine configuration of step (1) frequency discrimination parameter comprises following content:
1) working frequency range scope configuration; According to the concrete modulating data operating frequency of waking up, the operating frequency upper limit value and lower limit value of configuration frequency discriminator;
2) the input data length of configuration frequency discrimination; According to the data frame format that wakes modulating data up of input Digital Modulation data, the logical frequency discriminator of configuration band receives the input data length of digital modulation signals;
3) the reference clock number ER of the configuration limits of error; Under the prerequisite that does not affect receiving sensitivity, do the configuration of frequency discrimination error precision according to the error rate requirement of system;
4) configuration rising edge counting settings P; Wake up under the prerequisite of the receiver error rate in assurance, operating rate is namely received input data decision length be configured;
5) scope of configurable clock generator counting settings; According to 1) working frequency range scope configurable clock generator counting settings.
Described band leads to frequency discrimination method, and its first rising edge and each rising edge that is step (2) and (3) described detection input data comprises following Control the content:
1) the rising edge detector does not detect the rising edge of first input data, and state machine is in idle IDLE attitude;
2) the rising edge detector detects the rising edge of first input data, and output beginning detection signal, state machine are in counting COUNTER attitude;
3) the rising edge detector detects the rising edge of each input data;
A. rising edge detector output send the rising edge counter to a rising edge counting number:
B. reference clock send clock counter to a clock counting number:
4) initial square-wave signal is discontinuous or square wave is not right if the rising edge detector detects,
A. the rising edge detector is exported a signal to reset unit:
B. reset unit output reseting request signal is to state machine;
C. state machine output reset signal, control rising edge counter and clock counter zero clearing, and the rising edge detector restarts the input data are detected;
4) the frequency discrimination data length of completing configuration detects, and state machine is in and finishes the FINISH attitude.
Described band leads to frequency discrimination method, and it is that step (4) is described and judges whether rising edge rolling counters forward value reaches settings and comprise following Control the content:
1) state machine does not receive rising edge counter output count completion signal, judge rising edge rolling counters forward value＜settings, state machine continues to wait for rising edge counter output count completion signal, and the rising edge counter continues counting, and clock counter continues counting;
2) state machine receives rising edge counter output count completion signal, judges rising edge rolling counters forward value 〉=settings;
3) state machine output stops count signal, and the rising edge counter stops counting, and clock counter stops counting;
4) the clock counter count value is delivered to the judgement of making comparisons of the comparator reference clock number settings corresponding with the working frequency range upper and lower limit of setting, if count value in the working frequency range scope, is exported the high level index signal, and enables to export data; Otherwise keep the low level output index signal, and counter is resetted, restart the rising edge detector, if the rising edge counter does not reach preset value, turn step (2) and continue counting.
Described band leads to frequency discrimination method, and it is that step (5) is described and judges whether the reference clock count value comprises following content within working frequency range upper and lower limit respective value scope:
1) comparator is to the judgement of making comparisons of reference clock count value and corresponding frequency discrimination parameter configuration value;
2) if within the clock cycle of setting, the reference clock count value is within working frequency range upper and lower limit respective value scope, and comparator is output as high level;
3) within the clock cycle of setting, the rising edge count value does not satisfy parameter setting values, and within working frequency range upper and lower limit respective value scope, comparator is not output as low level to the reference clock count value, does not possess wake-up condition.
Described band leads to frequency discrimination method, and it is that the described output high level of step (6) enables gating and controls and realize that arousal function comprises following content:
1) when comparator is output as high level, enable the logical frequency discriminator gated data output of storbing gate realization band as enabling gating signal control, gated data is transferred to the digital baseband processor of next stage, and gated data once transfers;
2) simultaneously, comparator is output as high level, possesses wake-up condition, and the output wake-up signal is to receiver, and arousal function is used for realizing low-power consumption;
3) the next stage digital baseband processor receives the gated data that the logical frequency discriminator of band once transmits, and feedback is sent reset signal to frequency discriminator, begins the new frequency discrimination of once inputting data and judgement.
Substantial effect of the present invention is:
1, solved in Internet of Things or wireless sense network waking the very harsh requirement of receiver super low-power consumption up, made the power consumption of waking receiver up less than 5uA.
When 2, the input signal that receives or data being carried out the frequency discrimination judgement, can inhibition zone is outer disturb and the in-band noise signal, overcome the problem of the interference rejection variation that low-power consumption brings.
3, the logical frequency discrimination of the band of the logical frequency discriminator of super low-power consumption band and noise jamming suppress, and are conducive at utmost guarantee the performance of front stage circuits, make receiver obtain higher receiving sensitivity and the lower error rate.
4, circuit adopts standard CMOS to realize, be convenient to integrated manufacturing, cost is low, and reliability is high.
5, the logical frequency discrimination method of super low-power consumption band and frequency discriminator can be widely used in the different communication systems that require in Internet of Things and wireless sense network, provide feasible technological approaches for super low-power consumption receives.
Description of drawings
Fig. 1 a is a kind of super low-power consumption AM receiver composition frame chart with the logical frequency discriminator of band of the present invention;
Fig. 1 b another kind leads to the super low-power consumption AM receiver composition frame chart of frequency discriminator with band of the present invention:
In Fig. 1 a and Fig. 1 b :-11-reception antenna, 12-radio-frequency (RF) front-end circuit, 120-differentiator, 121-RF envelope wave detector, 122-amplifier, 123-comparator, the logical frequency discriminator of 13-band, 131-numerical frequency comparator, 132-state machine, 14-digital baseband processor.
Fig. 2 a is the forming circuit block diagram of the logical frequency discriminator of band of first embodiment of the invention;
Fig. 2 b is the forming circuit block diagram of the logical frequency discriminator of band of second embodiment of the invention;
In Fig. 2 a and Fig. 2 b :-21-numerical frequency comparator, 22-state machine, 211-rising edge detector, 212-rising edge counter, 213-reset unit, 214-clock counter, 215-comparator, 216-parameters dispensing unit, 217-enable storbing gate, EN-enable signal, RST-from the reset signal of baseband processor, ER-error precision configuration words, DUP-upper frequency limit configuration words, DDN-lower-frequency limit configuration words, P-rising edge counter configuration words, the wake-up signal of Y-frequency discrimination judgement output.
Fig. 3 is the state machine state transition diagram of the logical frequency discriminator of band of the embodiment of the present invention
In Fig. 3: 31-Idle state (IDLE), 32-counting attitude (COUNTER), 33-end attitude (FINISH)
Fig. 4 is the workflow diagram of the embodiment of the present invention.
Fig. 5 a is the simulation waveform figure of the logical frequency discriminator input of the band of embodiment of the present invention data 13KHz.
Fig. 5 b is the simulation waveform figure of the logical frequency discriminator input of the band of embodiment of the present invention data 8KHz.
Embodiment
The below is described in detail specific implementation of the present invention according to embodiment also by reference to the accompanying drawings, and technical scheme of the present invention, beneficial effect are further illustrated.
The super low-power consumption AM receiver of the present invention the 1st embodiment consists of block diagram as shown in Figure 1a, reception antenna 11 receives the modulated amplitude modulated radio frequency signal, RF envelope wave detector 12 demodulates envelope modulated signal or the data of low frequency from the amplitude modulated carrier signal, after 13 gains are amplified through amplifier, deliver to comparator 14 and be quantified as digital signal.Radio frequency and AFE (analog front end) comprise that RF envelope wave detector 12, amplifier 13 and comparator 14 all adopt the structure of super low-power consumption and circuit to realize, total power consumption is in 3uA.In the digital signal of comparator 14 outputs, also include band outer interference signal and noise, also comprise due to radio frequency and AFE (analog front end) employing ultralow Consumption, the digital noise signal through comparator 14 outputs that internal noise causes, digital signal and digital noise signal are delivered to the logical frequency discriminator 15 of band and are carried out frequency discrimination and filtering processing, the filtering band is outer to be disturbed and the digital noise signal, export to again digital baseband processor 16, in the receiving sensitivity performance that guarantees complete machine, control the receive data error rate in low scope.
The super low-power consumption FM receiver of the present invention the 2nd embodiment consists of block diagram as shown in Fig. 1 b, in order to reach the receiver of super low-power consumption, on the basis that Fig. 1 a AM receiver consists of, access one-level differentiator 10 between antenna 11 and RF envelope wave detector 12, differentiator 10 becomes modulated frequency amplitude-modulated carrier signal with the frequency-modulated carrier signal, and the reception ﹠ disposal of back receives by AM receiver.The AM receiver of the course of work of back and Fig. 1 a is similar, no longer describes in detail.
The logical frequency discriminator of the band of first embodiment of the invention consists of block diagram as shown in Fig. 2 a, and it comprises numerical frequency comparator 21 and state machine 22.What numerical frequency comparator 21 comprised rising edge detector 211, rising edge counter 212, reset unit 213, clock counter 214, comparator 215, parameters dispensing unit 216 and output data enables storbing gate 217.Input data DATA IN connects rising edge detector 211, rising edge counter 212 is given in the output of rising edge detector 211, output is simultaneously given reset unit 213 and carried out the signal judgement, state machine 22 is also given in rising edge detector 211 outputs simultaneously, as the beginning detection signal, output starts the frequency discrimination control signal to state machine with 211 first rising edges of exporting.the output of rising edge counter 212 feeds back to state machine, reset unit also will export and result is delivered to state machine, reference clock is delivered to clock counter, deliver to comparator together with the settings of its output and parameters configuration, the gating signal that enables as the output data is delivered to and is enabled storbing gate 217, input data DATA IN is connected to simultaneously and enables storbing gate 217 signal input parts, be high level when enabling gating signal, enabling storbing gate 217 outputs allows the input data pass through, enable the logical frequency discriminator output of the band data DATA OUT of storbing gate 217 outputs, the input data of the outer interference of filtering band and in-band noise.State machine 22 Enable Pins and reset terminal receive enable signal EN and the reset signal RES from digital baseband processor, state machine 22 also receives from the count completion signal of the detection signal of rising edge detector 211 outputs of numerical frequency comparator 21,212 outputs of rising edge counter, the reset signal of reset unit 213 outputs, process to received signal judgement, state machine 22 output signals comprise the control signal that begins to count and stop counting to clock counter 214, and to the reset signal with logical frequency discriminator.Comparator is output as frequency discrimination judgement output signal Y simultaneously, is used for as waking output signal up.
Be described further in conjunction with Fig. 2 a and the logical frequency discriminator technical scheme of 1 pair of band of embodiment.The digital signal of comparator 123 outputs in Fig. 1 a or Fig. 1 b, deliver to the logical frequency discriminator of band as input data DATA IN, if the rising edge detector 211 of numerical frequency comparator 21 detects first rising edge of input data, export the enabling signal of " beginning to detect " to state machine 22, state machine 22 is processed the control signal that output " begins counting ", rising edge counter 212 begins input data rising edge is counted, and clock counter 214 begins reference clock is counted simultaneously.Meanwhile, the input data are delivered to reset unit 213 and are carried out signal decision, if discontinuous signal appears in the input data, namely, the interval of pulse surpasses default scope, when the duty ratio of perhaps inputting data does not meet the demands, reset unit 213 output high level are to state machine, and state machine resets to the logical frequency discriminator of whole band, restarts the judgement of new round frequency discrimination.If the judgement input data signal is continuous, reset unit 213 output low levels, rising edge counter 212 adds 1, reset unit is made signal decision successively, if the count value of rising edge counter 212 does not arrive rising edge counter configuration words P preset value, low level is kept in reset unit 213 outputs, and rising edge counter 212 constantly adds 1.when the count value arrival rising edge counter configuration words P of rising edge counter 212 preset value, reset unit 213 output high level signals are to state machine 22, the signal that state machine 22 outputs stop counting is to clock counter 214, on the operating frequency that the clock count value that clock counter 214 is sent and parameters dispensing unit 216 are sent, two preset values that lower limit is corresponding, delivering to together comparator 215 compares, as count value in two preset value scopes, export the frequency discrimination decision signal Y of high level, Y delivers to as enable signal and enables control gate 217 inputs, control enables storbing gate 217 gating output data DATA OUT and delivers to baseband processor, if count value is not in the preset value scope, counter resets, frequency discriminator begins again to adjudicate.The parameters dispensing unit 216 of the embodiment of the present invention is according to error precision, the operating rate of working frequency range scope, frequency discrimination, by state machine to the frequency discrimination parameter: error precision configuration words ER, lower-frequency limit configuration words DUP, upper frequency limit configuration words DDN and rising edge count limit configuration words P are configured.
For ease of the description to the embodiment course of work, suppose that the frequency discrimination parameter configuration is as follows: the reference clock of input is 20KHz and is configured to 80KHz through 4 frequencys multiplication; The bandpass characteristics of the logical frequency discriminator of band is between 8 ~ 22KHz, and is adjustable by the working frequency range scope; Operating rate is adjustable between the rising edge of 4 ~ 15 input data, and the error precision configuration words is adjustable between 3 ~ 8 reference clock numbers.22 pairs of frequency discrimination parameter configuration of state machine are that the performance requirement according to receiver arranges, and provide error precision configuration words ER by tabling look-up, upper frequency limit configuration words DUP, upper frequency limit configuration words DDN and rising edge counter configuration words P.
Table 1 is speed and the bandpass characteristics allocation list of frequency discrimination.As shown in table 1, the left side first row band passband rate F of table, the band passband rate of expression frequency discrimination, and top the first row C represents rising edge counting settings.Provide the reference clock counting settings under the logical frequency values of different frequency discrimination bands and different rising edge counting settings in table 1, the clock count settings are corresponding with frequency discrimination speed, therefrom as seen.take the band passband rate scope of frequency discriminator as 13 ~ 15kHz as example, if selecting rising edge counting settings P is 6, the reference clock counting settings of the reference clock 80kHz that the lower frequency limit 13kHz of frequency discriminator is corresponding are 31, and reference clock counting settings corresponding to upper limiting frequency 15kHz are 27, when 212 pairs of input data rising edge count values of rising edge counter reach 6, clock counter 214 stops counting, if deliver to the reference clock count value of comparator 215 in 27 ~ 31 scopes, comparator 215 is exported high level, the logical frequency discriminator output of band wakes control signal Y up, open the transmission circuit on receiver, enabling simultaneously storbing gate 217 opens, the output of input data, otherwise, the comparator output low level, enabling storbing gate 217 closes, the input data are not exported, from the input data filtering data of the outer interference of band and in-band noise, the logical frequency discriminator of band is not exported and is waken control signal up simultaneously, close the transmission circuit on receiver, realize energy-conservation low-power consumption.
The continuity judgment condition allocation list that table 2 resets.As shown in table 2, the first row Fmin is expressed as the lower frequency limit value of the logical frequency discriminator configuration of band, and the 2nd row Cs is expressed as the reference clock numerical value that in the clock cycle, error allows, it is determined by the error precision configuration words, the reference clock maximum number value of permissible error when namely in the clock cycle, one group of continuous data is inputted.Reset unit 213 is mainly that continuity and the duty ratio of input data are added up and adjudicated, and the continuity of the rising edge number of 213 pairs of rising edge detectors of reset unit, 211 outputs is adjudicated.According to table 1 and table 2 explanation frequency discrimination parameter configuration value and judgement relation.Within a clock cycle (take institute's configuration frequency lower limit as the clock cycle), when clock counter 214 count down to the longest counting number 31 corresponding to operating frequency lower limit, when the rising edge detector did not also detect rising edge, the data that show input were discontinuous, just sent reset signal.
High level and the low level number of the input data that 212 pairs of rising edge detectors 211 of reset unit are sent are added up and judge, if within a clock cycle, and the poor limit value that surpasses of the number of high and low level, the duty ratio of interior input of clock cycle data does not meet the demands for this reason, reset unit 212 output reset signals.By shown in table 2, the reference clock maximum number value of the permissible error that lower frequency limit 13kHz is corresponding is 6, if the continuity of the rising edge number of 213 pairs of rising edge detectors of reset unit, 211 outputs is adjudicated, exceed 6 if the number of high and low level is poor, export reset signal.
Within a clock cycle, the rising edge counter does not reach rising edge counting settings, resets the zero clearing of current rising edge count value.
Table 1
Table 2
The logical frequency discriminator of the band of the present invention the 2nd embodiment consists of block diagram as shown in Fig. 2 b, consists of with the logical frequency discriminator of band of the first embodiment and compares, and omits reset unit, omits to rising edge counter configuration count value P.The course of work of the logical frequency discriminator of the band of two embodiment and the logical frequency discriminator of the band of the first embodiment are basic identical, difference is: rising edge detector 211 outputs will detect output and send state machine 22 and rising edge counter 212, rising edge counter 212 output rising edge count values are given state machine 22, state machine 22 is done whether identical judgement with rising edge count value and configuration count value P, if judgement is "Yes", state machine 22 " stops counting " signal for rising edge counter 212 and clock counter 214 outputs, otherwise continues counting.State machine 22 begin the counting, stop the counting and reset signal, deliver to respectively rising edge counter 212 and clock counter 214.
Fig. 2 b is the 2nd embodiment of the logical frequency discriminator of low-power consumption band, rising edge detector 211 is exported and is all directly to be connected to state machine from resetting of baseband processor, realize the warm reset processing, the rising edge counter is except detection upper body edge, simultaneously also to inputting the high level part-pulse duration of data, the time of low level part is added up respectively, when the time that high and low level partly counts surpasses preset value, state machine is resetted, remaining realizes with the 1st embodiment basic identical, no longer describes in detail.
The state machine state of the embodiment of the present invention is changed schematic diagram as shown in Figure 3, and state machine has three kinds of states: idle (IDLE) attitude 31, counting (COUNTER) attitude 32 and end (Finish) attitude 33.
The state machine beginning is in IDLE attitude 31, when the rising edge detector detects first rising edge of input data, state machine receives rising edge detector output beginning detection signal, change counting COUNTER attitude 32 over to, if state machine is according to the output signal of reset unit, the requirement that resets is not satisfied in judgement, and when the input data are arranged, remains on COUNTER attitude 32.
When reset unit satisfies when resetting requirement and the rising edge of next input data being detected, restart counting, when counting reached preset value, state machine entered Finish attitude 33.
If state machine is according to the request of the reset unit output QRES signal that resets, the requirement that resets is satisfied in judgement, and when not inputting data, state machine initiatively changes IDLE attitude 31 over to from COUNTER attitude 32.
When state machine receives digital base band processor chip reset signal RES, also change IDLE attitude 31 over to by Finish attitude 33.
Adopt that the logical frequency discrimination method of band of a kind of super low-power consumption of the present invention implements the logical frequency discriminator of band, its course of work in conjunction with Fig. 2, is described below the workflow of embodiment frequency discriminator as shown in Fig. 4 flow process:
(1) S401 is when chip power or when RSE reset signal from digital baseband processor is arranged, and the state machine that is in the IDLE attitude enters (2);
(2) the S402 state machine is to configuring the frequency discrimination parameter with logical frequency discriminator: according to the requirement of operation of receiver band limits, operating rate, frequency discrimination error precision, comprise operating frequency upper and lower limit settings DUP and DDN by the configuration parameter of tabling look-up, rising edge counting settings P, reference clock counting settings T and error precision settings ER;
(3) S403 detects the rising edge of input data, if input data rising edge detected, turns (4); If input data rising edge do not detected, continue to detect the rising edge of input data;
(4) S404 is when first rising edge of input data being detected, and state machine changes COUNTER attitude 32 over to from IDLE attitude 31, controls rising edge counter and clock counter and begins separately counting, carries out simultaneously (5);
(5) S405 detects the continuity of the square-wave signal of inputting data or the duty ratio of square wave, if the duty ratio of the continuity of square-wave signal or square wave is undesirable, turns (6); If the duty ratio of the continuity of square-wave signal or square wave meets the requirements, turn (7);
(6) the S406 reset unit is exported reseting request signal to state machine, skips to S403;
(7) if the inspection of S407 reset unit is normal, the rising edge counter adds 1, and enters (8);
(8) S408 judges whether the rising edge rolling counters forward reaches preset value, completes the calculating signal if reach preset value to one of state machine, enters (9); If the rising edge counter does not reach preset value, skip to (13) S413;
(9) S409 state machine control clock counter stops counting, and count value is delivered to comparator, enters (10);
(10) the S410 comparator compares clock counter count value and the frequency band upper limit value and lower limit value of presetting, if in the frequency band upper limit value and lower limit value, turn (12); Otherwise keep the low level output index signal, turn (11);
(11) S411 resets counter, and skips to S403;
(12) S412 frequency discrimination indication output high level;
(13) S413 enables to export data, and when enabling to export data to digital baseband processor, a data transfer is complete, and digital baseband processor output RES reset signal gives band logical frequency discriminator, jumps to (1), and beginning is newly once inputted the logical frequency discrimination of band of data and processed;
(14) S414 frequency discrimination output high level is as the wake-up signal Y of the logical frequency discriminator output of band.
Fig. 5 a and Fig. 5 b provide the simulation waveform figure of embodiment of the present invention input data 13KHz and the simulation waveform figure of embodiment of the present invention input data 8KHz.The frequency discrimination scope that the embodiment of the present invention arranges the logical frequency discriminator of band is 10 ~ 20KHz, and the settings P of statistics rising edge number is 7, and clock signal is 20KHz, through 4 frequencys multiplication to the reference clock of 80KHz as clock counter.13KHz and the 8KHz input data of delivering to the logical frequency discriminator of band have been carried out frequency discrimination emulation, and its simulation result is as shown in Fig. 5 a and Fig. 5 b.In Fig. 5 a and Fig. 5 b, the reference clock of the signal indication 80KHz that goes up most, Fin represents to input the signal of data, and in Fig. 5 a, the input data are 13KHz, and in Fig. 5 b, the input data are 8KHz.Y represents the frequency discrimination court verdict of frequency discriminator, and court verdict is high level, and the input data are strobed output, export simultaneously wake-up signal, wake receiver chip up.Court verdict is that low level is not gatings of input data, does not export wake-up signal, continues judgement.RST represents the reset signal from base band.By Fig. 5 a as can be known, because the logical frequency-selecting scope of the band of frequency discriminator is 10 ~ 20kHz, therefore wake output enable signal-Y up, export high level after the rising edge of statistics 7 input data; After circuit received reset signal, circuit reset Y also became low level, and when condition satisfied again, after 7 input data rising edges, Y is the output enable signal again.In Fig. 5 b, due to the data of input not in the logical frequency-selecting scope of band, therefore Y is low level always.
Protection scope of the present invention is not limited to embodiments described herein.As long as various variations claims limit and the spirit and scope of the present invention determined in, these variations are apparent, all utilize example that the present invention conceives all at the row of protection.
Claims (10)
1. the logical frequency discriminator of the band of a super low-power consumption, is characterized in that, the logical frequency discriminator of the band of the super low-power consumption of modular structure is called for short the logical frequency discriminator of band and comprises numerical frequency comparator and state machine; Wherein
The input of numerical frequency comparator connects the previous stage output, and the input of one-level digital baseband processor after the output of numerical frequency comparator connects is used for gating output from the input data of previous stage output; State machine enable that control end and reseting controling end connect respectively rear one-level digital baseband processor enable control line and the control line that resets, counting and the reseting controling end of the counting of state machine and the control line linking number word frequency comparator that resets, the frequency discrimination parameter configuration end of the frequency discrimination parameter configuration line linking number word frequency comparator of state machine; The logical frequency discriminator output of band is used for one of output and wakes control signal Y up for waking control end up.
2. the logical frequency discriminator of band as claimed in claim 1, is characterized in that, described numerical frequency comparator comprises rising edge detector, rising edge counter, reset unit, clock counter, comparator, parameters dispensing unit, enables storbing gate; Wherein
the input data connect rising edge detector input, an output connect state machine of rising edge detector, this rising edge detects output and is used for making state machine enter count status, and open corresponding rising edge counter and clock counter counting, another output of rising edge detector connects the input of rising edge counter, the digital control configuration words P of the configuration end connect state machine of rising edge detector, the rising edge detector also has an output to connect the input of reset unit, the reset terminal of the output connect state machine of reset unit, the input end of clock of clock counter connects reference clock signal, the starting end of clock counter, stop holding the counting that begins with the reset terminal connect state machine, stop the control signal end counting and reset, the configuration words end connect state machine configuration words ER of parameters dispensing unit, DUP, DDN, be used for completing the parameters configuration control of the logical frequency discriminator of band, an output of parameters dispensing unit connects clock counter, be used for arranging clock counter counting preset value, another output of parameters dispensing unit connects an input of comparator, be used for arranging the preset value of comparator, the output of clock counter and parameters dispensing unit parameter configuration end connect respectively two inputs of comparator, the preset value that is used for the count value of clock counter and setting is delivered to comparator and is compared, comparator output connection enables input of storbing gate, the input data also are connected to and enable another input of storbing gate, the output high potential of comparator is as enable signal, be used for control and enable storbing gate, will input data strobe output, the output of comparator simultaneously is used for the output wake-up signal also as the frequency discrimination index signal.
3. band as claimed in claim 2 leads to frequency discriminator, and it is characterized in that: described clock counter comprises frequency divider, the frequency multiplier sum counter that is connected in series successively; Reference clock access frequency divider, frequency division are connected the ER configuration end of parameters dispensing unit with the frequency parameter control end, the beginning counting, stop counting and reset terminal, counter output connection comparator of counter controls end connect state machine; The frequency division of clock counter is connected end and connects the parameters dispensing unit with frequency parameter, the frequency division of clock counter and frequency parameter are configured by parameters dispensing unit ER configuration words, determine that reference clock carries out frequency dividing ratio and times frequency ratio of frequency division, be used for determining the frequency discrimination error precision.
4. band as described in claim 1-3 leads to frequency discriminator, it is characterized in that: described state machine is the microprocessor that is integrated in the logical frequency discriminator sheet of band, state machine connects enable signal EN and the reset signal RES from the outer digital baseband processor of sheet, the output signal that connects simultaneously rising edge detector from the numerical frequency comparator, rising edge counter, reset unit, state machine output begin to count, stop counting and the rising edge counter of the control signal wire linking number word frequency comparator that resets and the control end of clock counter; The operating state of state machine comprises idle IDLE attitude, counting COUNTER attitude, finishes the FINISH attitude, and state machine is realized the conversion of three kinds of operating states according to the frequency discrimination work requirements.
5. the band of a super low-power consumption leads to frequency discrimination method, comprises the following steps:
(1) state machine by the logical frequency discriminator of band configures the frequency discrimination parameter;
State machine by the logical frequency discriminator of band is numerical frequency comparator arrangement frequency discrimination parameter, has the frequency discrimination parameter configuration table in the memory of state machine, state machine according to radio-frequency transmitter the frequency discrimination requirement, by the one group of frequency discrimination parameter configuration word of output of tabling look-up; When chip power or receive reset signal, one group of frequency discrimination parameter configuration word is configured to the numerical frequency comparator;
(2) detect the rising edge of input data;
Detection, begins a rising edge counting number when the first rising edge being detected from the rising edge of the input data of radio-frequency (RF) front-end circuit, detects each rising edge of input data, and count value adds 1; Begin simultaneously reference clock signal is counted;
(3) detection is inputted each rising edge of data and the input data is judged;
Detect each rising edge of input data and the input data are judged, if the rising edge number of rising edge detector output is discontinuous, detection determines the discontinuous or duty cycle square wave of square-wave signal not to sending a count signal again, state machine resets do filtering, turns step (2) and again detects input data rising edge; Turn if not step (4);
Initial square-wave signal is discontinuous or duty cycle square wave is not right if detect, state machine is made the filtering reset processing, make the input signal that square-wave signal is discontinuous or square wave is not right, can not from being with logical phase discriminator output, realize the bandpass filtering with the noise signal in outer interference signal and band;
(4) judge whether the rising edge count value reaches settings;
The rising edge count value adds 1, and judges whether the rising edge count value reaches settings; If state machine output stops counting controling signal, the reference clock counter stops counting; Otherwise turn step (2);
(5) judge that the reference clock count value is whether within working frequency range upper and lower limit respective value scope;
The reference clock count value is sent comparator, with the judgement of making comparisons of corresponding frequency discrimination parameter configuration value; If within the clock cycle of setting, the reference clock count value is within working frequency range upper and lower limit respective value scope, and comparator is exported high level; Otherwise output low level is returned to step (2);
Within the clock cycle of setting, the rising edge count value does not satisfy parameter setting values, and output low level, wake receiver up and do not possess wake-up condition;
(6) the output high level enables gating and controls and realize arousal function;
By enabling the unit, comparator output level and input data are enabled to control processing, when comparator output high level, selected input data, and output wake-up signal realize arousal function; Do not export otherwise block the input data, realize disturbing and the in-band noise filtering function outside band;
The logical frequency discriminator of band can make a good job of as wake module and wake the control function up, and when carrying out not arousal function, other power consumption module of receiver is in resting state, is used for obtaining super low-power consumption.
6. the logical frequency discrimination method of band as claimed in claim 5, is characterized in that, the described state machine configuration of step (1) frequency discrimination parameter comprises following content:
1) working frequency range scope configuration; According to the concrete modulating data operating frequency of waking up, the operating frequency upper limit value and lower limit value of configuration frequency discriminator;
2) the input data length of configuration frequency discrimination; According to the data frame format that wakes modulating data up of input Digital Modulation data, the logical frequency discriminator of configuration band receives the input data length of digital modulation signals;
3) the reference clock number ER of the configuration limits of error; Under the prerequisite that does not affect receiving sensitivity, do the configuration of frequency discrimination error precision according to the error rate requirement of system;
4) configuration rising edge counting settings P; Wake up under the prerequisite of the receiver error rate in assurance, operating rate is namely received input data decision length be configured;
5) scope of configurable clock generator counting settings; According to 1) working frequency range scope configurable clock generator counting settings.
7. the logical frequency discrimination method of band as claimed in claim 5, is characterized in that, the first rising edge and each rising edge of the described detection input in step (2) and (3) data comprise following Control the content:
1) the rising edge detector does not detect the rising edge of first input data, and state machine is in idle IDLE attitude; Counting COUNTER attitude, end FINISH attitude;
2) the rising edge detector detects the rising edge of first input data, output beginning count signal;
3) the rising edge detector detects the rising edge of each input data;
A. rising edge detector output send the rising edge counter to a rising edge counting number:
B. reference clock send clock counter to a clock counting number:
4) initial square-wave signal is discontinuous or square wave is not right if the rising edge detector detects,
A. the rising edge detector is exported a signal to reset unit:
B. reset unit output reseting request signal is to state machine;
C. state machine output reset signal, control rising edge counter and clock counter zero clearing, and the rising edge detector restarts the input data are detected.
8. the logical frequency discrimination method of band as claimed in claim 5, is characterized in that, step (4) is described judges whether rising edge rolling counters forward value reaches settings and comprise following Control the content:
1) state machine does not receive rising edge counter output count completion signal, judge rising edge rolling counters forward value＜settings, state machine continues to wait for rising edge counter output count completion signal, and the rising edge counter continues counting, and clock counter continues counting;
2) state machine receives rising edge counter output count completion signal, judges rising edge rolling counters forward value 〉=settings;
3) state machine output stops count signal, and the rising edge counter stops counting, and clock counter stops counting;
4) the clock counter count value is delivered to the judgement of making comparisons of the comparator reference clock number settings corresponding with the working frequency range upper and lower limit of setting, if count value in the working frequency range scope, is exported the high level index signal, and enables to export data; Otherwise keep the low level output index signal, and counter is resetted, restart the rising edge detector, if the rising edge counter does not reach preset value, turn step (2) and continue counting.
9. the logical frequency discrimination method of method band as claimed in claim 5, is characterized in that, step (5) is described judges whether the reference clock count value comprises following content within working frequency range upper and lower limit respective value scope:
1) comparator is to the judgement of making comparisons of reference clock count value and corresponding frequency discrimination parameter configuration value;
2) if within the clock cycle of setting, the reference clock count value is within working frequency range upper and lower limit respective value scope, and comparator is output as high level;
3) within the clock cycle of setting, the rising edge count value does not satisfy parameter setting values, and within working frequency range upper and lower limit respective value scope, comparator is not output as low level to the reference clock count value, does not possess wake-up condition.
10. the logical frequency discrimination method of band as described in claim 5-9, is characterized in that, the described output high level of step (6) enables gating and controls and realize that arousal function comprises following content:
1) when comparator is output as high level, enable the logical frequency discriminator gated data output of storbing gate realization band as enabling gating signal control, gated data is transferred to the digital baseband processor of next stage, and gated data once transfers;
2) simultaneously, comparator is output as high level, possesses wake-up condition, and the output wake-up signal is to receiver, and arousal function is used for realizing low-power consumption;
3) the next stage digital baseband processor receives the gated data that the logical frequency discriminator of band once transmits, and feedback is sent reset signal to frequency discriminator, begins the new frequency discrimination of once inputting data and judgement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110358567.2A CN103107776B (en) | 2011-11-14 | 2011-11-14 | A kind of band of super low-power consumption leads to frequency discriminator and frequency discrimination method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110358567.2A CN103107776B (en) | 2011-11-14 | 2011-11-14 | A kind of band of super low-power consumption leads to frequency discriminator and frequency discrimination method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103107776A true CN103107776A (en) | 2013-05-15 |
| CN103107776B CN103107776B (en) | 2015-09-09 |
Family
ID=48315386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110358567.2A Active CN103107776B (en) | 2011-11-14 | 2011-11-14 | A kind of band of super low-power consumption leads to frequency discriminator and frequency discrimination method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103107776B (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217229A (en) * | 2013-06-04 | 2014-12-17 | 深圳市金溢科技股份有限公司 | High arousal sensitivity card, OBU, OBU component and communication method |
| CN105922927A (en) * | 2015-08-31 | 2016-09-07 | 陈觉明 | Object gating control method |
| CN103746781B (en) * | 2013-11-12 | 2017-02-08 | 福建星网锐捷网络有限公司 | Method and apparatus for processing response information in reception sensitivity test |
| CN107295615A (en) * | 2016-04-11 | 2017-10-24 | 黎吉春 | A kind of method of wake on wireless equipment |
| CN108173539A (en) * | 2016-12-07 | 2018-06-15 | 大唐恩智浦半导体有限公司 | A chip wake-up method and circuit |
| CN109618448A (en) * | 2018-12-11 | 2019-04-12 | 帝奥微电子有限公司 | Multi-mode LED drive circuit |
| CN109963327A (en) * | 2019-05-08 | 2019-07-02 | 北京倍胜智能科技有限公司 | A radio frequency signal wake-up method, device, electronic device and storage medium |
| CN110351648A (en) * | 2019-07-31 | 2019-10-18 | 广州笙达电器有限公司 | The detection method of signal deteching circuit and SPDIF fiber-optic signal |
| CN110545117A (en) * | 2019-09-10 | 2019-12-06 | 西安电子科技大学 | A wake-up receiver with sampling function |
| CN112039517A (en) * | 2020-09-04 | 2020-12-04 | 上海川土微电子有限公司 | Ultra-low power consumption capacitance type digital isolator circuit based on Pulse-Coding |
| CN112367065A (en) * | 2020-12-01 | 2021-02-12 | 珠海市一微半导体有限公司 | Clock regulation and control circuit and control method of I2C controller clock line |
| CN113037319A (en) * | 2016-01-14 | 2021-06-25 | 高通股份有限公司 | Apparatus and method for waking up slave circuit in system |
| CN113992222A (en) * | 2021-12-27 | 2022-01-28 | 北京百瑞互联技术有限公司 | Wake-up receiver, system, method and equipment applied to BLE |
| CN114448403A (en) * | 2020-11-05 | 2022-05-06 | 中移物联网有限公司 | Asynchronous wake-up circuit |
| CN114705943A (en) * | 2022-06-06 | 2022-07-05 | 苏州浪潮智能科技有限公司 | Signal quality detection system, method and computer equipment |
| CN115226191A (en) * | 2022-07-27 | 2022-10-21 | 深圳市元征科技股份有限公司 | Wake-up method, apparatus, device and medium |
| CN117560091A (en) * | 2024-01-02 | 2024-02-13 | 南京美辰微电子有限公司 | GPON OLT optical module burst mode receiving end noise detection circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1214489A (en) * | 1997-08-31 | 1999-04-21 | 三星电子株式会社 | Automatic wake-up device for radio automatic recognition terminal and communication method using the terminal |
| CN1416220A (en) * | 2001-10-30 | 2003-05-07 | 株式会社电装 | Comparator circuit, comparator, level sensing circuit and threshold voltage setting method |
| CN101482734A (en) * | 2009-01-22 | 2009-07-15 | 深圳市博孚机电有限公司 | Low-power consumption control circuit and its operating procedure |
| CN102082587A (en) * | 2009-12-01 | 2011-06-01 | 中兴通讯股份有限公司 | Data communication method and system of vehicle-mounted unit |
-
2011
- 2011-11-14 CN CN201110358567.2A patent/CN103107776B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1214489A (en) * | 1997-08-31 | 1999-04-21 | 三星电子株式会社 | Automatic wake-up device for radio automatic recognition terminal and communication method using the terminal |
| CN1416220A (en) * | 2001-10-30 | 2003-05-07 | 株式会社电装 | Comparator circuit, comparator, level sensing circuit and threshold voltage setting method |
| CN101482734A (en) * | 2009-01-22 | 2009-07-15 | 深圳市博孚机电有限公司 | Low-power consumption control circuit and its operating procedure |
| CN102082587A (en) * | 2009-12-01 | 2011-06-01 | 中兴通讯股份有限公司 | Data communication method and system of vehicle-mounted unit |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217229B (en) * | 2013-06-04 | 2017-06-16 | 深圳市金溢科技股份有限公司 | Height wakes up sensitivity card, OBU, OBU component and communication means |
| CN104217229A (en) * | 2013-06-04 | 2014-12-17 | 深圳市金溢科技股份有限公司 | High arousal sensitivity card, OBU, OBU component and communication method |
| CN103746781B (en) * | 2013-11-12 | 2017-02-08 | 福建星网锐捷网络有限公司 | Method and apparatus for processing response information in reception sensitivity test |
| CN105922927A (en) * | 2015-08-31 | 2016-09-07 | 陈觉明 | Object gating control method |
| CN113037319A (en) * | 2016-01-14 | 2021-06-25 | 高通股份有限公司 | Apparatus and method for waking up slave circuit in system |
| CN113037319B (en) * | 2016-01-14 | 2022-06-21 | 高通股份有限公司 | Apparatus and method for waking up slave circuit in system |
| CN107295615A (en) * | 2016-04-11 | 2017-10-24 | 黎吉春 | A kind of method of wake on wireless equipment |
| CN108173539B (en) * | 2016-12-07 | 2019-10-22 | 大唐恩智浦半导体有限公司 | A chip wake-up method and circuit |
| CN108173539A (en) * | 2016-12-07 | 2018-06-15 | 大唐恩智浦半导体有限公司 | A chip wake-up method and circuit |
| CN109618448B (en) * | 2018-12-11 | 2020-10-16 | 帝奥微电子有限公司 | Multi-mode LED drive circuit |
| CN109618448A (en) * | 2018-12-11 | 2019-04-12 | 帝奥微电子有限公司 | Multi-mode LED drive circuit |
| CN109963327A (en) * | 2019-05-08 | 2019-07-02 | 北京倍胜智能科技有限公司 | A radio frequency signal wake-up method, device, electronic device and storage medium |
| CN110351648A (en) * | 2019-07-31 | 2019-10-18 | 广州笙达电器有限公司 | The detection method of signal deteching circuit and SPDIF fiber-optic signal |
| CN110545117A (en) * | 2019-09-10 | 2019-12-06 | 西安电子科技大学 | A wake-up receiver with sampling function |
| CN110545117B (en) * | 2019-09-10 | 2021-05-04 | 西安电子科技大学 | A wake-up receiver with sampling function |
| CN112039517A (en) * | 2020-09-04 | 2020-12-04 | 上海川土微电子有限公司 | Ultra-low power consumption capacitance type digital isolator circuit based on Pulse-Coding |
| CN112039517B (en) * | 2020-09-04 | 2024-03-22 | 上海川土微电子有限公司 | Ultra-low power consumption capacitive digital isolator circuit based on Pulse-Coding |
| CN114448403A (en) * | 2020-11-05 | 2022-05-06 | 中移物联网有限公司 | Asynchronous wake-up circuit |
| CN114448403B (en) * | 2020-11-05 | 2024-07-16 | 中移物联网有限公司 | Asynchronous wake-up circuit |
| CN112367065A (en) * | 2020-12-01 | 2021-02-12 | 珠海市一微半导体有限公司 | Clock regulation and control circuit and control method of I2C controller clock line |
| CN113992222A (en) * | 2021-12-27 | 2022-01-28 | 北京百瑞互联技术有限公司 | Wake-up receiver, system, method and equipment applied to BLE |
| CN113992222B (en) * | 2021-12-27 | 2022-04-08 | 北京百瑞互联技术有限公司 | Wake-up receiver, system, method and equipment applied to BLE |
| CN114705943A (en) * | 2022-06-06 | 2022-07-05 | 苏州浪潮智能科技有限公司 | Signal quality detection system, method and computer equipment |
| CN115226191A (en) * | 2022-07-27 | 2022-10-21 | 深圳市元征科技股份有限公司 | Wake-up method, apparatus, device and medium |
| CN117560091A (en) * | 2024-01-02 | 2024-02-13 | 南京美辰微电子有限公司 | GPON OLT optical module burst mode receiving end noise detection circuit |
| CN117560091B (en) * | 2024-01-02 | 2024-03-29 | 南京美辰微电子有限公司 | GPON OLT optical module burst mode receiving end noise detection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103107776B (en) | 2015-09-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103107776B (en) | A kind of band of super low-power consumption leads to frequency discriminator and frequency discrimination method thereof | |
| US9720875B2 (en) | Receiver with signal arrival detection capability | |
| CN101404511B (en) | Energy-saving control device for wireless sensor network node circuit | |
| CN102082587B (en) | Data communication method and system of vehicle-mounted unit | |
| CN103226169B (en) | Square wave detector for wireless wake-up circuit | |
| CN204228833U (en) | A kind of based on GPS very-long-range nuclear phase detection device | |
| CN106162532B (en) | In-vehicle communication method and system with cognitive function | |
| CN105103476A (en) | A receiver, transceiver, transceiver module for a body coupled communication device, a body coupled communication system and a method of waking-up a body coupled receiver of a body coupled communication device | |
| CN101425218A (en) | Intelligent telemetering water meter based on wireless sensor network | |
| WO2024046417A1 (en) | Mode determination method, device, and storage medium | |
| CN103927790A (en) | Method of awakening vehicle-mounted unit, method of detecting sensitivity gears of vehicle-mounted unit, and vehicle-mounted unit | |
| KR20160065732A (en) | wireless wakeup signal transmitter for electronic equipment and receiver for the same | |
| EP2245748B1 (en) | Power-saving receiver | |
| CN107782964A (en) | Alternative output pulse signal frequency and measuring system, the measuring method counted | |
| CN106972867B (en) | A kind of filter calibration device, filter calibration method and digital receiver | |
| CN202092770U (en) | Probe device for wireless vibration measurement | |
| CN103572441B (en) | For the sensor of the monitoring running state that spins, wireless sensing node and method thereof | |
| CN101521609A (en) | Wireless sensor network node hardware device | |
| CN102098116A (en) | Digital frequency spectrum high-speed scanning detection control technology | |
| CN105469006A (en) | Electronic tag arousing method, electronic tag arousing device and electronic tag | |
| CN203632629U (en) | Intermediate-frequency filter circuit having frequency adaptivity | |
| CN105788205B (en) | Acquisition terminal based on WIA-PA wireless communication module and power management monitoring method thereof | |
| CN205910830U (en) | Wireless meter reading terminal | |
| CN104348468A (en) | Pulse width self-adaptive single-bus receiver | |
| CN208257806U (en) | A kind of frequency deviation test macro of power line carrier communication unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: YIN MING Free format text: FORMER OWNER: JIAXING LIANXING MICROELECTRONICS CO., LTD. Effective date: 20150116 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20150116 Address after: Jiaxing City, Zhejiang province 314006 Ling Gong Tang Road No. 3339 building A block 3 building JRC Applicant after: Yin Ming Address before: Jiaxing City, Zhejiang province 314006 Ling Gong Tang Road No. 3339 building A block 3 building JRC Applicant before: Jiaxing Lianxing Microelectronic Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170428 Address after: 201822 room J86, building 1288, Yecheng Road, Shanghai, Jiading District, 6 Patentee after: Hai Tong Electronic Technology (Shanghai) Co., Ltd. Address before: Jiaxing City, Zhejiang province 314006 Ling Gong Tang Road No. 3339 building A block 3 building JRC Patentee before: Yin Ming |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210901 Address after: 310051 room 1001, innovation building, No. 3850, Jiangnan Avenue, hi tech (Binjiang) District, Hangzhou, Zhejiang Patentee after: HANGZHOU ZHONGKE MICROELECTRONICS Co.,Ltd. Address before: Room j86, building 6, 1288 Yecheng Road, Jiading District, Shanghai, 201822 Patentee before: Haidang Electronic Technology (Shanghai) Co.,Ltd. |