CN103107158A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN103107158A CN103107158A CN2011103579760A CN201110357976A CN103107158A CN 103107158 A CN103107158 A CN 103107158A CN 2011103579760 A CN2011103579760 A CN 2011103579760A CN 201110357976 A CN201110357976 A CN 201110357976A CN 103107158 A CN103107158 A CN 103107158A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 74
- 230000004888 barrier function Effects 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 208
- 239000012790 adhesive layer Substances 0.000 claims description 43
- 239000013078 crystal Substances 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 230000015572 biosynthetic process Effects 0.000 claims description 26
- 238000001179 sorption measurement Methods 0.000 claims description 21
- 239000010949 copper Substances 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 10
- 229910052582 BN Inorganic materials 0.000 claims description 8
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000011049 filling Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
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- 238000002513 implantation Methods 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
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- 238000000280 densification Methods 0.000 description 1
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- 238000005137 deposition process Methods 0.000 description 1
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- 238000007687 exposure technique Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 125000000026 trimethylsilyl group Chemical group [H]C([H])([H])[Si]([*])(C([H])([H])[H])C([H])([H])[H] 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention provides a semiconductor device and a forming method thereof. The forming method includes a first step of providing a semiconductor substrate, a second step of forming a bonding layer, an etching barrier layer, and a dielectric layer on the semiconductor substrate in sequence, wherein a range of the dielectric constant of the etching barrier layer is 2.2-2.5, a third step of etching the dielectric layer, the etching barrier layer and the bonding layer in sequence to expose the semiconductor substrate so as to form a groove, and a fourth step of filling a metal layer in the groove. The semiconductor device comprises the semiconductor substrate, the bonding layer, the etching barrier layer, the dielectric layer and a metal wiring layer or a conductive plug. The bonding layer, the etching barrier layer and the dielectric layer are located on the semiconductor substrate in sequence. The range of the dielectric constant of the etching barrier layer is 2.2-2.5. The metal wiring layer or the conductive plug is arranged on the semiconductor substrate and penetrates through the dielectric layer, the etching barrier layer and the bonding layer in sequence. The etching barrier layer in the semiconductor device is capable of reducing resistor-capacitor (RC) interconnection delay of the semiconductor device. The bonding layer arranged between the etching barrier layer and the semiconductor substrate is capable of improving the binding force between the etching barrier layer and the semiconductor substrate.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular a kind of semiconductor device and forming method thereof.
Background technology
Along with the development of IC technology, device size is more and more less, and interconnection RC postpones the impact of device opening speed increasing, and the impact considerably beyond grid delay brings becomes so reduce the RC interconnect delay focus that people pay close attention to.On the one hand people introduce with the little Cu of resistivity and replace the large Al of resistivity, reducing interconnection resistance, and are applied to 0.25 μ m and following technique; People introduce advanced low-k materials and reduce electric capacity between metal interconnecting wires on the other hand.Further, when characteristic size reaches 32 nanometers and following technique, when making copper wiring or conductive plunger, for preventing the RC effect, the dielectric material that must use ultralow dielectric (Ultra low k) is as dielectric layer (described ultralow k as dielectric constant less than or equal to 2.5).
In order to solve Cu diffusion contamination problem, first deposit skim Cu barrier layer-Ti/TiN or Ta/TaN before deposit Cu; For the problem of the etching difficulty that solves Cu, the Cu damascene structure arises at the historic moment, and the IC industry generally adopts this structure to do Cu technique now.But along with the introducing of these new materials brings a lot of problems, such as, the selection of the etch stop layer in damascene structure and preparation, it makes the device reliability problem also become challenge.
Etch stop effect when the effect of etch stop layer is to define groove and dielectric layer through-hole structure in above-mentioned low-k or ultra-low dielectric constant material layer on the one hand is (because both consist of the material difference, have better etching selectivity), can obtain better groove and dielectric layer through-hole structure.On the other hand, also provide as preventing that metallic copper material is to diffusion inside.
The manufacture craft of semiconductor device is as shown in Figures 1 to 4:
With reference to figure 1, Semiconductor substrate 10 is provided, be formed with as structures such as transistor, capacitor, conductive plungers on described Semiconductor substrate 10; Forming etching barrier layer 20 on Semiconductor substrate 10 (is Si
xC
yN
z); Form low k or ultralow k dielectric layer 30 on etching barrier layer 20; Form anti-reflecting layer (BARC) 40 on low k or ultralow k dielectric layer 30; Apply photoresist layer 50 on anti-reflecting layer 40; Through exposure imaging technique, define the pattern of opening on photoresist layer 50.
As shown in Figure 2, take photoresist layer 50 as mask, along the low k of the pattern etch of opening or ultralow k dielectric layer 30 to exposing Semiconductor substrate 10, form groove 60.
As shown in Figure 3, remove photoresist layer 50 and anti-reflecting layer 40; Form copper metal layer 70 with sputtering process, and described copper metal layer 70 is filled full groove on low k or ultralow k dielectric layer 30.
As shown in Figure 4, adopt chemical mechanical milling method (CMP) planarization copper metal layer 70 to exposing low k or ultralow k dielectric layer 30, form metal wiring layer 70a.
People adopt carbonitride of silicium (Si mostly at present
xC
yN
z) serve as etching barrier layer.More heterogeneous pass technology can application reference number is the U.S. Patent application of US20000705279.
But Si
xC
yN
zDielectric constant is larger, generally is positioned at 5.1～5.6 scopes, thereby not too is fit to do insulating barrier, is unfavorable for reducing the RC interconnect delay.
A kind of double-deck carbonitride of silicium also is provided in prior art, it specifically can comprise: dielectric constant is about 5.2 the first carbonitride of silicium and the second titanium carbonitride that is positioned on described the first carbonitride of silicium, and the dielectric constant of described the second carbonitride of silicium is about 3.8.Wherein, described the second carbonitride of silicium is that the using plasma injection mode is to the top Implantation element formation of the first carbonitride of silicium.Although can reduce the dielectric constant of carbonitride of silicium by plasma Implantation element, also can cause this double-deck carbonitride of silicium plasma damage (PID) to occur simultaneously.In addition, inject too much carbon ion for the dielectric constant that reduces carbonitride of silicium and also can make carbonitride of silicium have a lot of dangling bonds, finally cause wherein existing higher electric charge, these all are unfavorable for reducing the RC interconnect delay of semiconductor device.
Therefore, the RC interconnect delay that how to reduce semiconductor device just becomes those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor device and forming method thereof, to reduce the RC interconnect delay of semiconductor device.
For addressing the above problem, the invention provides a kind of semiconductor device, comprising:
Semiconductor substrate;
Be positioned at adhesive layer, etching barrier layer and dielectric layer on described Semiconductor substrate, the dielectric constant of described etching barrier layer is positioned at 2.2～2.5;
Be positioned on described Semiconductor substrate and run through metal wiring layer or the conductive plunger of described dielectric layer, etching barrier layer and adhesive layer.
Alternatively, the material of described metal wiring layer or conductive plunger comprises copper.
Alternatively, the material of described etching barrier layer comprises boron nitride.
Alternatively, the thickness range of described etching barrier layer comprises
Alternatively, the material of described adhesive layer comprises the carbonitride of silicium layer.
Alternatively, the thickness range of described adhesive layer comprises
Alternatively, comprise between described adhesive layer and described Semiconductor substrate: inculating crystal layer.
Alternatively, the material of described inculating crystal layer comprises silicon and silicon nitride.
Alternatively, the thickness range of described inculating crystal layer comprises
Alternatively, also comprise between described adhesive layer and described inculating crystal layer: adsorption layer.
Alternatively, the material of described adsorption layer comprises silicon.
Alternatively, the thickness range of described adsorption layer comprises
Alternatively, described dielectric layer comprises low k dielectric layer or ultralow k dielectric layer.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprise step:
Semiconductor substrate is provided;
Form successively adhesive layer, etching barrier layer and dielectric layer on described Semiconductor substrate, the dielectric constant of described etching barrier layer is positioned at 2.2～2.5;
The described dielectric layer of etching, etching barrier layer and adhesive layer to exposing described Semiconductor substrate, form groove successively;
Fill full metal level in described groove.
Alternatively, the material of described metal level comprises copper.
Alternatively, the material of described etching barrier layer comprises boron nitride.
Alternatively, the thickness range of described etching barrier layer comprises
Alternatively, the material of described adhesive layer comprises the carbonitride of silicium layer.
Alternatively, the thickness range of described adhesive layer comprises
Alternatively, also comprised before forming described adhesive layer: form inculating crystal layer on described Semiconductor substrate.
Alternatively, form described inculating crystal layer and comprise the pecvd process that adopts radio-frequency power to be less than or equal to 50W.
Alternatively, the material of described inculating crystal layer comprises silicon and silicon nitride.
Alternatively, the thickness range of described inculating crystal layer comprises
Alternatively, also comprised before forming described adhesive layer: form adsorption layer on described inculating crystal layer.
Alternatively, the material of described adsorption layer comprises silicon.
Alternatively, the thickness range of described adsorption layer comprises
Alternatively, described dielectric layer comprises low k dielectric layer or ultralow k dielectric layer.
Compared with prior art, the present invention has the following advantages:
1) in the present invention, the dielectric constant of etching barrier layer is positioned at 2.2～2.5, thereby described etching barrier layer is suitable for doing insulating barrier, and can reduce the RC interconnect delay of semiconductor device; And adhesive layer is set below etching barrier layer, and described adhesive layer can improve the adhesion between etching barrier layer and Semiconductor substrate.
2) in possibility, between adhesive layer and Semiconductor substrate, inculating crystal layer is set, described inculating crystal layer can react with metal level, thereby improves the adhesion of etching barrier layer and metal level.
3) in possibility, between adhesive layer and inculating crystal layer, adsorption layer is set, described adsorption layer can absorb the ultraviolet light in pecvd process, thereby reduces plasma to the damage of etching barrier layer.
Description of drawings
Fig. 1 to Fig. 4 is the schematic diagram that prior art forms the metal line that comprises ultralow k dielectric layer;
Fig. 5 is the formation method embodiment schematic flow sheet of semiconductor device of the present invention;
Fig. 6 to Figure 14 is the schematic diagram of the formation method of embodiment of the present invention semiconductor device;
Figure 15 is the schematic diagram of the formation method of the embodiment of the present invention two semiconductor device;
Figure 16 is the schematic diagram of the formation method of the embodiment of the present invention three semiconductor device.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
When prior art is made metal wiring layer or conductive plunger in last part technology, adopt low k or ultralow k dielectric material as in the dielectric layer process, the inventor finds because the dielectric constant of the etching barrier layer below dielectric layer is larger, thereby is unfavorable for reducing the RC interconnect delay of semiconductor device.The Implantation ion is to reduce the dielectric constant of etching barrier layer in the etching barrier layer although prior art can using plasma technique, and the dielectric constant of the etching barrier layer after the Implantation ion is still not ideal enough; And plasma doping technique can cause the PID defective of etching barrier layer; In addition, inject too much carbon ion and also can make etching barrier layer have a lot of dangling bonds, cause wherein existing higher electric charge.
The inventor through the analysis to reason, when constantly research finds to adopt dielectric constant to be positioned at 2.2～2.5 etching barrier layer, can reduce the RC interconnect delay of semiconductor device for above-mentioned technical problem; Less in 2.2～2.5 etching barrier layer and the adhesion between Semiconductor substrate for dielectric constant, also between etching barrier layer and Semiconductor substrate, adhesive layer is set, described adhesive layer can improve the adhesion between etching barrier layer and Semiconductor substrate.
Fig. 5 is the formation method embodiment schematic flow sheet of semiconductor device of the present invention, and as shown in Figure 5, the formation method of described semiconductor device comprises:
Step S1 provides Semiconductor substrate;
Step S2 forms adhesive layer, etching barrier layer and dielectric layer successively on described Semiconductor substrate, the dielectric constant of described etching barrier layer is positioned at 2.2～2.5;
Step S3, the described dielectric layer of etching, etching barrier layer and adhesive layer to exposing described Semiconductor substrate, form groove successively;
Step S4 fills full metal level in described groove.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Embodiment one
Fig. 6 to Figure 11 is embodiment one schematic diagram that the present invention forms the semiconductor device that comprises ultralow k dielectric layer.The present embodiment is take the formation metal wiring layer as example, but it does not limit protection scope of the present invention, as: can also adopt the present embodiment method to form conductive plunger etc.
As shown in Figure 6, provide Semiconductor substrate 100.
Usually be formed with as structures such as transistor, capacitor, metal wiring layers through FEOL on described Semiconductor substrate 100.
As shown in Figure 7, form adhesive layer 200 on described Semiconductor substrate 100.
Described adhesive layer 200 is mainly used in increasing the adhesion between the etching barrier layer of Semiconductor substrate 100 and follow-up formation.
The material of adhesive layer described in the present embodiment 200 can be carbonitride of silicium (Si
xC
yN
z, x, y and z represent respectively the content of Si, C and N).The dielectric constant of described carbonitride of silicium is positioned at 5.1～5.6 scopes, and wherein the content range of each component is same as the prior art.
The thickness range of described adhesive layer 200 can comprise
As:
Or
Deng.
Described adhesive layer 200 can adopt chemical gaseous phase depositing process to form, and specifically can pass through trimethyl silyl (TMS) and ammonia gas react and realize.
As shown in Figure 8, form etching barrier layer 300 on described adhesive layer 200.
Described etching barrier layer 300 is as etching stop layer, is damaged to following rete to prevent in etching process etching gas or liquid.
The dielectric constant of etching barrier layer described in the present embodiment 300 can be positioned at 2.2～2.5, as: 2.2,2.3,2.4 or 2.5.This moment, etching barrier layer 300 was more suitable for doing insulating barrier, and less on the RC interconnect delay impact of semiconductor device.
The material of described etching barrier layer 300 can be boron nitride, and its thickness can comprise
As:
Or
The dielectric constant of described boron nitride is directly proportional to its thickness.
Described boron nitride can adopt Atomic layer deposition method to form, and also can adopt additive method formation in prior art.When adopting Atomic layer deposition method to form boron nitride, reaction temperature can be positioned at 400 ℃～600 ℃, and air pressure range can be positioned at 1torr～3torr, and reacting gas can comprise BCl
3, BBr
3, B
2H
6Or BF
3In at least a, NH
3Or N
2H
4In at least a.
As shown in Figure 9, form dielectric layer 400 on described etching barrier layer 300.
Described dielectric layer 400 can be the low k dielectric layer, as black diamond (black diamond) etc.; Also can be ultralow k dielectric layer, as SiOCH etc.The dielectric constant of described ultralow k dielectric layer can be less than or equal to 2.5.The concrete formation technique of described dielectric layer 400 is known for those skilled in the art, does not repeat them here.
As shown in figure 10, form anti-reflecting layers 600 on described dielectric layer 400 surfaces, and on anti-reflecting layer 600 spin coating photoresist layer 700.
The rete of described anti-reflecting layer 600 below protection in post-exposure technique avoided lower face mask layer to be subject to the impact of light and changes character.
As shown in figure 11, described photoresist layer 700 is carried out patterned process, form opening figure; Take described photoresist layer 700 as mask, along the described anti-reflecting layer 600 of opening figure etching successively, dielectric layer 400, etching barrier layer 300 and adhesive layer 200 to exposing described Semiconductor substrate 100, form groove, described groove forms metal wiring layer in order to follow-up filling.
As shown in figure 12, remove photoresist layer 700 with cineration technics, then remove residual photoresist layer 700 and anti-reflecting layer 600 with wet etching.
As shown in figure 13, fill full metal level 800 in described groove.
In the present embodiment, the material of described metal level 800 can be copper.At this moment, before forming metal level 800, channel bottom also the Applied Physics vapour deposition process form layer of copper inculating crystal layer (not shown), make metal level 800 around its growth.
As shown in figure 14, carry out planarization, make the upper surface flush of upper surface and the described metal level 800 of described dielectric layer 400.
So far, form metal wiring layer 800a.
Embodiment two
Compare with embodiment one, the present embodiment also comprised before forming described adhesive layer: form inculating crystal layer on described Semiconductor substrate.
With reference to shown in Figure 15, the metal wiring layer 800a of the last semiconductor device that forms of the present embodiment still is positioned on Semiconductor substrate 100 but need to runs through successively described dielectric layer 400, etching barrier layer 300, adhesive layer 200 and inculating crystal layer 500.
All the other steps are identical with embodiment one, do not repeat them here.
Described inculating crystal layer 500 can react with metal level, thereby can improve the adhesion of etching barrier layer 300 and metal wiring layer 800a.
The material of the 800a of metal wiring layer described in the present embodiment is copper, and the material of described inculating crystal layer 500 can comprise silicon and silicon nitride, and it can form by the PECVD method, also can adopt existing other techniques to form.Particularly, can adopt SiH
4And NH
3Reaction generates.
Preferably, the damage that may cause semiconductor device in order to stop plasma, the radio-frequency power when forming inculating crystal layer 500 can be less than or equal to 50W, as: 50W, 40W, 25W or 10W.
The thickness range of described inculating crystal layer 500 can comprise
As:
Or
In order to bring into play better the combination of inculating crystal layer 500, can also change the structure of metal wiring layer 800a, to increase the contact area of inculating crystal layer 500 and metal wiring layer 800a.
Embodiment three
Compare with embodiment two, the present embodiment also comprised before forming described adhesive layer: form adsorption layer on described inculating crystal layer.
With reference to shown in Figure 16, the metal wiring layer 800a of the last semiconductor device that forms of the present embodiment still is positioned on Semiconductor substrate 100 but need to runs through successively described dielectric layer 400, etching barrier layer 300, adhesive layer 200, adsorption layer 900 and inculating crystal layer 500.
All the other steps are identical with embodiment one, do not repeat them here.
When described dielectric layer 400 adopted pecvd process to form, described adsorption layer 900 can absorb the ultraviolet light in pecvd process, thereby reduces plasma to the damage of etching barrier layer 300.
The material of described adsorption layer 900 can comprise silicon, and its thickness range can comprise
As:
Or
Described adsorption layer 900 can adopt any method of prior art to form, and it does not limit protection scope of the present invention.
Particularly, the present embodiment adopts the PECVD method to form inculating crystal layer 500 and adsorption layer 900.When adopting SiH
4And NH
3After reaction generates inculating crystal layer 500, stop supplies NH
3, continue to use SiH
4Generate adsorption layer 900, thereby method is simple, is easy to control.
Need to prove, in above-mentioned three embodiment in forming the process of groove, one deck TEOS (tetraethoxysilane) layer can also be set between dielectric layer and anti-reflecting layer, described TEOS layer is the oxide layer of one deck densification, and it can further improve the adhesion between dielectric layer and anti-reflecting layer.
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (27)
1. a semiconductor device, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at adhesive layer, etching barrier layer and dielectric layer on described Semiconductor substrate, the dielectric constant of described etching barrier layer is positioned at 2.2～2.5;
Be positioned on described Semiconductor substrate and run through metal wiring layer or the conductive plunger of described dielectric layer, etching barrier layer and adhesive layer.
2. semiconductor device as claimed in claim 1, is characterized in that, the material of described metal wiring layer or conductive plunger comprises copper.
3. semiconductor device as claimed in claim 1, is characterized in that, the material of described etching barrier layer comprises boron nitride.
4. semiconductor device as claimed in claim 1, is characterized in that, the thickness range of described etching barrier layer comprises
5. semiconductor device as claimed in claim 1, is characterized in that, the material of described adhesive layer comprises the carbonitride of silicium layer.
6. semiconductor device as claimed in claim 1, is characterized in that, the thickness range of described adhesive layer comprises
7. semiconductor device as claimed in claim 1, is characterized in that, comprises between described adhesive layer and described Semiconductor substrate: inculating crystal layer.
8. semiconductor device as claimed in claim 7, is characterized in that, the material of described inculating crystal layer comprises silicon and silicon nitride.
9. semiconductor device as claimed in claim 7, is characterized in that, the thickness range of described inculating crystal layer comprises
10. semiconductor device as claimed in claim 7, is characterized in that, also comprises between described adhesive layer and described inculating crystal layer: adsorption layer.
11. semiconductor device as claimed in claim 10 is characterized in that, the material of described adsorption layer comprises silicon.
12. the semiconductor device as claim 10 is stated is characterized in that, the thickness range of described adsorption layer comprises
13. semiconductor device as claimed in claim 1 is characterized in that, described dielectric layer comprises low k dielectric layer or ultralow k dielectric layer.
14. the formation method of a semiconductor device is characterized in that, comprises step:
Semiconductor substrate is provided;
Form successively adhesive layer, etching barrier layer and dielectric layer on described Semiconductor substrate, the dielectric constant of described etching barrier layer is positioned at 2.2～2.5;
The described dielectric layer of etching, etching barrier layer and adhesive layer to exposing described Semiconductor substrate, form groove successively;
Fill full metal level in described groove.
15. the formation method of semiconductor device as claimed in claim 14 is characterized in that the material of described metal level comprises copper.
16. the formation method of semiconductor device as claimed in claim 14 is characterized in that the material of described etching barrier layer comprises boron nitride.
17. the formation method of semiconductor device as claimed in claim 14 is characterized in that the thickness range of described etching barrier layer comprises
18. the formation method of semiconductor device as claimed in claim 14 is characterized in that the material of described adhesive layer comprises the carbonitride of silicium layer.
19. the formation method of semiconductor device as claimed in claim 14 is characterized in that the thickness range of described adhesive layer comprises
20. the formation method of semiconductor device as claimed in claim 14 is characterized in that, also comprises before forming described adhesive layer: form inculating crystal layer on described Semiconductor substrate.
21. the formation method of semiconductor device as claimed in claim 20 is characterized in that, forms described inculating crystal layer and comprises the pecvd process that adopts radio-frequency power to be less than or equal to 50W.
22. the formation method of semiconductor device as claimed in claim 20 is characterized in that the material of described inculating crystal layer comprises silicon and silicon nitride.
23. the formation method of semiconductor device as claimed in claim 20 is characterized in that the thickness range of described inculating crystal layer comprises
24. the formation method of semiconductor device as claimed in claim 20 is characterized in that, also comprises before forming described adhesive layer: form adsorption layer on described inculating crystal layer.
25. the formation method of semiconductor device as claimed in claim 24 is characterized in that the material of described adsorption layer comprises silicon.
26. the formation method of semiconductor device as claimed in claim 24 is characterized in that the thickness range of described adsorption layer comprises
27. the formation method of semiconductor device as claimed in claim 14 is characterized in that, described dielectric layer comprises low k dielectric layer or ultralow k dielectric layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241194A (en) * | 2013-06-20 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor interconnecting structure and manufacturing method thereof |
| CN112374456A (en) * | 2020-11-12 | 2021-02-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing MEMS device |
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| CN112374456B (en) * | 2020-11-12 | 2024-01-23 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing MEMS device |
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