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CN103098191B - 电子元器件安装体、电子元器件及基板 - Google Patents

电子元器件安装体、电子元器件及基板 Download PDF

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Publication number
CN103098191B
CN103098191B CN201180029141.0A CN201180029141A CN103098191B CN 103098191 B CN103098191 B CN 103098191B CN 201180029141 A CN201180029141 A CN 201180029141A CN 103098191 B CN103098191 B CN 103098191B
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components
electrode
substrate
electrode terminal
dummy
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CN103098191A (zh
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樱井大辅
后川和也
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明提供的电子元器件安装体，在基板（6）上安装有包括多个元器件侧电极端子（3a，3b）的电子元器件（1），该基板包括与多个元器件侧电极端子（3a，3b）相对应的多个基板侧电极端子（7a，7b），其特征在于，包括：多个突起状电极（5a，5b），该突起状电极分别形成于电子元器件（1）的多个元器件侧电极端子（3a，3b）上且与电子元器件（1）及基板（6）电连接；假电极（3c），该假电极形成于电子元器件（1）上且与多个元器件侧电极端子（3a，3b）中的预定位置上的元器件侧电极端子（3a）电连接，与假电极（3c）电连接的预定位置上的元器件侧电极端子（3a）上的突起状电极（5a）比与上述预定位置不同的位置上的元器件侧电极端子（3b）上的突起状电极（5b）更高。

Description

电子元器件安装体、电子元器件及基板
技术领域
本发明涉及一种具有在基板上安装有电子元器件的结构的电子元器件安装体，以及用于电子元器件安装体上的电子元器件及基板。
通常，在倒装芯片的安装中，LSI等半导体元件的电极上形成有焊料凸点等突起电极，且形成有该突起电极的半导体元件面朝下地安装在安装基板上。具体而言，加热后的半导体元件的突起电极压接在安装基板的电极端子上。作为在半导体元件的电极上形成焊料凸点的方法，一般采用如下方法：通过丝网印刷、涂布或电解电镀在电极上形成焊料层后，利用回流炉将该焊料层加热到焊料熔点以上。
但是，近年来，为了同时实现半导体元件的高密度化与半导体元件电极端子的多引脚化，半导体元件的电极端子的窄间距化及面积缩小化正在加以推进。由于如上所述那样半导体元件的电极端子趋于窄间距化，因此若像从前那样在半导体元件的外周部配置1列电极端子、或交错地配置2列，则电极端子间可能会发生短路。另外，由于半导体元件的电极端子的窄间距化，从而产生由半导体元件与安装基板的热膨胀系数差而产生的翘曲所引起的连接不良等问题。因此，采用将半导体元件的电极端子配置成矩阵状的区域配置，从而实现电极端子间间距的扩大。
但是，近年来，即使进行区域配置，电极端子的窄间距化进展依然显著，焊料接合部间的间距变窄。另外，近年来，半导体元件与基板端子之间的间隙也变窄了。因此，在安装倒装芯片时进行的压接及加热工序中，产生焊料桥接不良的问题。焊料桥接不良的产生是由于熔融的焊料凸点发生变形，并且由于焊料表面的张力引起焊料凸点互相粘连。
因此，提出一种半导体装置，利用含有金属粒子的绝缘性皮膜将由金或铜形成的突起电极覆盖(例如，参照专利文献1)。根据该半导体装置，在安装倒装芯片时绝缘性皮膜及突起电极不会熔融。在该半导体装置中，通过在注入于半导体元件与基板之间的密封树脂硬化收缩时产生的压缩方向的力，从而使含有绝缘性皮膜的金属粒子与突起电极及基板端子接触，并使半导体元件的突起电极与基板端子电导通。由此，根据该半导体装置，即使电极端子间的间距变狭窄了，也能防止桥接的发生。
但是，在仅依靠金属粒子与突起电极及基板端子不扩散接合地接触来确保电导通的连接方式下，若半导体元件的电极面积变小，则当然存在于突起电极与基板端子间的导电粒子的数量将变少。因此，将产生连接电阻变大且信号的传输损失增大的问题。特别是近年来，由于对半导体元件电极端子的窄间距化的要求变得非常严苛，并且半导体元件的电极端子的面积变得越来越小，因此该问题更为显著。
因此，开始采用如下的2层结构的突起电极：利用高熔点金属形成下层金属，并利用焊料在该下层金属上形成上层金属(例如，参照专利文献2)。根据该2层结构的突起电极，与仅由焊料层组成的突起电极相比，能够减少焊料量，并且能在安装倒装芯片时减少平面方向上的焊料坍塌量。因此，可以防止焊料桥接的发生。另外，根据该2层结构的突起电极，由于焊料与基板端子进行扩散接合，因此接触电阻变小了。由此，信号的传输损失也不会增大。
现有技术
专利文献
专利文献1
日本专利特开2003-282617号公报
专利文献2
日本专利特开平9－97791号公报
发明内容
发明所要解决的技术问题
但是，出于近年来与布线规则的细微化或信号处理的高速化的要求相对应的目的，开始使用所谓low－k模、ULK(Ultralow－k：超低介电常数)膜等低介电常数绝缘膜，以作为半导体元件的层间绝缘膜。为了降低介电常数，低介电常数绝缘膜呈具有多个数nm大小的空孔的多孔状。低介电常数绝缘膜的密度为，例如：1.0～1.4g/cm3。因此，低介电常数绝缘膜是脆弱的。因此，在从前的安装方法中，存在低介电常数绝缘膜容易产生剥离或裂缝的问题。
以专利文献2中记载的安装方法为例对该问题进行详细说明。图9是专利文献2中记载的安装方法的示意图。如图9上侧的图所示，在半导体元件101上形成有由电极102a及焊料接合部102b组成的凸点103。在该安装方法中，如图9所示，将上述凸点103与电路基板104上的电极105的位置对准后，对半导体元件101进行加热，并向电路基板104施加压力，从而使焊料接合部102b熔融。由此，将半导体元件101装载到电路基板104上。
但是，如专利文献2的安装方法所示，通过电极102a及焊料接合部102b来确保凸点103的高度在面内相等，在此情况下，存在于电极102a正下方的脆弱的低介电常数绝缘膜会产生剥离或裂缝，该电极102a配置在半导体元件101的边角部分。这是由于，在凸点103高度相等的情况下，在倒装芯片工序中，较大的应力作用在存在于半导体元件101边角部分上的电极102a正下方的低介电常数绝缘膜上。即，由于在倒装芯片工序中将焊料熔融后进行的冷却过程中，半导体元件101与电路基板104的弹性率及线膨胀系数存在差值从而引起热应力集中到半导体元件101的边角部分上的焊料接合部102b，并且该应力不经过缓和而直接被传递到半导体元件101的电极102a正下方的层。另外，在温度差急剧增大的使用环境下，还存在如下的问题：产生与在倒装芯片工序中产生的热应力集中相同的热应力集中，并且位于电极正下方的脆弱的低介电常数绝缘膜产生剥离或裂缝。
本发明鉴于上述问题，目的在于，提供一种电子元器件安装体、电子元器件以及基板，即使在将具有脆弱薄膜的半导体元件等电阻元器件安装到基板上的情况下也能容易地确保较高的连接可靠性。
解决技术问题所采用的技术方案
为了达成上述目的，本发明的第1电子元器件安装体在基板上安装有包括多个元器件侧电极端子的电子元器件，该基板包括与上述多个元器件侧电极端子相对应的多个基板侧电极端子，该电子元器件安装体的特征在于，包括：多个突起状电极，该突起状电极分别形成于上述电子元器件的上述多个元器件侧电极端子上且与上述电子元器件及上述基板电连接；假电极，该假电极形成于上述电子元器件上且与上述多个元器件侧电极端子中的预定位置上的元器件侧电极端子电连接，与上述假电极电连接的上述预定位置上的元器件侧电极端子上的上述突起状电极比与上述预定位置不同的位置上的元器件侧电极端子上的上述突起状电极更高。
在上述本发明的第1电子元器件安装体中，也可以将上述假电极与上述多个元器件侧电极端子中的配置于与上述电子元器件的边角部相对应的位置上的元器件侧电极端子电连接。
另外，在上述本发明的第1电子元器件安装体中，上述假电极可以包含面积互不相同的多种假电极，并且可以使得进行电连接的假电极的面积越大，与上述假电极电连接的元器件侧电极端子上的上述突起状电极的高度越高。另外，在该结构中，上述假电极包含：第1假电极，该第1假电极与第1元器件侧电极端子电连接，该第1元器件侧电极端子配置在与上述电子元器件的边角部相对应的位置上；以及第2假电极，该第2假电极的面积比上述第1假电极小并且与第2元器件侧电极端子电连接，该第2元器件侧电极端子与上述第1元器件侧电极端子相邻，上述第1元器件侧电极端子上的上述突起状电极可以比上述第2元器件侧电极端子上的上述突起状电极更高。
另外，在上述本发明的第1电子元器件安装体中，也可以将上述假电极形成于与配置有上述电子元器件的上述多个元器件侧电极端子的面不同的面上。在该结构中，也可以将上述假电极与上述多个元器件侧电极端子中的配置于与上述电子元器件的边角部相对应的位置上的元器件侧电极端子电连接。另外，在该结构中，也可以将上述多个元器件侧电极端子配置成矩阵状，并且将上述假电极与配置有上述多个元器件侧电极端子的区域的中央部上的元器件侧电极端子电连接。另外，在该结构中，也可以将上述假电极与电源端子或散热源连接。
另外，在上述本发明的第1电子元器件安装体中，也可以将上述假电极形成于配置有上述多个元器件侧电极端子的面上且具有起到位置校正用识别标记的作用的形状。
为了达成上述目的，本发明的第2电子元器件安装体在基板上安装有包括多个元器件侧电极端子的电子元器件，该基板包括与上述多个元器件侧电极端子相对应的多个基板侧电极端子，该电子元器件安装体的特征在于，包括：多个突起状电极，该突起状电极分别形成于上述基板的上述多个基板侧电极端子上且与上述电子元器件及上述基板电连接；假电极，该假电极形成于上述基板上且与上述多个基板侧电极端子中的预定位置上的基板侧电极端子电连接，与上述假电极电连接的上述预定位置上的基板侧电极端子上的上述突起状电极比与上述预定位置不同的位置上的基板侧电极端子上的上述突起状电极更高。
在上述本发明的第2电子元器件安装体中，也可以将上述假电极与上述多个基板侧电极端子中的配置于与上述电子元器件的边角部相对应的位置上的基板侧电极端子电连接。
另外，在上述本发明的第2电子元器件安装体中，上述假电极可以包含面积互不相同的多种假电极，并且可以使得进行电连接的假电极的面积越大，与上述假电极电连接的基板侧电极端子上的上述突起状电极的高度越高。另外，在该结构中，上述假电极包含：第1假电极，该第1假电极与第1基板侧电极端子电连接，该第1基板侧电极端子配置在与上述电子元器件的边角部相对应的位置上；以及第2假电极，该第2假电极的面积比上述第1假电极小，并且与第2基板侧电极端子电连接，该第2基板侧电极端子与上述第1基板侧电极端子相邻，上述第1基板侧电极端子上的上述突起状电极可以比上述第2基板侧电极端子上的上述突起状电极更高。
为了达成上述目的，本发明的电子元器件包括：多个元器件侧电极端子；假电极，该假电极与上述多个元器件侧电极端子中的预定位置上的元器件侧电极端子电连接；以及多个突起状电极，该突起状电极分别形成于上述多个元器件侧电极端子上，与上述假电极电连接的上述预定位置上的元器件侧电极端子上的上述突起状电极比与上述预定位置不同的位置上的元器件侧电极端子上的上述突起状电极更高。
在上述本发明的电子元器件中，也可以将上述假电极与上述多个元器件侧电极端子中的配置于与上述电子元器件的边角部相对应的位置上的元器件侧电极端子电连接。
另外，在上述本发明的电子元器件中，可以使上述假电极包含面积互不相同的多种假电极，并且使得进行电连接的假电极的面积越大，与上述假电极电连接的元器件侧电极端子上的上述突起状电极的高度越高。另外，在该结构中，上述假电极包含：第1假电极，该第1假电极与第1元器件侧电极端子电连接，该第1元器件侧电极端子配置在与该电子元器件的边角部相对应的位置上；以及第2假电极，该第2假电极的面积比上述第1假电极小，并且与第2元器件侧电极端子电连接，该第2元器件侧电极端子与上述第1元器件侧电极端子相邻，上述第1元器件侧电极端子上的上述突起状电极可以比上述第2元器件侧电极端子上的上述突起状电极更高。
另外，在上述本发明的电子元器件中，也可以将上述假电极形成于与配置有上述多个元器件侧电极端子的面不同的面上。在该结构中，也可以将上述假电极与上述多个元器件侧电极端子中的配置于与上述电子元器件的边角部相对应的位置上的元器件侧电极端子电连接。另外，在该结构中，也可以将上述多个元器件侧电极端子配置成矩阵状，并且将上述假电极与配置有上述多个元器件侧电极端子的区域的中央部上的元器件侧电极端子电连接。
另外，在上述本发明的电子元器件中，也可以使上述假电极形成于配置有上述多个元器件侧电极端子的面上且具有起到位置校正用识别标记的作用的形状。
另外，为了达成上述目的，本发明的基板的特征在于，包括：多个基板侧电极端子；假电极，该假电极与上述多个基板侧电极端子中的预定位置上的基板侧电极端子电连接；以及多个突起状电极，该突起状电极分别形成于上述多个基板侧电极端子上，与上述假电极电连接的上述预定位置上的基板侧电极端子上的上述突起状电极比与上述预定位置不同的位置上的基板侧电极端子上的上述突起状电极更高。
在上述本发明的基板中，也可以将上述假电极与上述多个基板侧电极端子中的配置于与安装在该基板上的电子元器件的边角部相对应的位置上的基板侧电极端子电连接。
另外，在上述本发明的基板中，上述假电极可以包含面积互不相同的多种假电极，并且可以使得进行电连接的假电极的面积越大，与上述假电极电连接的基板侧电极端子上的上述突起状电极的高度越高。另外，在该结构中，上述假电极包含：第1假电极，该第1假电极与第1基板侧电极端子电连接，该第1基板侧电极端子配置在与安装在该基板上的电子元器件的边角部相对应的位置上；以及第2假电极，该第2假电极的面积比上述第1假电极小，并且与第2基板侧电极端子电连接，该第2基板侧电极端子与上述第1基板侧电极端子相邻，上述第1基板侧电极端子上的上述突起状电极可以比上述第2基板侧电极端子上的上述突起状电极更高。
发明效果
根据本发明，由于能够选择性地将设置在翘曲最大的部位上的突起状电极的高度加高，因此能够在安装时抵消基板的翘曲。若如此抵消翘曲，则在焊料凝固后的冷却过程中产生的垂直方向(拉伸方向)的焊料接合部的延伸量将减少，并且拉伸方向上的热应力将得以缓和。
另外，根据本发明，由于将设置于电子元器件的边角部的突起状电极的高度加高到比设置于与边角部不同位置上的突起状电极更高，因此能够在电子元器件的边角部加高接合间隙。由此，与接合间隙相等的情况相比，能够使剪切方向上的热应力集中于电子元器件的电极端子上的情况得以缓和。通过缓和该热应力，存在于电子元器件的电极端子正下方的低介电常数绝缘膜等脆弱薄膜所承受的热应力将得以减小。因此，能够防止该脆弱薄膜的剥离及裂缝，能够确保较高的连接可靠性。
因此，根据本发明，即使在将具有脆弱薄膜的半导体元件等电子元器件安装到基板上的情况下也能容易地确保较高的连接可靠性。
附图说明
图1(a)是示意性地表示本发明的实施方式1中的电子元器件安装体的主要部分的剖视图，(b)是示意性地表示本发明的实施方式1中的电子元器件安装体的主要部分的俯视图。
图2是表示本发明的实施方式1中的电子元器件安装体的制造方法的流程图。
图3是用于对本发明的实施方式1中的电子元器件安装体的制造方法按工序分别进行说明的示意图。
图4是用于对本发明的实施方式1中的电子元器件安装体进行说明的示意图。
图5(a)是示意性地表示本发明的实施方式2中的电子元器件安装体的主要部分的剖视图，(b)是示意性地表示本发明的实施方式2中的电子元器件安装体的主要部分的俯视图。
图6是用于对本发明的实施方式2中的电子元器件安装体的制造方法按工序分别进行说明的示意图。
图7(a)是示意性地表示本发明的实施方式3中的电子元器件的主要部分的剖视图，(b)是示意性地表示本发明的实施方式3中的电子元器件的主要部分的俯视图，(c)是示意性地表示本发明的实施方式3中的电子元器件安装体的主要部分的剖视图。
图8是示意性地表示本发明的实施方式4中的电子元器件的主要部分的俯视图。
图9是表示现有的半导体装置的主要部分的示意图。
具体实施方式
下面，参照附图对本发明的实施方式进行说明。在如下的各个实施方式中，作为具有在基板上安装有电子元器件的结构的电子元器件安装体，以具有在电路基板上安装有半导体元件的结构的半导体装置为例进行说明。
(实施方式1)
图1(a)是示意性地表示本发明的实施方式1中的半导体装置的主要部分的剖视图。例外，图1(b)是示意性地表示本发明的实施方式1中的半导体装置的主要部分的俯视图，即从形成有元器件侧电极端子的主面(电极面)一侧观察半导体元件。
在半导体元件1的电极面内侧的层设置有多层布线层，该多层布线层包含：由例如Cu或Al组成的细微布线层以及Low－k膜或ULK膜等低介电常数绝缘膜2，在该多层布线层的最外面等间隔地将多个元器件侧电极端子3设置成矩阵状。
多个元器件侧电极端子3包含：第1元器件侧电极端子3a，该第1元器件侧电极端子3a配置于与半导体元件1的边角部对应的位置上；第2元器件侧电极端子3b，该第2元器件侧电极端子3b配置于与第1元器件侧电极端子3a不同的位置上。另外，在配置有多个元器件侧电极端子3的区域的外侧，设置有面积比元器件侧电极端子3大的假电极3c，并且第1元器件侧电极端子3a与假电极3c由布线3ac连接以使其电导通。例如，可以使第1元器件侧电极端子3a、第2元器件侧电极端子3b、假电极3c以及布线3ac在同一平面内。第1元器件侧电极端子3a、第2元器件侧电极端子3b、假电极3c以及布线3ac中的任一个都可以由例如Al－Cu或Al－Si－Cu组成。
另外，在半导体元件1上设置有覆盖其电极面的绝缘膜4。绝缘膜4具有多个开口部，该开口部使第1元器件侧电极端子3a、第2元器件侧电极端子3b以及假电极3c均至少露出一部分，且将半导体元件1的电极面上的布线覆盖。绝缘膜4例如由Si3N4组成。
另外，第1元器件侧电极端子3a、第2元器件侧电极端子3b以及假电极3c上分别设置有第1突起状电极5a、第2突起状电极5b以及假突起状电极5c。第1突起状电极5a、第2突起状电极5b以及假突起状电极5c由经过例如Ni－P/Au或Ni－Au等焊料浸润后的金属组成。
另一方面，安装有半导体元件1的电路基板6的主面上具有第1基板侧电极端子7a及第2基板侧电极端子7b，该第1基板侧电极端子7a与第2基板侧电极端子7b配置成分别与半导体元件1的第1突起状电极5a及第2突起状电极5b相对。电路基板6例如由硅组成。基板侧电极端子7a、7b例如由Ni/Au、Ni/Pd/Au、Ni/SnAg等组成。
利用焊料8使半导体元件1的第1突起状电极5a及第2突起状电极5b、与电路基板6的第1基板侧电极端子7a及第2基板侧电极端子7b接合，并且电连接或机械连接。焊料8例如由SnAg、SnAgCu、SnZn、SnZnBi、SnPb、SnBi、SnAgBiIn、SnIn、In、Sn等组成。另外，在半导体元件1与电路基板6之间填充有密封树脂9。
在该实施方式1中，作为半导体元件1，使用外形尺寸为6mm×6mm，厚度为0.2mm，并且在其电极面上包括直径为25μm，厚度为1μm的圆形的多个元器件侧电极端子3，该多个元器件侧电极端子3进行区域配置成相互之间中心间距为50μm的矩阵状。另外，作为电路基板6，使用外形尺寸为8mm×8mm，厚度为0.2mm的电路基板。另外，元器件侧电极端子3的绝缘膜4的开口部呈直径为15μm的圆形。另外，假电极3c的绝缘膜4的开口部呈800μm×800μm的正方形。
图2是表示本发明的实施方式1中的半导体装置的制造方法的流程图。如图2所示，在本发明实施方式1的制造方法中，首先，在半导体元件1的元器件侧电极端子上形成作为突起状电极的UBM(UnderBumpMetal：凸点下金属)(步骤S1)，在电路基板6的基板侧电极端子上预敷焊料材料以形成焊料层(步骤S2)。接下来，将半导体元件1的元器件侧电极端子与电路基板6的基板侧电极端子的位置对准，并在电路基板6上安装半导体元件1后(步骤S3)，利用底部填充物将半导体元件1与电路基板6之间的空隙填充(步骤S4)。
利用图3对该半导体装置的一个制造方法的例子进行详细说明。图3是用于对本发明的实施方式1中的半导体装置的制造方法按工序分别进行说明的示意图。
首先，对形成UBM的工序进行说明。在该工序中，如图3(a0)、图3(a1)所示，利用非电解电镀法在半导体元件1的第1元器件侧电极端子3a、第2元器件侧电极端子3b以及假电极3c上形成第1突起状电极5a、第2突起状电极5b以及假突起状电极5c。具体而言，在去除电极表面的杂质以后，将半导体元件1浸渍于锌电镀敷中，从而进行将电极材料的Al置换成Zn的置换反应。接下来，在去除Zn核后，再次将半导体元件1浸入锌电镀液中，使更细微的Zn核在电极材料Al上生长。接下来，将半导体元件1浸渍于Ni－P电镀液中来溶解Zn，并使Ni－P皮膜在电极材料Al上生长。此后，将半导体元件1浸渍于非电解电镀液中并使Au皮膜在Ni－P皮膜上生长。由此，形成了由非电解电镀金属组成的突起状电极。
在该形成UBM的工序中，如图3(a2)所示，由于假电极3c与第1元器件侧电极端子3a的总面积比第2元器件侧电极端子3b的面积大，因此在电镀液中发生电位差，从而使第1元器件侧电极端子3a中的电子交换比第2元器件侧电极端子3b中的更活跃，该第1元器件侧电极端子3a与该假电极3c电连接。因此，第1元器件侧电极端子3a中的Zn核的生长比在第2元器件侧电极端子3b中的进展更快，并且Ni－P皮膜或Au皮膜也是在第1元器件侧电极端子3a中的生长比在第2元器件侧电极端子3b中的生长更快。在非电解电镀中，由于生长是在高度方向与水平方向上以一定比例进行的，因此第1突起状电极5a的直径与高度均比第2突起状电极5b的大。
在该实施方式1中，第2突起状电极5b的高度为8μm，直径为31μm，与此相对，第1突起状电极5a的高度为10μm，直径为35μm，从而第1突起状电极5a比第2突起状电极5b高2μm。这样，在该实施方式1中，使配置于与半导体元件1边角部相对应的位置上的突起状电极5a比配置于与半导体元件1边角部相对应的位置不同的位置上的其它突起状电极5b更高。另外，假突起状电极5c的面积是第1突起状电极5a面积(从高度方向上看第1突起状电极5a时的投影面积)的100倍以上。
接下来，对在基板侧电极端子上涂敷焊料材料的工序进行说明。在该工序中，如图3(b)所示，在基板侧电极端子7a、7b上形成有焊料涂敷层8’，该基板侧电极端子7a、7b位于电路基板6的主面上。具体而言，将电路基板6浸渍于粘性添加化合物中。接下来，在将微小的焊料粒子均匀地撒到电路基板6上，随后清洗电路基板6。由此，在基板侧电极7a、7b上添加微小焊料粒子。此后，在添加有微小焊料粒子的基板侧电极7a、7b上涂布助焊剂并将电路基板6放入回流炉中，使焊料粒子熔融。由此形成焊料涂敷层8’。
此外，焊料涂敷层也可以通过将均匀地排列有细微焊料粉末的焊料转印片的焊料面与半导体元件1重叠使得与形成在半导体元件1上的突起状电极5a、5b相对，并对焊料转印片进行加热，向半导体元件1施加压力，从而在突起状电极5a、5b上对焊料粒子进行转印并制作。
接下来，对在电路基板6上安装半导体元件1的工序进行说明。在该工序中，如图3(c)所示，将半导体元件1与电路基板6的位置对准使得半导体元件1的第1突起状电极5a及第2突起状电极5b、与电路基板6的第1基板侧电极端子7a及第2基板侧电极端子7b相对。此后，对半导体元件1进行加热的同时对电路基板6施加压力，从而将半导体元件1装载到电路基板6上。此时，以焊料熔点以上的温度对焊料涂敷层8’进行加热。因此，焊料涂敷层8’熔融，使第1突起状电极5a与第1基板侧电极端子7a之间，以及第2突起状电极5b与及第2基板侧电极端子7b之间接合。此后，如图3(d)所示，使用涂布装置，将密封树脂9填充于半导体元件1与电路基板6之间的空隙中。
根据如上说明的半导体装置，由于第1突起状电极5a比第2突起状电极5b更高，因此包含第1突起状电极5a在内的接合部的接合间隙A比包含第2突起状电极5b在内的接合部的接合间隙B更大。其结果是，即使在对使用low－k膜或ULK膜等脆弱的低介电常数绝缘膜以作为层间绝缘膜的半导体元件在电路基板上进行倒装芯片安装的情况下，也能确保优异的连接可靠性。
具体而言，在将半导体元件1安装到电路基板6的工序中焊料熔融后的冷却过程中，由于半导体元件1与电路基板6的弹性率及线膨胀系数不同，从而在半导体元件1的边角部分的附近容易产生电路基板的翘曲，其结果是，接合部垂直方向(拉伸方向)上的拉伸在半导体元件1的边角部附近的接合部最大。因此，在以往，半导体元件1与电路基板6之间的接合间隙相等的情况下，具体如图4(a)所示那样，半导体元件1的边角部附近的第1突起状电极5a的高度、与配置于与半导体元件1的边角部附近不同的位置上的第2突起状电极5b的高度相等，并且包含第1突起状电极5a在内的接合部的接合间隙A、与包含第2突起状电极5b在内的接合部的接合间隙B相等，在该情况下，若将接合部的弹性率近似设为E，将半导体元件1的边角部附近的接合部的冷却过程中的拉伸量设为l，则半导体元件1的边角部附近的接合部所承受的应力为E×l/B。该应力传递给位于元器件侧电极端子3a正上方的脆弱的低介电常数绝缘膜2。该应力超过了低介电常数绝缘膜2的破坏应力。因此，在低介电常数绝缘膜2的界面上低介电常数绝缘膜2产生剥离或裂缝。
另一方面，在该实施方式1中，如图4(b)所示，半导体元件1边角部附近的第1突起状电极5a比配置于与半导体元件1的边角部附近不同的位置上的第2突起状电极5b更高。由此，包含第1突起状电极5a在内的接合部的接合间隙A、与包含第2突起状电极5b在内的接合部的接合间隙B的关系有A＞B。因此，半导体元件1边角部附近的接合部所承受的应力为E×l/A，比以往更小。其结果是，由于半导体元件1边角部附近的接合部所承受的应力在脆弱的低介电常数绝缘膜2的破坏应力以下，因此能够在低介电常数绝缘膜2的界面上防止低介电常数绝缘膜2产生剥离或裂缝。
如上所述，能够通过在将半导体元件安装到电路基板上的工序中，使构成配置于半导体元件与电路基板之间间隙最大的部位上的接合部的突起装电极的高度、比构成配置于其它部位上的接合部的突起状电极更高，从而减小脆弱的低介电常数绝缘膜所承受的应力，并确保较高的连接可靠性。
(实施方式2)
图5(a)是示意性地表示本发明的实施方式2中的半导体装置的主要部分的剖视图。另外，图5(b)是示意性地表示本发明的实施方式2中的电路基板的主要部分的俯视图，即从形成有基板侧电极端子的主面一侧观察电路基板。
作为电路基板10能够使用例如：玻璃环氧多层基板、芳族聚酰胺多层基板或者硅基板等。在电路基板10中，例如由Al－Si－Cu等组成的基板侧电极端子11被等间隔地设置成矩阵状。
多个基板侧电极端子11包含：第1基板侧电极端子11a；第2基板侧电极端子11b；以及第3基板侧电极端子11c，该第3基板侧电极端子11c配置于与该第1、第2基板侧电极端子11a及11b不同的位置上。第1基板侧电极端子11a配置于与安装在电路基板10上的半导体元件的边角部相对应的位置。沿着配置有多个基板侧电极端子11的区域的周向，与第1基板侧电极端子11a相邻地配置有第2基板侧电极端子11b。另外，在配置有多个基板侧电极端子11的区域的外侧设置有面积比基板侧电极端子11大的第1假电极11d及第2假电极11e。第1假电极11d的面积比及第2假电极11e大，并且经由布线11ad与第1基板侧电极端子11a电连接。另外，第2假电极11e经由布线11be与第2基板侧电极端子11b电连接。例如，也可以使第1基板侧电极端子11a、第2基板侧电极端子11b、第3基板侧电极端子11c、第1假电极11d、第2假电极11e、布线11ad以及布线11be在同一平面内。第1基板侧电极端子11a、第2基板侧电极端子11b、第3基板侧电极端子11c、第1假电极11d、第2假电极11e、布线11ad以及布线11be中的任一个均可以由例如Al－Cu或Al－Si－Cu组成。
另外，在电路基板10上设置有覆盖其主面的绝缘膜12。绝缘膜12具有多个开口部，该开口部使第1基板侧电极端子11a、第2基板侧电极端子11b、第3基板侧电极端子11c、第1假电极11d以及第2假电极11e均至少露出一部分，且将电路基板10的主面上的布线覆盖。绝缘膜12例如由Si3N4组成。
另外，在第1基板侧电极端子11a、第2基板侧电极端子11b、第3基板侧电极端子11c、第1假电极11d以及第2假电极11e上分别设有第1突起状电极13a、第2突起状电极13b、第3突起状电极13c、第1假突起状电极13d以及第2假突起状电极13e。第1突起状电极13a、第2突起状电极13b、第3突起状电极13c、第1假突起状电极13d以及第2假突起状电极13e由经过例如Ni－P/Au或Ni－Au等焊料浸润后的金属组成。
另一方面，在半导体元件14的电极面(主面)内侧的层设置有多层布线层，该多层布线层包含：由例如Cu或Al组成的细微布线层、以及比例如ULK膜还脆弱的Extremelylow－k膜等低介电常数绝缘膜15，在该多层布线层的最表面上对作为元器件侧电极端子的焊料凸点16进行区域配置使得与电路基板10的基板侧电极端子11相对。焊料凸点16例如由Sn－Ag、Sn－Ag－Cu、Sn－Bi等组成。
半导体元件14安装在电路基板10上，利用焊料使半导体元件14的焊料凸点16与电路基板10的第1突起状电极11a、第2突起状电极11b、第3突起状电极11c接合，并电连接或机械连接。另外，在半导体元件14与电路基板10之间填充有密封树脂17。
在该实施方式2中，半导体元件14的焊料凸点16的间距为40μm的间距。另外，电路基板10的基板侧电极端子11的绝缘膜12的开口部呈直径为12μm的圆形。另外，电路基板10的第1假电极11d的绝缘膜12的开口部呈800μm×800μm的正方形，电路基板10的第2假电极11e的绝缘膜12的开口部呈400μm×400μm的正方形。
接下来，利用图6对上述半导体装置的一个制造方法的例子进行说明。图6是用于对本发明的实施方式2中的半导体装置的制造方法按工序分别进行说明的示意图。
首先，如图6(a)、图6(b)所示，通过非电解镀金法在电路基板10的第1基板侧电极端子11a、第2基板侧电极端子11b、第3基板侧电极端子11c、第1假电极11d以及第2假电极11e上形成第1突起状电极13a、第2突起状电极13b、第3突起状电极13c、第1假突起状电极13d以及第2假突起状电极13e。具体而言，在去除电极表面的杂质以后，将电路基板10浸渍于锌电镀液中，从而进行将电极材料的Al置换成Zn的置换反应。接下来，在去除Zn核后，再次将电路基板10浸渍于锌电镀液中，使更细微的Zn核在电极材料Al上生长。接下来，将电路基板10浸渍于Ni－P电镀液中来溶解Zn，并使Ni－P皮膜在电极材料Al上生长。此后，将电路基板10浸渍于非电解电镀液中并使Au皮膜在Ni－P皮膜上生长。由此，形成了由非电解电镀金属组成的突起状电极。
在该工序中，如图5(b)所示，由于第1假电极11d的面积比第2假电极11e的面积大，因此在与第1模拟电解11d电连接的第1基板侧电极端子11a中进行的电镀的生长速度比在与第2模拟电解11e电连接的第2基板侧电极端子11b中更快。另外，由于第2假电极11e的面积比基板侧电极端子11的面积大，因此在第2基板侧电极端子11b中进行的电镀的生长速度比在未与第1、第2假电极11d及11e电连接的第3基板侧电极端子11c中更快。其结果是，如图6(b)所示，突起状电极的高度按第3突起状电极13c、第2突起状电极13b、第1突起状电极13a的顺序依次变高。
如上所述，在该实施方式2所涉及的半导体装置的制作方法中，与前述的实施方式1相同，使用非电解电镀法通过假电极的面积对电子的交换进行控制。在该实施方式2中，第1突起状电极13a、第2突起状电极13b以及第3突起状电极13c的高度分别为10μm、9μm、8μm。这样，在该实施方式2中，使配置于与半导体元件14边角部相对应的位置上的第1突起状电极13a、以及与第1突起状电极13a相邻的第2突起状电极13b的高度，比配置于与第1突起状电极13a及第2突起状电极13b不同的位置上的第3突起状电极13c更高。另外，第1假突起状电极13d的面积是第1突起状电极13a的面积(从高度方向看第1突起状电极13a时的投影面积)的10000倍以上，第2假突起状电极13e的面积是第2突起状电极13b的面积(从高度方向看第2突起状电极13b时的投影面积)的100倍以上。
接下来，如图6(c)所示，提供密封树脂17以将电路基板10上的第1突起状电极13a、第2突起状电极13b以及第3突起状电极13c覆盖。例如，将NCF(非导电性薄膜)粘贴于电路基板10上，或利用涂布将NCP(非导电糊料)提供给电路基板10即可。
接下来，如图6(d)所示，将半导体元件14与电路基板10的位置对准使得电路基板10的第1突起状电极13a、第2突起状电极13b以及第3突起状电极13c与半导体元件14的焊料凸点16相对。此后，对半导体元件14进行加热的同时对电路基板10施加压力，从而将半导体元件14装载到电路基板10上。此时，以焊料熔点以上的温度对焊料凸点16进行加热。因此，焊料凸点16熔融，并且焊料凸点16与第1突起状电极13a、第2突起状电极13b以及第3突起状电极13c接合。此后，密封树脂17的硬化反应开始。为了使密封树脂17的硬化反应彻底结束，也可以再将密封树脂17放在回流炉中加热。
在该实施方式2中，低介电常数绝缘膜比前述的实施方式1更脆弱，且元器件侧电极端子(焊料凸点16)间的间距也更窄。因此，如果所有突起状电极的高度相等，则由于在将半导体元件14安装到电路基板10的步骤中的冷却过程中，半导体元件14与电路基板10的弹性率及线膨胀系数不同，从而不仅使半导体元件14边角部的接合部所承受的应力，还使得与该边角部的接合部相邻的接合部所承受的应力的大小也超过脆弱的低介电常数绝缘膜15的破坏强度。因此，在低介电常数绝缘膜15的界面上低介电常数绝缘膜15产生剥离或裂缝。
与此相对，根据该实施方式2，突起状电极的高度按第3突起状电极13c、与半导体元件1边角部相邻的第2突起状电极13b、位于半导体元件1边角部的第1突起状电极13a的顺序依次变高。由此，半导体元件1边角部的接合部与以往相比，在与该边角部的接合部相邻的接合部上，在冷却过程中所承受的应力有所缓和。由此，即使在对具有脆弱的低介电常数绝缘膜且电极端子间间距狭窄的半导体元件进行倒装安装的情况下，也能够防止低介电常数绝缘膜产生剥离或裂缝。
通过截面研究，对上面说明的半导体装置进行了截面解析，其结果是，能够确认半导体元件与电路基板的间隔在半导体元件的边角部最大，并且脆弱的低介电常数绝缘膜没有发生剥离及裂缝。另外，对半导体装置进行温度周期测试(1个周期：－45℃、85℃、各30分钟)的结果为：1000个周期后能够确保连接电阻的稳定。
如上所述，对与上述的实施方式1相比电极端子间间距狭窄且低介电常数绝缘膜脆弱的半导体元件进行安装倒装芯片，即使再此情况下，通过阶段性地改变突起状电极的高度，从而能够将低介电常数绝缘膜所承受的应力减小、并确保较高的连接可靠性。
此外，这里，对将突起状电极的高度设定成3个阶段的情况进行了说明，但是也可以设定成3个阶段以上。通过将突起状电极的高度设定成3个阶段以上，从而能够适用于更加脆弱的元件、以及翘曲更大的基板。
另外，这里，对将突起状电极的高度设定成3个阶段的情况进行了说明，与上述的实施方式1相同，也可以仅使设置在基板上的突起状电极中的与半导体元件的边角部相对应的突起状电极比其它突起状电极更高。与此相反的，在上述的实施方式1中，与该实施方式2相同，也可以将设置在半导体元件上的突起状电极的高度设定成3个阶段以上。
(实施方式3)
图7(a)是示意性地表示本发明的实施方式3中的电子元件的主要部分的剖视图。图7(b)是示意性地表示本发明的实施方式3中的电子元件的主要部分的俯视图，即从形成有元器件侧电极端子的主面(电极面)一侧观察半导体元件。图7(c)是示意性地表示本发明的实施方式3中的半导体装置的主要部分的剖视图。此外，与在上述实施方式1中说明了的构件相对应的构件对其赋予相同的符号，并适当省略对其的说明。
如图7(a)、图7(b)所示，在半导体元件1电极面内侧的层设置有多层布线层，该多层布线层包含：例如由Cu或Al组成的细微布线层以及例如ULK膜等脆弱的低介电常数绝缘膜2，在该多层布线层的最表面上以40μm的间距等间隔地对多个元器件侧电极端子3进行区域配置。
多个元器件侧电极端子3包含：第1元器件侧电极端子3a；第2元器件侧电极端子3b，该第2元器件侧电极端子3b配置于与第1元器件侧电极端子3a不同的位置上。在该实施方式3中，第1元器件侧电极端子3a不仅位于与半导体元件1的边角部相对应的位置上，还配置于配置有多个元器件侧电极端子3的区域的中央部。另外，在配置有多个元器件侧电极端子3的区域的外侧设置有焊盘18，并通过布线19将第1元器件侧电极端子3a与焊盘18连接使其导通。
另外，在半导体元件1上设置有覆盖其电极面的绝缘膜4。绝缘膜4将与元器件侧电极端子3位于同一平面内的布线以及焊盘18覆盖，且具有多个开口部，该开口部使各元器件侧电极端子3的中央部露出。绝缘膜4例如由Si3N4组成。在未由元器件侧电极端子3的绝缘膜4覆盖的区域上设置有称作UBM的突起状电极5。突起状电极5由形成在第1元器件侧电极端子3a上的第1突起状电极5a、以及形成在第2元器件侧电极端子3b上的第2突起状电极5b组成。第1突起状电极5a及第2突起状电极5b通过非电解电镀法形成，突起从第1突起状电极5a电极表面的高度比从第2突起状电极5b电极表面的高度更高。
另一方面，在与半导体元件1的电极面相反的一面上设置有假电极20。在该实施方式3中，设置有3mm×3mm的正方形的假电极20。该假电极20通过贯穿孔21与焊盘18电连接。贯穿孔21由电镀金属填充。焊盘18与假电极20由例如Ni－P/Au皮膜组成。Ni－P/Au例如通过非电解电镀法形成。填充贯穿孔21的电镀金属由例如Cu组成。在焊盘18、假电极20以及贯穿孔21的界面上可以设置例如由Ti或W等组成的片层。
另外，由图7(c)所示，安装半导体元件1的电路基板6在其主面上具有配置成使得分别与半导体元件1的突起状电极相对的基板侧电极端子。作为电路基板6能够使用例如：玻璃环氧多层基板、芳族聚酰胺多层基板或者硅基板等。半导体元件1的突起状电极与电路基板6的基板侧电极端子由焊料接合并电导通，半导体元件1与电路基板6之间注入有密封树脂9。
根据该实施方式3，为了使假电极20与元器件侧电极端子不在同一面内，可以使半导体元件1的面积比上述的实施方式1更小。另外，由于位于半导体元件1的边角部的突起状电极5a比未与假电极20电连接的突起状电极5b更高，因此与上述的实施方式1相同，能够防止脆弱的低介电常数绝缘膜发生剥离及破坏。
另外，由于假电极20设置于与半导体元件1的电极面相反一侧的面上，因此能够将假电极20与散热板、散热片等散热源连接。在半导体元件的电极端子间间距狭窄的情况下，由于接合部的截面积微小，因此增加了来自接合部的发热量。另外，若半导体元件的电极端子间间距狭窄，则来自接合部的散热性将恶化。特别是，位于配置有多个元器件侧电极端子的区域的中央部的接合部的散热性将恶化。与此相对，在该实施方式3中，由于与假电极20电连接的元器件侧电极端子3a也设置于配置有多个元器件侧电极端子的区域的中央部，因此如果将假电极20与散热源连接，则可以散去不易散去的中央部上的热。因此，即使在微小的接合部的截面积流过大电流的情况下也能进行散热。这是由于，该实施方式3中的半导体元件对电极端子间距正趋于狭窄化的半导体元件是有用的。
另外，由于突起状电极通过非电解电镀法形成，因此与假电极20电连接的突起状电极5a不仅高度直径也比未与假电极20电连接的突起状电极5b更大。在该实施方式3中，第1突起状电极5a的高度为12μm、平均直径为29μm，与此相对，第2突起状电极5b的高度为10μm、平均直径为25μm，第1突起状电极5a与第2突起状电极5b相比，高度高2μm、平均直径长4μm。因此，如果将假电极20与供电源连接，则能够使流过大电流的供电端子的直径比非供电端子的其它突起状电极更大。由此，可以防止电迁移等问题。
如上所述，根据该实施方式3，能够不增大半导体元件的面积及半导体封装，并将脆弱的低介电常数绝缘膜所承受的应力减小，以确保较高的连接可靠性。
(实施方式4)
图8(a)～图8(d)是示意性地表示本发明的实施方式4中的电子元件的主要部分的俯视图，即，从未形成有元器件侧电极端子的主面(电极面)一侧观察半导体元件。此外，与在上述实施方式1中说明了的构件相对应的构件对其赋予相同的符号，并适当省略对其说明。
如图8(a)～图8(d)所示，也可以使与第1突起状电极5a电连接的假突起状电极5c具有起到位置校正用识别标记的作用的形状，该位置校正用识别标记在安装倒装芯片时由图像识别摄像头拍摄得到。
此外，在该实施方式4中，与上述的实施方式1相同，在配置有多个元器件侧电极端子3的区域的外侧设置面积相同的一种假突起状电极5c，并对此情况进行了说明，如实施方式2中说明的那样，在设置面积互异的多种假突起状电极的情况下，能够使多种假突起状电极中的至少一些具有识别标记的作用。
在上面的各个实施方式中，作为电子元器件以半导体元件为例进行了说明，但不局限于此，例如，在将电极端子间间距狭窄的电容器、电感、电阻等电子元器件安装到基板上的情况下同样也能够实施。
工业上的实用性
本发明所涉及的电子元器件安装体、电子元器件以及基板能够提高电子元器件与基板的连接可靠性，并且在将电子端子趋于窄距化的半导体元件、具有由低介电常数材料等组成的层间绝缘膜的半导体元件等半导体元件安装到基板上的安装领域中特别有效。

Claims (26)

1.一种电子元器件安装体，在基板上安装有包括多个元器件侧电极端子的电子元器件，该基板包括与所述多个元器件侧电极端子相对应的多个基板侧电极端子，该电子元器件安装体的特征在于，包括：
多个突起状电极，该多个突起状电极分别形成于所述电子元器件的所述多个元器件侧电极端子上且与所述电子元器件及所述基板电连接；以及
假电极，该假电极形成于所述电子元器件上且与所述多个元器件侧电极端子中的预定位置上的元器件侧电极端子电连接，
与所述假电极电连接的所述预定位置上的元器件侧电极端子上的所述突起状电极比与所述预定位置不同的位置上的元器件侧电极端子上的所述突起状电极更高。
2.如权利要求1所述的电子元器件安装体，其特征在于，
所述假电极与所述多个元器件侧电极端子中的配置于与所述电子元器件的边角部相对应的位置上的元器件侧电极端子电连接。
3.如权利要求1所述的电子元器件安装体，其特征在于，
所述假电极包含面积互不相同的多种假电极，
进行电连接的假电极的面积越大，与所述假电极电连接的元器件侧电极端子上的所述突起状电极的高度越高。
4.如权利要求3所述的电子元器件安装体，其特征在于，
所述假电极包含：
第1假电极，该第1假电极与第1元器件侧电极端子电连接，该第1元器件侧电极端子配置在与所述电子元器件的边角部相对应的位置上；以及
第2假电极，该第2假电极的面积比所述第1假电极小，并且与第2元器件侧电极端子电连接，该第2元器件侧电极端子与所述第1元器件侧电极端子相邻，
所述第1元器件侧电极端子上的所述突起状电极比所述第2元器件侧电极端子上的所述突起状电极更高。
5.如权利要求1所述的电子元器件安装体，其特征在于，
所述假电极形成于所述电子元器件的与配置有所述多个元器件侧电极端子的面不同的面上。
6.如权利要求5所述的电子元器件安装体，其特征在于，
所述假电极与所述多个元器件侧电极端子中的配置于与所述电子元器件的边角部相对应的位置上的元器件侧电极端子电连接。
7.如权利要求6所述的电子元器件安装体，其特征在于，
所述多个元器件侧电极端子配置成矩阵状，所述假电极与配置有所述多个元器件侧电极端子的区域的中央部上的元器件侧电极端子电连接。
8.如权利要求5所述的电子元器件安装体，其特征在于，
所述假电极与电源端子连接。
9.如权利要求5所述的电子元器件安装体，其特征在于，
所述假电极与散热源连接。
10.如权利要求1所述的电子元器件安装体，特征在于，
所述假电极形成于配置有所述多个元器件侧电极端子的面上且具有起到位置校正用识别标记的作用的形状。
11.一种电子元器件安装体，在基板上安装有包括多个元器件侧电极端子的电子元器件，该基板包括与所述多个元器件侧电极端子相对应的多个基板侧电极端子，该电子元器件安装体的特征在于，包括：
多个突起状电极，该多个突起状电极分别形成于所述基板的所述多个基板侧电极端子上且与所述电子元器件及所述基板电连接；以及
假电极，该假电极形成于所述基板上且与所述多个基板侧电极端子中的预定位置上的基板侧电极端子电连接，
与所述假电极电连接的所述预定位置上的基板侧电极端子上的所述突起状电极比与所述预定位置不同的位置上的基板侧电极端子上的所述突起状电极更高。
12.如权利要求11所述的电子元器件安装体，其特征在于，
所述假电极与所述多个基板侧电极端子中的配置于与所述电子元器件的边角部相对应的位置上的基板侧电极端子电连接。
13.如权利要求11所述的电子元器件安装体，其特征在于，
所述假电极包含面积互不相同的多种假电极，
进行电连接的假电极的面积越大，与所述假电极电连接的基板侧电极端子上的所述突起状电极的高度越高。
14.如权利要求13所述的电子元器件安装体，其特征在于，
所述假电极包含：
第1假电极，该第1假电极与第1基板侧电极端子电连接，该第1基板侧电极端子配置在与所述电子元器件的边角部相对应的位置上；以及
第2假电极，该第2假电极的面积比所述第1假电极小，并且与第2基板侧电极端子电连接，该第2基板侧电极端子与所述第1基板侧电极端子相邻，
所述第1基板侧电极端子上的所述突起状电极比所述第2基板侧电极端子上的所述突起状电极更高。
15.一种电子元器件，其特征在于，包括：
多个元器件侧电极端子；
假电极，该假电极与所述多个元器件侧电极端子中的预定位置上的元器件侧电极端子电连接；以及
多个突起状电极，该多个突起状电极分别形成于所述多个元器件侧电极端子上，
与所述假电极电连接的所述预定位置上的元器件侧电极端子上的所述突起状电极比与所述预定位置不同的位置上的元器件侧电极端子上的所述突起状电极更高。
16.如权利要求15所述的电子元器件，其特征在于，
所述假电极与所述多个元器件侧电极端子中的配置于与该电子元器件的边角部相对应的位置上的元器件侧电极端子电连接。
17.如权利要求15所述的电子元器件，其特征在于，
所述假电极包含面积互不相同的多种假电极，
进行电连接的假电极的面积越大，与所述假电极电连接的元器件侧电极端子上的所述突起状电极的高度越高。
18.如权利要求17所述的电子元器件，其特征在于，
所述假电极包含：
第1假电极，该第1假电极与第1元器件侧电极端子电连接，该第1元器件侧电极端子配置在与该电子元器件的边角部相对应的位置上；以及
第2假电极，该第2假电极的面积比所述第1假电极小，并且与第2元器件侧电极端子电连接，该第2元器件侧电极端子与所述第1元器件侧电极端子相邻，
所述第1元器件侧电极端子上的所述突起状电极比所述第2元器件侧电极端子上的所述突起状电极更高。
19.如权利要求15所述的电子元器件，其特征在于，
所述假电极形成于与配置有所述多个元器件侧电极端子的面不同的面上。
20.如权利要求19所述的电子元器件，其特征在于，
所述假电极与所述多个元器件侧电极端子中的配置于与该电子元器件的边角部相对应的位置上的元器件侧电极端子电连接。
21.如权利要求20所述的电子元器件，其特征在于，
所述多个元器件侧电极端子配置成矩阵状，所述假电极与配置有所述多个元器件侧电极端子的区域的中央部上的元器件侧电极端子电连接。
22.如权利要求15所述的电子元器件，其特征在于，
所述假电极形成于配置有所述多个元器件侧电极端子的面上且具有起到位置校正用识别标记的作用的形状。
23.一种基板，其特征在于，包括：
多个基板侧电极端子；
假电极，该假电极与所述多个基板侧电极端子中的预定位置上的基板侧电极端子电连接；以及
多个突起状电极，该多个突起状电极分别形成于所述多个基板侧电极端子上，
与所述假电极电连接的所述预定位置上的基板侧电极端子上的所述突起状电极比与所述预定位置不同的位置上的基板侧电极端子上的所述突起状电极更高。
24.如权利要求23所述的基板，其特征在于，
所述假电极与所述多个基板侧电极端子中的配置于与在该基板上安装着的电子元器件的边角部相对应的位置上的基板侧电极端子电连接。
25.如权利要求23所述的基板，其特征在于，
所述假电极包含面积互不相同的多种假电极，
进行电连接的假电极的面积越大，与所述假电极电连接的基板侧电极端子上的所述突起状电极的高度越高。
26.如权利要求25所述的基板，其特征在于，
所述假电极包含：
第1假电极，该第1假电极与第1基板侧电极端子电连接，该第1基板侧电极端子配置于与安装在该基板上的电子元器件的边角部相对应的位置上；以及
第2假电极，该第2假电极的面积比所述第1假电极小，并且与第2基板侧电极端子电连接，该第2基板侧电极端子与所述第1基板侧电极端子相邻，
所述第1基板侧电极端子上的所述突起状电极比所述第2基板侧电极端子上的所述突起状电极更高。
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US20130170165A1 (en) 2013-07-04
JPWO2012073417A1 (ja) 2014-05-19
JP5562438B2 (ja) 2014-07-30
CN103098191A (zh) 2013-05-08
WO2012073417A1 (ja) 2012-06-07
KR20130041208A (ko) 2013-04-24

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