CN103095447B - A kind of bpsk signal synchronous circuit suitable for ISO14443 agreements - Google Patents
A kind of bpsk signal synchronous circuit suitable for ISO14443 agreements Download PDFInfo
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- CN103095447B CN103095447B CN201110340177.2A CN201110340177A CN103095447B CN 103095447 B CN103095447 B CN 103095447B CN 201110340177 A CN201110340177 A CN 201110340177A CN 103095447 B CN103095447 B CN 103095447B
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Abstract
The invention discloses a kind of bpsk signal synchronous circuit suitable for ISO14443 agreements, comprising：One RF modules, for receiving the radiofrequency signal and recovered clock signal with data message；One digital phase-locked loop, for the bpsk signal that synchronous local clock and RF modules are produced；One decoder module, for the decoding of bpsk signal；One phase inverter, for negating to enabling signal.The bpsk signal synchronous circuit of the present invention can make local clock synchronous with the bpsk signal of reception, beneficial to being correctly decoded to bpsk signal.
Description
Technical field
The present invention relates to contactless card field, more particularly to a kind of bpsk signal suitable for ISO14443 agreements is together
Step circuit.
Background technology
In the regulation of ISO14443 agreements, BPSK (Binary Phase Shift Keying) signal can with office when
Carve and return, and unlike the Synchronization of type-A, must be closed into multiple with ETU in regulation using Synchronization
System, and there is no such restriction in BPSK, bpsk signal can be returned at any time.So at card reader end, during decoding just
There is a synchronization, and due to the impact of the reasons such as dutycycle, cumulative errors, it is easy to can cause to misread asking for code
Topic.
Content of the invention
The technical problem to be solved in the present invention is to provide a kind of bpsk signal synchronous circuit suitable for ISO14443 agreements
Local clock can be made synchronous with the bpsk signal for receiving, beneficial to being correctly decoded to bpsk signal.
For solve above-mentioned technical problem, the present invention bpsk signal synchronous circuit, comprising：
One RF modules, for receiving radio frequency (RF) signal and recovered clock signal with data message；
One digital phase-locked loop, for the bpsk signal that synchronous local clock and RF modules are produced；
One decoder module, for the decoding of bpsk signal；
One phase inverter, for negating to enabling signals DP LL_EN.
The RF signals are the bpsk signals based on ISO/IEC14443 agreements.
The digital phase-locked loop can use general digital phase-locked loop；
The decoder module can use general BPSK decoding circuits；
Phase error and the locking time that can be adjusted when locking.
The bpsk signal synchronous circuit of the present invention uses digital phase-locked loop, synchronizes local during signal is enabled
Phase relation between 847K clocks and the bpsk signal that receives, so after signal is enabled, it is possible to after using synchronization
847K clocks bpsk signal is decoded.After the synchronization of digital phase-locked loop, eliminate local clock and receive
The phase indeterminacy of bpsk signal, makes both phase relation fix.
The bpsk signal synchronous circuit of the present invention can make local clock synchronous with the bpsk signal of reception, beneficial to believing to BPSK
Number be correctly decoded.
Description of the drawings
The present invention is further detailed explanation with specific embodiment below in conjunction with the accompanying drawings：
Fig. 1 is the electrical block diagram of one embodiment of the invention.
Description of reference numerals
100 be RF modules 110 be digital phase-locked loop
120 be decoder module 130 be phase inverter.
Specific embodiment
As shown in figure 1, one embodiment of the invention includes：RF modules 100, digital phase-locked loop 110, decoder module 120, fall
Phase device 130；
RF modules 100, for sending and receiving RF signals and recovered clock signal with data message, complete to demodulate
Afterwards, digital phase-locked loop 110 and follow-up decoder module are given by the signal according to ISO14443 communications protocol coding for receiving
120；
Digital phase-locked loop 110, using general digital PLL circuit, its clock signal is recovered using RF modules 110
Clock signal, after synchronization, pause (time-out) signal phase of the generation of local clock clk847 and RF module 110 for obtaining
Fixed；Digital phase-locked loop 110 can change the phase when tracing step of digital phase-locked loop and locking by input signal Kmode
Position error, the modulus value of input signal Kmode can change, and the size of modulus value determines the tracing step of digital phase-locked loop, modulus value
Bigger, tracing step is less, and phase error during locking is less, but capture time is longer；Conversely, modulus value is less, tracing step
Bigger, the phase error of locking is bigger, but capture time is less；
Decoder module 120, is produced to RF modules 100 using the synchronised clock clk847 obtained through digital phase-locked loop 110
Pause signals be decoded, which uses general BPSK decoding circuits；
Phase inverter 130, enters line phase to input enable signals DP LL_EN and negates, must enable signals DP LL_EN works before negating
For the enable signal of digital phase-locked loop 110, enable signal of the signal of the inverted as decoder module 120, i.e., when both are different
Work, after need to synchronously completing, decoder module 120 is just started working.
The present invention has been described in detail above by specific embodiment and embodiment, but these not constitute right
The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Enter, these also should be regarded as protection scope of the present invention.
Claims (5)
1. a kind of bpsk signal synchronous circuit suitable for ISO14443 agreements, it is characterised in that include：
One RF modules, for receiving the radiofrequency signal and recovered clock signal with data message；
One digital phase-locked loop, for the bpsk signal that synchronous local clock and RF modules are produced, its clock signal uses RF modules
Recovered clock signal, after synchronization, the local clock for obtaining and the halt signal phase place of RF modules are fixed；Digital phase-locked loop
Phase error when changing the tracing step of digital phase-locked loop by input signal and locking, the modulus value of input signal can change
Become；
One decoder module, for the decoding of bpsk signal, is produced to RF modules using the synchronised clock obtained through digital phase-locked loop
Raw halt signal is decoded；
One phase inverter, negates for entering line phase to enable signal, enable of the enable signal before negating as digital phase-locked loop
Signal, enable signal of the signal of the inverted as decoder module.
2. bpsk signal synchronous circuit as claimed in claim 1, it is characterised in that：RF signals are assisted based on ISO/IEC14443
The bpsk signal of view.
3. bpsk signal synchronous circuit as claimed in claim 1, it is characterised in that：Digital phase-locked loop can use general numeral
Phaselocked loop.
4. bpsk signal synchronous circuit as claimed in claim 1, it is characterised in that：Decoder module can use general BPSK to solve
Code circuit.
5. bpsk signal synchronous circuit as claimed in claim 3, it is characterised in that：Phase error and lock when locking can be adjusted
Fix time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110340177.2A CN103095447B (en) | 2011-11-01 | 2011-11-01 | A kind of bpsk signal synchronous circuit suitable for ISO14443 agreements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110340177.2A CN103095447B (en) | 2011-11-01 | 2011-11-01 | A kind of bpsk signal synchronous circuit suitable for ISO14443 agreements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103095447A CN103095447A (en) | 2013-05-08 |
| CN103095447B true CN103095447B (en) | 2017-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110340177.2A Active CN103095447B (en) | 2011-11-01 | 2011-11-01 | A kind of bpsk signal synchronous circuit suitable for ISO14443 agreements |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110135548B (en) * | 2019-05-21 | 2024-12-10 | 上海明矽微电子有限公司 | A digital circuit device for high-frequency radio frequency identification chip demodulation blind area processing |
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2011
- 2011-11-01 CN CN201110340177.2A patent/CN103095447B/en active Active
Non-Patent Citations (1)
| Title |
|---|
| 载频为13.56MHz的非接触式IC卡读写模块研究;庞学骏;《中国优秀硕士论文电子期刊网》;20060815;摘要、正文第1.4-1.5，4.2，4.4-4.5节、图4.1 * |
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| CN103095447A (en) | 2013-05-08 |
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