CN103094214B - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN103094214B CN103094214B CN201110344432.0A CN201110344432A CN103094214B CN 103094214 B CN103094214 B CN 103094214B CN 201110344432 A CN201110344432 A CN 201110344432A CN 103094214 B CN103094214 B CN 103094214B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 102
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 31
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 124
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- 239000013078 crystal Substances 0.000 claims description 38
- 230000008878 coupling Effects 0.000 claims description 13
- 238000010168 coupling process Methods 0.000 claims description 13
- 238000005859 coupling reaction Methods 0.000 claims description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 9
- 229910021529 ammonia Inorganic materials 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 3
- 230000035484 reaction time Effects 0.000 claims description 3
- 125000004430 oxygen atom Chemical group O* 0.000 abstract description 7
- 238000005530 etching Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000011982 device technology Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 150000002829 nitrogen Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method for a semiconductor device. The manufacturing method for the semiconductor device comprises: a) a semiconductor substrate is provided, wherein the semiconductor substrate comprises a P-type transistor area and an N-type transistor area, and a gate dielectric layer and a covering layer are sequentially formed on the semiconductor substrate; b) a photoresist layer which exposes the P-type transistor area is formed on the covering layer; c) nitrogen treatment process is carried out, and nitrogen is mixed in the gate dielectric layer and the covering layer of the P-type transistor area; d) the photoresist layer is removed. By the fact that the nitrogen-atoms are mixed in the gate dielectric layer and the covering layer of the P-type transistor area to replace oxygen atoms at the interface, effective work function value of the covering layer in the P-type transistor area is increased, threshold voltage of a P-type transistor is reduced, so that the covering layer can be matched with work function layers of the P-type transistor area and the N-type transistor area at the same time.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of method making semiconductor device.
Background technology
Along with grid size foreshortens to tens nanometers, the thickness of gate oxide layers is down to below 3nm, has caused that resistance is excessive, grid leak and to increase and the problems such as vague and general phenomenon appear in polysilicon gate.Therefore, sight is invested metal gate technique again by people again, and metal gate technique adopts has more low-resistance metal as grid, and adopts the material with larger dielectric constant as gate dielectric layer.
Metal gate technique comprises and first forms grid (Gate-first) technique and rear formation grid (Gate-last) technique.Gate-first technique refers to leaking silicon chip/source region ion implantation and high-temperature annealing step subsequently before form metal gates, Gate-last technique is then in contrast.Because in Gate-first technique, metal gates need stand high-temperature process, therefore this technique may cause the problems such as thermal stability, threshold voltage shift and the regrowth of grid stack layer, and this is very serious problem for PMOS.
Fig. 1 is the process chart of the Gate-last technique adopting prior art.As shown in Figure 1, perform step 101, Semiconductor substrate is provided, and forms gate dielectric layer and the cover layer of high-k on a semiconductor substrate successively; Perform step 102, on the cover layer deposition of polysilicon layer, and be patterned to form the first dummy grid and the second dummy grid; Perform step 103, in the Semiconductor substrate of the first dummy grid and the second dummy grid both sides, form shallow doped region; Perform step 104, form clearance wall at the first dummy grid and the second dummy grid both sides, and form source electrode and drain electrode in the Semiconductor substrate of clearance wall both sides; Perform step 105, source electrode and drain electrode form metal silicide to reduce contact resistance; Perform step 106, the semiconductor device of step 105 forms interlayer dielectric layer, and carries out chemical mechanical milling tech to exposing the first dummy grid and the second dummy grid; Perform step 107, remove the first dummy grid, and form P type metal gates; Perform step 108, remove the second dummy grid, and form N-type metal gates.
The cover layer that gate dielectric layer is formed not only can as the etching stop layer of polysilicon layer in the Patternized technique of step 102, but also can to remove in dummy grid processes grill-protected dielectric layer from damage at this etching technics and step 107 and 108.But, because N-type metal gates is identical with the cover layer below P type metal gates, if tectal work function is higher, the threshold voltage (Vt) of P-type crystal pipe can be reduced, otherwise, then can reduce the threshold voltage of N-type transistor, therefore, be difficult to take into account N-type transistor and P-type crystal pipe simultaneously.If use midgap (midgap) although material can take into account N-type transistor and P-type crystal pipe work function to a certain extent as cover layer, both threshold voltages can be caused all relatively high.
Therefore, a kind of method making semiconductor device is badly in need of at present, to solve the problem.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method making semiconductor device, comprise: a) provide Semiconductor substrate, described Semiconductor substrate comprises P-type crystal area under control and N-type transistor district, and it is formed with gate dielectric layer and cover layer successively; B) on described cover layer, form the photoresist layer exposing described P-type crystal area under control; C) nitrogen treatment process is performed, with the nitrogen that adulterates in the described gate dielectric layer and described cover layer in described P-type crystal area under control; And d) remove described photoresist layer.
Preferably, the described nitrogen treatment process in described c) step is rapid thermal nitridation process, and wherein, the reacting gas passed into is ammonia.
Preferably, the pressure in reaction chamber is 1-30Torr.
Preferably, reaction temperature is 500-1000
oc.
Preferably, the flow velocity of described ammonia is 1-60sccm.
Preferably, the reaction time is 1-100 second.
Preferably, the described nitrogen treatment process in described c) step comprises a point coupling formula plasma nitridation process, use pulsed power, and the reacting gas passed into comprises nitrogen in described point of coupling formula plasma nitridation process.
Preferably, the pulsed power in described point of coupling formula plasma nitridation process is 100-3000W.
Preferably, the duty ratio of described pulsed power is 0-50%.
Preferably, described nitrogen treatment process also comprises annealing process after described point of coupling formula plasma nitridation process.
Preferably, described nitrogen treatment process is plasma doping process, and wherein, the reacting gas passed into comprises nitrogen.
Preferably, the Implantation Energy of described plasma doping process is 100-2000eV.
Preferably, the implantation dosage of described plasma doping process is 10
11-10
14individual/square centimeter.
Preferably, described method also comprises after described d) step: on described cover layer, form the first dummy grid and the second dummy grid respectively, and wherein, described first dummy grid is positioned at described N-type transistor district, and described second dummy grid is positioned at described P-type crystal area under control; Described cover layer is formed the interlayer dielectric layer surrounding described first dummy grid and described second dummy grid; Remove in described first dummy grid and described second dummy grid and fill metal level, to form the first metal gates; And another removing in described first dummy grid and described second dummy grid also fills metal level, to form the second metal gates.
To sum up, the oxygen atom of interface is replaced by the gate dielectric layer in P-type crystal area under control and tectal interface doping nitrogen-atoms, the tectal effective work function value in P-type crystal area under control can be improved, reduce the threshold voltage of P-type crystal pipe, and then cover layer can be matched with the work-function layer in P-type crystal area under control and N-type transistor district simultaneously.In addition, the part nitrogen-atoms of doping can be diffused in gate dielectric layer, and this part nitrogen-atoms not only can improve the dielectric constant of gate dielectric layer, can also effectively improve equivalent oxide thickness.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the process chart of the Gate-last technique adopting prior art;
Fig. 2 makes semiconductor device technology flow chart according to one embodiment of the present invention;
Fig. 3 A-3H is for making the cutaway view of the device that each step obtains in semiconductor device technology flow process according to one embodiment of the present invention.
Embodiment
Next, by reference to the accompanying drawings the present invention will more intactly be described, shown in the drawings of embodiments of the invention.But the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.
Fig. 2 shows and makes semiconductor device technology flow chart according to one embodiment of the present invention, and Fig. 3 A-3H shows the cutaway view making the device that each step obtains in semiconductor device technology flow process according to one embodiment of the present invention.It should be noted that the part of devices structure in semiconductor device can be manufactured by CMOS Making programme, therefore before method of the present invention, among or extra technique can be provided afterwards, and wherein some technique only does simple description at this.Manufacture method of the present invention is described in detail below in conjunction with Fig. 2 and Fig. 3 A-3H.
Perform step 201, provide Semiconductor substrate, this Semiconductor substrate comprises P-type crystal area under control and N-type transistor district, and it is formed with gate dielectric layer and cover layer successively.
As shown in Figure 3A, Semiconductor substrate 300 comprises P-type crystal area under control and N-type transistor district, and wherein, P-type crystal area under control is used for forming P-type crystal pipe within it, and N-type transistor district is used for forming N-type transistor within it.
Semiconductor substrate 300 can at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, GaAs, silicon-on-insulator (SOI), insulator.Doped region (not shown) can be formed with in Semiconductor substrate 300, such as, be positioned at the N-type well region in P-type crystal area under control and be positioned at the P type trap zone in N-type transistor district.In addition, can also comprise isolation structure 310 in Semiconductor substrate 300, such as shallow trench isolation is from (STI) etc., and isolation structure 310 can be formed by silica, silicon nitride, silicon oxynitride, Fluorin doped glass and/or other existing advanced low-k materials.
Semiconductor substrate 300 is formed gate dielectric layer 301, and gate dielectric layer 301 has higher dielectric constant, and its thickness can be 10-30 dust.Gate dielectric layer 301 can comprise hafnium oxide (HfO
x), or optionally comprise HfSiO
x, HfSiON, HfTaO, HfTiO, HfZrO or aforesaid combination.Gate dielectric layer 301 is formed cover layer 302, and the thickness of cover layer 302 can be 10-100 dust.Cover layer 302 not only can as the etching stop layer of etching technics forming dummy grid, but also at this etching technics and can to remove in dummy grid process grill-protected dielectric layer 301 from damage.Cover layer 302 can comprise titanium nitride or tantalum nitride etc.
Perform step 202, form the photoresist layer exposing P-type crystal area under control on the cover layer.
As shown in Figure 3 B, cover layer 302 is formed with the photoresist layer 303 exposing P-type crystal area under control.Described photoresist layer 303 can be formed by methods such as spin coating, exposure, developments.This photoresist layer 303, for blocking N-type transistor district, has an impact to the gate dielectric layer 301 in N-type transistor district and cover layer 302 to avoid last nitrogen treatment process.
Perform step 203, perform nitrogen treatment process, with the nitrogen that adulterates in the gate dielectric layer and cover layer in P-type crystal area under control.
As shown in Figure 3 C, to adulterate in the gate dielectric layer 301 and cover layer 302 in P-type crystal area under control nitrogen by performing nitrogen treatment process.On the one hand, replaced the oxygen atom of interface by the interface doping nitrogen-atoms of the gate dielectric layer 301 in P-type crystal area under control and cover layer 302, effectively can improve the work function of cover layer 301.Particularly, use nitrogen-atoms to be replaced by the oxygen atom of 1/3 of interface and the effective work function of cover layer 301 (EWF) value can be improved 180meV, and along with the increasing of quantity of the oxygen atom be substituted, work function is larger, when the oxygen atom that interface is all is all replaced by nitrogen-atoms, effective work function value can be improved 450meV.As can be seen here, method of the present invention can improve the effective work function value of the cover layer 302 in P-type crystal area under control, reduces the threshold voltage of P-type crystal pipe, and then cover layer 302 can be matched with the work-function layer in P-type crystal area under control and N-type transistor district simultaneously.On the other hand, the part nitrogen-atoms of doping can be diffused in gate dielectric layer 301, and this part nitrogen-atoms not only can improve the dielectric constant of gate dielectric layer 301, effectively can also improve equivalent oxide thickness (EOT).
According to one embodiment of the present invention, nitrogen treatment process is rapid thermal nitridation process, and wherein, the reacting gas passed into is ammonia.Exemplarily, the pressure in rapid thermal nitridation process in reaction chamber can be 1-30Torr.Reaction temperature can be 500-1000
oc.The flow velocity of ammonia can be 1-60sccm, and wherein, sccm is under standard state, namely 1 atmospheric pressure, 1 cubic centimetre of (1cm per minute under 25 degrees Celsius
3/ min) flow velocity.Reaction time can be 1-100 second.The nitrogen-atoms of major part doping can be made like this to be positioned at the interface of gate dielectric layer 301 and cover layer 302, to improve the utilance of nitrogen-atoms.In addition, those skilled in the art can carry out choose reasonable according to actual conditions within the scope of above-mentioned parameter, with the nitrogen-atoms at the interface of gate dielectric layer 301 and cover layer 302 doping suitable concn, control the increase of effective work function value, reduce the impact on the P-type crystal pipe formed subsequently as far as possible.
According to another execution mode of the present invention, nitrogen treatment process comprises a point coupling formula pecvd nitride (Decoupled Plasma Nitridation, DPN) technique.Use pulsed power in this point of coupling formula plasma nitridation process, and the reacting gas passed into comprises nitrogen.Exemplarily, the pulsed power in coupling formula plasma nitridation process is divided can be 100-3000W.The duty ratio of pulsed power can be 0-50%.The reacting gas passed into can also comprise the inert gases such as argon gas.In addition, this nitrogen treatment process also comprises annealing process, with activating dopant atoms after point coupling formula plasma nitridation process.Annealing temperature in annealing process can be 500-1000
oc, annealing time can be 1-80 second.In addition, owing to also comprising annealing process in subsequent technique (such as, shallow doping process and source/drain doping process etc.), therefore, the annealing process after coupling formula plasma nitridation process is divided also can to omit.The nitrogen-atoms of major part doping can be made like this to be positioned at the interface of gate dielectric layer 301 and cover layer 302, to improve the utilance of nitrogen-atoms.In addition, those skilled in the art can carry out choose reasonable according to actual conditions within the scope of above-mentioned parameter, with the nitrogen-atoms at the interface of gate dielectric layer 301 and cover layer 302 doping suitable concn, control the increase of effective work function value, reduce the impact on the P-type crystal pipe formed subsequently as far as possible.
According to yet another embodiment of the present invention, nitrogen treatment process is plasma doping process, and wherein, the reacting gas passed into is nitrogen.Exemplarily, the energy of plasma doping process can be 100-2000eV.Those skilled in the art can select suitable Implantation Energy according to the material of selected cover layer 302 and thickness, with the interface making the nitrogen-atoms of major part doping be positioned at gate dielectric layer 301 and cover layer 302, improves the utilance of nitrogen-atoms.The implantation dosage of plasma doping process can be 10
11-10
14individual/square centimeter, with the nitrogen-atoms at the interface of gate dielectric layer 301 and cover layer 302 doping suitable concn, controls the increase of effective work function value, reduces the impact on the P-type crystal pipe formed subsequently as far as possible.
Should be understood that, the nitrogen treatment process of above-mentioned execution mode is only exemplary, those skilled in the art can also adopt the nitrogen treatment process of alternate manner to adulterate in gate dielectric layer 301 and cover layer 302 nitrogen, as long as can increase the effective work function that P-type crystal pipe removes interior cover layer 302.
Perform step 204, remove photoresist layer.
As shown in Figure 3 D, the conventional method in this area can be adopted to remove photoresist layer 303, be not described in detail in this.
In addition, method of the present invention can also comprise the step of follow-up formation metal gates.Below in conjunction with Fig. 3 E-3H, the metal gates formation process according to one embodiment of the present invention is simply described.
As shown in FIGURE 3 E, cover layer 302 is formed the first dummy grid 304 and the second dummy grid 305 respectively, and wherein, the first dummy grid 304 is positioned at N-type transistor district, and the second dummy grid 305 is positioned at P-type crystal area under control.The material of the first dummy grid 304 and the second dummy grid 305 can be the material of formation dummy grid conventional in this area, such as polysilicon.Exemplarily, polysilicon layer can be formed on cover layer 302, then etching be carried out formed the first dummy grid 304 and the second dummy grid 305 to polysilicon layer.
In addition, the step being formed with known element (not shown) in Semiconductor substrate 300 or on it can also be comprised, described known elements such as comprises shallow doped region, clearance wall, source/drain region, the SiGe element of P-type crystal pipe, metal silicide, contact hole etching stop-layer (CESL), these known elements can carry out extra CMOS technology to be formed, and therefore no longer describe in detail.
As illustrated in Figure 3 F, cover layer 306 is formed the interlayer dielectric layer 306 of encirclement first dummy grid 304 and the second dummy grid 305.Interlayer dielectric layer 306 can comprise the oxide formed by high-aspect-ratio (HARP) and/or high-density plasma (HDP) depositing operation.Exemplarily, interlayer dielectric layer 306 can be formed on cover layer 302 and the first dummy grid 304 and the second dummy grid 305, then carry out chemical mechanical milling tech to the upper surface exposing the first dummy grid 304 and the second dummy grid 305.
As shown in Figure 3 G, remove in the first dummy grid 304 and the second dummy grid 305 and fill metal level, to form the first metal gates.Exemplarily, remove the first dummy grid 304 and fill metal level, to form N-type metal gates 307.
As shown in figure 3h, another removing in the first dummy grid 304 and the second dummy grid 305 also fills metal level, to form the second metal gates.Exemplarily, remove the second dummy grid 305 and fill metal level, to form P type metal gates 308.
It should be noted that, first can also remove the second dummy grid 305, form P type metal gates 308; And then remove the first dummy grid 304, form N-type metal gates 307.In addition, because N-type metal gates and P type metal gates need to have different work functions, therefore, N-type metal gates 307 and P type metal gates 308 comprise the work-function layer and metal material layer (all not shown) that are formed successively.Work-function layer can comprise the such as derivative of titanium nitride, ruthenium, molybdenum, aluminium, tungsten nitride, aforesaid oxide or silicide or the single metal level of aforementioned combinatorial or complex metal layer, to improve effective work function (EWF) value.This workfunction layers can be formed by atomic layer deposition method (ALD), physical vaporous deposition (PVD) or other appropriate technology.The thickness of the work-function layer of P type metal gates can be about 50-100 dust, and the thickness of the workfunction layers of N-type metal gates should be less than the thickness of the workfunction layers of P type metal gates, and can adjust its work function through Technology for Heating Processing.Metal material layer can comprise the metal that aluminium, copper etc. have excellent conductive performance.
To sum up, the oxygen atom of interface is replaced by the gate dielectric layer in P-type crystal area under control and tectal interface doping nitrogen-atoms, the tectal effective work function value in P-type crystal area under control can be improved, reduce the threshold voltage of P-type crystal pipe, and then cover layer can be matched with the work-function layer in P-type crystal area under control and N-type transistor district simultaneously.In addition, the part nitrogen-atoms of doping can be diffused in gate dielectric layer, and this part nitrogen-atoms not only can improve the dielectric constant of gate dielectric layer, can also effectively improve equivalent oxide thickness.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (13)
1. make a method for semiconductor device, comprising:
A) provide Semiconductor substrate, described Semiconductor substrate comprises P-type crystal area under control and N-type transistor district, and it is formed with gate dielectric layer and cover layer successively;
B) on described cover layer, form the photoresist layer exposing described P-type crystal area under control;
C) perform nitrogen treatment process, with the described gate dielectric layer in described P-type crystal area under control and described tectal interface doping nitrogen-atoms, the part nitrogen-atoms of doping can be diffused in described gate dielectric layer; And
D) described photoresist layer is removed; And
Described cover layer is formed the first dummy grid and the second dummy grid respectively, and wherein, described first dummy grid is positioned at described N-type transistor district, and described second dummy grid is positioned at described P-type crystal area under control;
Described cover layer is formed the interlayer dielectric layer surrounding described first dummy grid and described second dummy grid;
Remove in described first dummy grid and described second dummy grid and fill metal level, to form the first metal gates; And
Another removing in described first dummy grid and described second dummy grid also fills metal level, to form the second metal gates, wherein
Described first metal gates and described second metal gates comprise the work-function layer and metal material layer that are formed successively.
2. the method for claim 1, is characterized in that, the described nitrogen treatment process in described c) step is rapid thermal nitridation process, and wherein, the reacting gas passed into is ammonia.
3. method as claimed in claim 2, it is characterized in that, the pressure in reaction chamber is 1-30Torr.
4. method as claimed in claim 2, it is characterized in that, reaction temperature is 500-1000 DEG C.
5. method as claimed in claim 2, it is characterized in that, the flow velocity of described ammonia is 1-60sccm.
6. method as claimed in claim 2, it is characterized in that, the reaction time is 1-100 second.
7. the method for claim 1, it is characterized in that, described nitrogen treatment process in described c) step comprises a point coupling formula plasma nitridation process, use pulsed power, and the reacting gas passed into comprises nitrogen in described point of coupling formula plasma nitridation process.
8. method as claimed in claim 7, it is characterized in that, the pulsed power in described point of coupling formula plasma nitridation process is 100-3000W.
9. method as claimed in claim 7, it is characterized in that, the duty ratio of described pulsed power is 0-50%.
10. method as claimed in claim 7, it is characterized in that, described nitrogen treatment process also comprises annealing process after described point of coupling formula plasma nitridation process.
11. the method for claim 1, is characterized in that, described nitrogen treatment process is plasma doping process, and wherein, the reacting gas passed into comprises nitrogen.
12. methods as claimed in claim 11, is characterized in that, the Implantation Energy of described plasma doping process is 100-2000eV.
13. methods as claimed in claim 11, is characterized in that, the implantation dosage of described plasma doping process is 10
11-10
14individual/square centimeter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN106298506A (en) * | 2015-05-25 | 2017-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and forming method |
| CN106328594B (en) * | 2015-07-02 | 2019-08-27 | 中芯国际集成电路制造(上海)有限公司 | How the transistor is formed |
| US9859392B2 (en) * | 2015-09-21 | 2018-01-02 | Samsung Electronics Co., Ltd. | Integrated circuit device and method of manufacturing the same |
| CN108346577B (en) * | 2017-01-22 | 2021-04-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of manufacturing the same |
| CN108389835B (en) * | 2017-02-03 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN1795539A (en) * | 2003-05-28 | 2006-06-28 | 应用材料有限公司 | Method and apparatus for plasma nitridation of gate dielectrics using amplitude modulated radio-frequency energy |
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