CN103092258B - Clock generation circuit self correcting system and bearing calibration thereof - Google Patents
Clock generation circuit self correcting system and bearing calibration thereof Download PDFInfo
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- CN103092258B CN103092258B CN201310032839.9A CN201310032839A CN103092258B CN 103092258 B CN103092258 B CN 103092258B CN 201310032839 A CN201310032839 A CN 201310032839A CN 103092258 B CN103092258 B CN 103092258B
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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Abstract
nullThe present invention proposes a kind of clock generation circuit self correcting system and method，Wherein system includes hardware logic module、The register module connected with hardware logic module、The clock generation circuit module connected with hardware logic module and register module and the memory module being bi-directionally connected with register module，Wherein hardware logic module produces search data and transmits to register module as the configuration parameter of clock generation circuit module，Register module output register data are to clock generation circuit module，Produce clock signal of system and transmit to hardware logic module，Clock signal of system and external reference clock signal compare，When being unsatisfactory for required precision，It is corrected producing new search data and carrying out next round correction to search data，During until meeting required precision，Hardware logic module stops correction，And now search data are stored in memory module.The error of the clock generation circuit in electronic system can be reduced in required error range by the present invention automatically.
Description
[technical field]
The present invention relates to integrated circuit fields, particularly relate to automatically the clock in electronic system to be produced electricity
Clock generation circuit self correcting system that the error on road is reduced in required error range and correction thereof
Method.
[background technology]
Clock signal used in integrated circuit fields typically requires the highest accuracy, just can ensure that
Communication is normal.Existing clock generation circuit alignment technique, in Patent No. CN200410086408.1
State's patent, the main algorithm using counting realizes correction, it is generally required to by control unit such as CPU or
MCU completes correct operation.
The defect that existing clock generation circuit alignment technique exists mainly has: the first, lacks checking computations mechanism, leads
Whether the clock accuracy after cause cannot verify its correction meets system requirements；The second, lack Data Control and deposit
Storage, causes correction data to be easily lost, poor reliability；As long as the 3rd lacks CPU's or MCU
Get involved, then cannot complete correction, i.e. system does not possess self-correcting capability.
[summary of the invention]
For the problems referred to above, it is an object of the invention to provide a kind of can be automatically by the clock in electronic system
Produce the clock generation circuit self correcting system that the error of circuit is reduced in required error range
And bearing calibration.
A kind of clock generation circuit self correcting system, comprising:
Hardware logic module, it receives external reference clock signal；
Register module, itself and described hardware logic module connect；
Clock generation circuit module, itself and described hardware logic module and described register module connect；
And
Memory module, itself and described register module are bi-directionally connected；
Described hardware logic module produces search data and transmits to described register module as described
The configuration parameter of oscillator in clock generation circuit module, described register module is according to described search number
According to output register data to described clock generation circuit module, described clock generation circuit module produces
Clock signal of system also transmits to described hardware logic module, and described hardware logic module is by described system
Clock signal and described external reference clock signal compare, the clock frequency when described oscillator exports
When rate is unsatisfactory for required precision, described search data are corrected producing newly by described hardware logic module
Search data and carry out next round correction, until described oscillator output clock frequency meet precision
During requirement, described hardware logic module stops correction, and now search data are stored in described storage mould
Block.
In the present invention one better embodiment, described hardware logic module carries out school to described search data
Just include the value increasing described search data and the value reducing described search data.
In the present invention one better embodiment, described register module is the register of variable bit width, its
Described search data are deposited in the different moment.
In the present invention one better embodiment, described memory module is nonvolatile memory.
In the present invention one better embodiment, described clock generation circuit self correcting system farther includes
Data transmission module, described data transmission module is arranged at described register module and described memory module
Between, itself and described register module and described memory module are bi-directionally connected respectively, described memory module
It is bi-directionally connected by described data transmission module and described register module.
In the present invention one better embodiment, described external reference clock signal is defeated by external clock generator
Enter to described hardware logic module.
The present invention additionally provides the bearing calibration of a kind of clock generation circuit self correcting system, it include with
Lower step:
Produce search data；
The frequency size of comparison system clock signal and external reference clock signal, if frequency error meets essence
Degree requires that then stopping correction also stores correction data, otherwise judges that described clock signal of system is relative to outside described
Portion's reference clock signal is the fastest the slowest；
If described clock signal of system is too fast relative to described external reference clock signal, then search described in reduction
Rope data, if described clock signal of system is too slow relative to described external reference clock signal, then increase institute
State search data；
The correction of next round is entered after time delay.
In the present invention one better embodiment, described search data are produced by hardware logic module and transmit
To register module as the configuration parameter of oscillator in clock generation circuit module.
In the present invention one better embodiment, described correction data is for making to shake in clock generation circuit module
The frequency of the clock signal of system swinging device output is full relative to the frequency of described external reference clock signal
The value of the search data of foot required precision.
In the present invention one better embodiment, described external reference clock signal is defeated by external clock generator
Enter to described hardware logic module.
Relative to prior art, described clock generation circuit self correcting system passes through hardware logic therein
Module, register module and clock generation circuit module, utilize described bearing calibration, can automatically by
The error of the clock generation circuit in respective electronic system is reduced to the error required by this electronic system
In accuracy rating, and corrected value is saved in memory module therein, thus, can be at described clock
After generation circuit self correcting system completes correction, this electronic system its clock after every time powering on produces
Circuit can provide high-precision clock signal.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the present invention's
Technological means, and can being practiced according to the content of specification, and in order to allow the above-mentioned of the present invention and
Other objects, features and advantages can become apparent, and below especially exemplified by embodiment, and coordinates accompanying drawing,
Describe in detail as follows.
[accompanying drawing explanation]
The composition diagram of the clock generation circuit self correcting system that Fig. 1 provides for first embodiment of the invention.
The composition diagram of the clock generation circuit self correcting system that Fig. 2 provides for second embodiment of the invention.
The bearing calibration of the clock generation circuit self correcting system that Fig. 3 provides for third embodiment of the invention
Workflow diagram.
[detailed description of the invention]
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing and reality
Execute example, the present invention is further elaborated.Only should be appreciated that specific embodiment described herein
Only in order to explain the present invention, it is not intended to limit the present invention.
Referring to Fig. 1, first embodiment of the invention provides a kind of clock generation circuit self correcting system
100, it includes that hardware logic module (search reg) 10, register module (reg) 20, clock produce
Circuit module (osc) 30 and memory module (mem) 40.
The input signal of described hardware logic module 10 is external reference clock signal ref_clk and described
The clock signal of system osc_clk of clock generation circuit module 30 output, output signal is search data
Nxt_reg, search data nxt_reg are transferred to described register module 20.In the present embodiment, described
Hardware logic module 10 utilizes certain searching algorithm, search data nxt_reg output to described
Register module 20, as the oscillator (figure do not indicate) of described clock generation circuit module 30
Configuration parameter, then monitors the clock signal of system osc_clk that described oscillator produces, and by one
Fixed method is by described clock signal of system osc_clk and described external reference clock signal ref_clk
Compare, until some search data nxt_reg makes the system clock letter that described oscillator exports
Till the frequency error of number osc_clk meets required precision, now, this searches for data nxt_reg
Value be correction data (result), its transmission is also stored in described storage to described memory module 40
Module 40.The circulation of the most described hardware logic module 10 revises described search data nxt_reg, with school
The clock signal of system osc_clk of the most described clock generation circuit module 30 output, when making described system
The frequency error of clock signal osc_clk meets required precision, and obtains correction data (result).
It is understood that during obtaining correction data (result), described hardware logic mould
Block 10 relates to searching algorithm and the frequency accuracy comparison algorithm searching for data nxt_reg.Wherein, search
The searching algorithm of rope data nxt_reg can produce an initial value, time then by described external reference
The comparative result of the clock frequency of clock signal ref_clk and described clock signal of system osc_clk, sentences
Break the need of the value increasing or reducing described search data nxt_reg, if comparative result is discontented with
Foot required precision corrects the most next time, described search data nxt_reg is i.e. increased or decreased and produces
New search data nxt_reg carry out the search of a new round, until described clock signal of system ref_clk
Till meeting required precision with the comparative result of described external reference clock signal ref_clk.Herein,
Increase or reduce the value of described search data nxt_reg to use dichotomy or gradually add one and subtract
One operation, specifically can select as required.Frequency accuracy comparison algorithm is outside ginseng described in comparison
The method examining the clock frequency of clock signal ref_clk and described clock signal of system osc_clk is permissible
Utilize high-frequency clock to add a counting to the rising edge or trailing edge adopting low frequency clock, pass through
Stopping counting after the known time, the value and the precalculated standard value that compare counter judge precision
Whether meet requirement；Another comparative approach is to be respectively adopted counter to described external reference clock
Signal ref_clk and described clock signal of system osc_clk counts, and stops through after a period of time
Counting, whether the value comparing two counters meets required precision, owing to described external reference clock is believed
Number ref_clk and described clock signal of system osc_clk is asynchronous clock signal, thus can not directly than
The relatively value of two counters, it will usually utilize Gray code to change, then to the value after Gray code
Carry out making a call to two rows to synchronize, then Gray code is binary code, compares the most again, and then judge ratio
Whether relatively result meets requirement.
Described register module 20 and described hardware logic module 10 connect, and its input signal is described
Hardware logic module 10 produce search data nxt_reg and from described memory module 40 transmit
Data mem2re, output signal is register data new_reg and data re2mem.Described deposit
Device data new_reg are input to described clock generation circuit module 30, and described data re2mem input
To described memory module 40.In the present embodiment, described register module 20 is register, its bit wide
Can be varied as desired in, deposit described search data nxt_reg and data in the different moment
The value of mem2re, and export described register data new_reg to described clock generation circuit module
30, output data re2mem are to described memory module 40.
It is understood that described register data new_reg is described register module 20 basis
Receive described search data nxt_reg and produce.
Described clock generation circuit module 30 and described hardware logic module 10 and described register module
20 are all connected with, and itself and described hardware logic module 10 and described register module 20 constitute unidirectional following
Ring.The input signal of described clock generation circuit module 30 is posting of described register module 20 output
Latch data new_reg, output signal is the clock signal of system osc_clk that wherein oscillator produces.
Described clock signal of system osc_clk input is to described hardware logic module 10.Described clock produces electricity
Road module 30 produces, according to different register data new_reg, the system clock letter that frequency is different
Number osc_clk.
Described memory module 40 and described register module 20 are bi-directionally connected, and its input signal is described
Data re2mem of register module 20 output, output signal is data mem2re.The present embodiment
In, described memory module 40 is nonvolatile memory, can store data steadily in the long term, work as institute
When stating memory module 40 power down, the data of its storage also will not be lost.
It is understood that the output of described register module 20 is to the data of described memory module 40
Re2mem is described correction data result, and thus, described correction data result can be stored in
Described memory module 40.The most described correction data result can be in described memory module 40 and described
It is transmitted between register module 20.Correct first and needed described correction data result by rear
By being transferred to described memory module 40, needs when powering on from described register module 20 the most every time
Described correction data result by being transferred to described register module 20 from described memory module 40.
In the present embodiment, described correction data result is in described register module 20 and described memory module
Transmission between 40 is realized by software.Certainly, and it is confined to this, described register module 20
With the transmission of data-signal can also be realized by hardware, such as Fig. 2 between described memory module 40
Shown in, the clock generation circuit self correcting system 200 that second embodiment of the invention provides farther includes
Data transmission module (move control) 50, described data transmission module 50 be arranged at described in deposit
Between device module 20 and described memory module 40, itself and described register module 20 and described storage
Module 40 is bi-directionally connected respectively.
In the present embodiment, described register module 20 exports data re2mc and transmits mould to described data
Block 50, the input signal of described data transmission module 50 is described data re2mc and deposits from described
Data me2mc of storage module 40 output, output signal is that transmission is to described register module 20
Data mc2me of data mc2re and transmission extremely described memory module 40.
It is understood that in the present embodiment, described clock generation circuit self correcting system 200 is passed through
Described data transmission module 50 realizes described correction data result in described memory module 40 and described
Transmission between register module 20.Now, correct first by rear described correction data result
It is transferred to described memory module 40 from described register module 20 by described data transmission module 50,
And when powering on the most every time described correction data result by described data transmission module 50 from
Described memory module 40 is transferred to described register module 20.
Referring to Fig. 3, third embodiment of the invention provides described clock generation circuit self correcting system
The bearing calibration of 100, it comprises the following steps:
S101, generation search data.
In the present embodiment, described hardware logic module 10 produces search data nxt_reg, and exports extremely
Described register module 20, as the configuration parameter of oscillator in described clock generation circuit module 30,
Register data new_reg is formed according to described search data nxt_reg again by described register module 20
Signal, and it is transferred to described clock generation circuit module 30, the vibration of described clock generation circuit module 30
Device output clock signal of system osc_clk, and transmit to described hardware logic module 10.
The frequency size of clock signal of system and external reference clock signal described in S103, comparison.
In the present embodiment, described hardware logic module 10 comparison system clock signal osc_clk and described outside
The frequency size of reference clock signal ref_clk.
Whether S104, determination frequency error meet required precision.
If the frequency of described clock signal of system osc_clk and described external reference clock signal ref_clk is by mistake
Difference meets required precision and then enters step S105A, otherwise enters step S105B.
It is understood that described external reference clock signal ref_clk is inputted extremely by external clock generator
Described hardware logic module 10.
S105A, stopping correction, and store correction data.
In the present embodiment, make the frequency of the clock signal of system osc_clk that described oscillator exports relative to
The frequency of described external reference clock signal ref_clk meets search data nxt_reg of required precision
Value is correction data result, and the transmission of described correction data result is deposited to described memory module 40
Storage.
S105B, judge that described clock signal of system is too fast relative to described external reference clock signal the most too
Slowly.
In the present embodiment, according to described clock signal of system osc_clk and described external reference clock signal
The frequency error of ref_clk, when judging described clock signal of system osc_clk relative to described external reference
Clock signal ref_clk is the soonest or too slow, and correspondingly revises the value of search data nxt_reg, if institute
State clock signal of system osc_clk too fast relative to described external reference clock signal ref_clk, then enter step
Rapid S107A, if described clock signal of system osc_clk is relative to described external reference clock signal ref_clk
Too slow, then enter step S107B.
S107A, reduce described search data.
It is understood that reduce search data nxt_reg new produced by described search data nxt_reg
By make described clock generation circuit module 30 produce clock signal of system osc_clk close to described external reference
Clock signal ref_clk, thus, it is possible to reduce described clock signal of system osc_clk and described external reference
The frequency error of clock signal ref_clk, and then meet required precision.
S107B, increase described search data reg.
It is understood that increase search data nxt_reg new produced by described search data nxt_reg
By make described clock generation circuit module 30 produce clock signal of system osc_clk close to described external reference
Clock signal ref_clk, thus, it is possible to reduce described clock signal of system osc_clk and described external reference
The frequency error of clock signal ref_clk, and then meet required precision.
The correction of next round is entered after S109, time delay.
It is understood that owing to described clock generation circuit module 30 is obtaining new register data
After new_reg value, need a period of time just can settle out, thus, obtain new register data
After new_reg value, need to wait for a period of time, i.e. start again after time delay to produce nxt_reg signal.
It is understood that concrete time delay exists difference to different clock generation circuits, need logical
Cross emulation to determine.
It is understood that the described clock generation circuit self correcting system that second embodiment of the invention provides
200 equally use described bearing calibration.
Compared to prior art, described clock generation circuit self correcting system 100(that the present invention provides and
Described clock generation circuit self correcting system 200) by hardware logic module 10 therein, register
Module 20 and clock generation circuit module 30, utilize described bearing calibration, can be automatically by corresponding electricity
The error of the clock generation circuit in subsystem is reduced to the error precision scope required by this electronic system
In, and corrected value is saved in described memory module 40, thus, can be at described clock generation circuit
After self correcting system 100 completes correction, clock generation circuit is all every time after powering on for this electronic system
It is provided that high-precision clock signal.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all at this
Any amendment, equivalent and the improvement etc. made within bright spirit and principle, should be included in the present invention
Protection domain within.
Claims (7)
1. a clock generation circuit self correcting system, it is characterised in that described clock
Produce circuit self correcting system to include:
Hardware logic module, it receives external reference clock signal；
Register module, itself and described hardware logic module connect；
Clock generation circuit module, itself and described hardware logic module and described register mould
Block connects；And
Memory module, itself and described register module are bi-directionally connected；
Described hardware logic module produces search data and transmits to described register module
As the configuration parameter of oscillator in described clock generation circuit module, described register mould
Block according to described search data output register data to described clock generation circuit module,
Described clock generation circuit module produces clock signal of system and transmission to described hardware is patrolled
Collecting module, described hardware logic module is by described clock signal of system and described external reference
Clock signal compares, and the clock frequency exported when described oscillator is unsatisfactory for precision and wants
When asking, described search data are corrected producing new search by described hardware logic module
Data also carry out next round correction, and described search data are carried out by described hardware logic module
Correction includes the value increasing described search data and the value reducing described search data, specifically
Including by dichotomy or gradually add one and subtract one that method is corrected；Until described vibration
When the clock frequency of device output meets required precision, described hardware logic module stops school
Just, and now search for data and be stored in described memory module.
2. clock generation circuit self correcting system as claimed in claim 1, its feature
Being, described register module is the register of variable bit width, and it was posted in the different moment
Deposit described search data.
3. clock generation circuit self correcting system as claimed in claim 1, its feature
Being, described memory module is nonvolatile memory.
4. clock generation circuit self correcting system as claimed in claim 1, its feature
Being, described clock generation circuit self correcting system farther includes data transmission module,
Described data transmission module is arranged between described register module and described memory module,
Itself and described register module and described memory module are bi-directionally connected respectively, described storage mould
Block is bi-directionally connected by described data transmission module and described register module.
5. clock generation circuit self correcting system as claimed in claim 1, its feature
Being, described external reference clock signal is patrolled to described hardware by the input of external clock generator
Collect module.
6. the bearing calibration of a clock generation circuit self correcting system, it is characterised in that
Described bearing calibration comprises the following steps:
Hardware logic module produces search data and transmits to register module as described
The configuration parameter of oscillator in clock generation circuit module, described register module is according to institute
State search data output register data to described clock generation circuit module；
The frequency size of comparison system clock signal and external reference clock signal, if frequency is by mistake
Difference meets required precision and then stops correction and store correction data, otherwise judges described system clock
Signal is the fastest relative to described external reference clock signal the slowest；Described correction data is
Make the frequency of the clock signal of system of oscillator output in clock generation circuit module relative
Frequency in described external reference clock signal meets the value of the search data of required precision；
If described clock signal of system is too fast relative to described external reference clock signal, then subtract
Little described search data, if described clock signal of system is believed relative to described external reference clock
Number too slow, then increase described search data, specifically include by dichotomy or gradually add one and subtract
One method is corrected；
The correction of next round is entered after time delay.
7. the correction side of clock generation circuit self correcting system as claimed in claim 6
Method, it is characterised in that described external reference clock signal is inputted extremely by external clock generator
Described hardware logic module.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310032839.9A CN103092258B (en) | 2013-01-28 | 2013-01-28 | Clock generation circuit self correcting system and bearing calibration thereof |
| PCT/CN2013/088846 WO2014114146A1 (en) | 2013-01-28 | 2013-12-09 | Self-correcting system for clock-generating circuit and correcting method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310032839.9A CN103092258B (en) | 2013-01-28 | 2013-01-28 | Clock generation circuit self correcting system and bearing calibration thereof |
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| CN103092258B true CN103092258B (en) | 2016-08-24 |
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| CN103092258B (en) * | 2013-01-28 | 2016-08-24 | 深圳市汇顶科技股份有限公司 | Clock generation circuit self correcting system and bearing calibration thereof |
| CN104184470B (en) * | 2014-09-01 | 2017-04-19 | 福州瑞芯微电子股份有限公司 | Automatic resetting device and method for PLL modification |
| WO2019061077A1 (en) * | 2017-09-27 | 2019-04-04 | 深圳市汇顶科技股份有限公司 | Pulse width modification circuit, pulse width modification method, and electronic apparatus |
| CN110729985B (en) * | 2018-07-17 | 2023-04-25 | 中芯国际集成电路制造(北京)有限公司 | Clock signal generation circuit and electronic equipment |
| CN110729984B (en) * | 2018-07-17 | 2023-12-22 | 中芯国际集成电路制造(北京)有限公司 | Clock signal generation circuit and electronic equipment |
| CN109394193B (en) * | 2018-11-27 | 2021-04-23 | 西安交大辰方科技有限公司 | Method for calibrating real-time clock of dynamic blood pressure recorder |
| CN110492848A (en) * | 2019-08-15 | 2019-11-22 | 成都锐成芯微科技股份有限公司 | The number adjustment device and its method of adjustment of RC oscillator |
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| CN101170349A (en) * | 2006-10-23 | 2008-04-30 | 大唐移动通信设备有限公司 | Real time clock calibration circuit |
| CN101436086B (en) * | 2008-11-20 | 2010-06-16 | 四川和芯微电子股份有限公司 | System for initially generating stabilized in-chip clock |
| CN102195646A (en) * | 2010-03-18 | 2011-09-21 | 上海华虹Nec电子有限公司 | Automatic clock oscillator calibration method and circuit |
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| TWI273367B (en) * | 2004-10-01 | 2007-02-11 | Fortune Semiconductor Corp | Method and device for calibrating monitor clocks |
| CN103092258B (en) * | 2013-01-28 | 2016-08-24 | 深圳市汇顶科技股份有限公司 | Clock generation circuit self correcting system and bearing calibration thereof |
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- 2013-01-28 CN CN201310032839.9A patent/CN103092258B/en active Active
- 2013-12-09 WO PCT/CN2013/088846 patent/WO2014114146A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101170349A (en) * | 2006-10-23 | 2008-04-30 | 大唐移动通信设备有限公司 | Real time clock calibration circuit |
| CN101436086B (en) * | 2008-11-20 | 2010-06-16 | 四川和芯微电子股份有限公司 | System for initially generating stabilized in-chip clock |
| CN102195646A (en) * | 2010-03-18 | 2011-09-21 | 上海华虹Nec电子有限公司 | Automatic clock oscillator calibration method and circuit |
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| CN103092258A (en) | 2013-05-08 |
| WO2014114146A1 (en) | 2014-07-31 |
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