CN103092246A - Power supply monitoring system and method - Google Patents

Abstract

The application provides a power supply monitoring system, the system includes: LDO; an acquisition circuit for collecting the current output by the LDO and converting it into an analog voltage signal; connected with the acquisition circuit, for converting the analog voltage signal An ADC for a digital voltage signal; connected to the ADC for receiving the digital voltage signal converted by the ADC, comparing the received digital voltage signal with a preset voltage threshold stored in itself, and controlling the operation of the LDO according to the comparison result state of the control chip. The power supply monitoring system control chip provided by this application can directly use software programming to easily change the preset voltage threshold, which facilitates the adjustment of the power supply monitoring system, so that the same power supply monitoring system is convenient for monitoring different sub-boards.

Description

A power supply monitoring system and method

technical field

The present application relates to the field of current monitoring on circuit boards, in particular to a power supply monitoring system and method.

Background technique

At present, in various application systems, the motherboard needs to supply power to the daughter board, and at the same time, the power supply needs to be monitored. The monitoring of the power supply from the motherboard to the daughter board refers to monitoring the real-time current provided by the mother board to the daughter board.

In the currently commonly used motherboard-to-daughterboard power supply monitoring system, the motherboard can simultaneously provide power to multiple daughterboards, and the motherboard can provide different voltages for each daughterboard to meet the voltage requirements of the daughterboards. However, when the power supply monitoring system is used to monitor the power supply, the comparator is directly used to monitor and control the analog voltage signal.

The components used to ensure the normal operation of the comparator in the power supply monitoring system and the comparator constitute the voltage reference circuit of the monitoring sub-board, that is, a voltage threshold is set in the power supply monitoring system. When the power supply system is monitoring different sub-boards, the voltage threshold needs to be changed, that is, the resistance connected to the comparator needs to be debugged. And it is necessary to repeatedly debug the resistance connected to the comparator, and it can be used only when the requirements are met.

Contents of the invention

The technical problem to be solved by this application is to provide a power supply monitoring system to solve the problem in the prior art that when the preset voltage threshold is changed when the power supply monitoring is based on the comparator, it is necessary to repeatedly debug the hardware.

In order to solve the above problems, the application discloses a power supply monitoring system, including:

linear regulator (LDO);

A collection circuit for collecting the current output by the LDO and converting it into an analog voltage signal;

connected with the acquisition circuit, and used for converting the analog voltage signal into an analog-to-digital converter (ADC) of a digital voltage signal;

A control chip connected to the ADC for receiving the digital voltage signal converted by the ADC, comparing the received digital voltage signal with a preset voltage threshold stored in itself, and controlling the working state of the LDO according to the comparison result.

Preferably, the control chip includes: a programmable logic device (FPGA), and the FPGA controls the enable terminal of the LDO to control the working state of the LDO.

Preferably, the FPGA controls the acquisition and conversion speed of the ADC by providing signals to the first pin and the second pin of the ADC.

Preferably, the acquisition circuit includes: a sense resistor and a current sense amplifier; wherein,

One end of the detection resistor is connected to the output end of the LDO, and the other end is used as the output end of the sub-board power supply;

A current sense amplifier is connected in parallel across the sense resistor.

Preferably, the first pin of the current sense amplifier is connected to one end of the sense resistor connected to the LDO; the second pin of the current sense amplifier is connected to the other end of the sense resistor; the third pin of the current sense amplifier is used as the current sense amplifier The output terminal of the ADC is connected to the third pin of the ADC.

The present application also provides a power supply monitoring method, the method comprising:

Receive the digital voltage signal sent by the ADC;

Comparing the digital voltage signal with the reserved threshold voltage, and controlling the working state of the LDO according to the comparison result; wherein the controlling the working state of the LDO according to the comparison result includes: if the digital voltage signal is within the preset voltage threshold range Inside, the control LDO is in the on state; if the digital voltage signal is higher than the preset voltage threshold, the control LDO is in the off state.

Preferably, if the enable terminal of the selected LDO is high effective, the working state of the control LDO includes:

Output a high level to the enable terminal of the LDO, so that the LDO is in the open state;

Output low level to the enable terminal of LDO, so that LDO is in the off state.

Preferably, if the enable terminal of the selected LDO is low effective, the working state of the control LDO includes:

Output low level to the enable terminal of LDO, so that LDO is in the open state;

Output high level to the enable terminal of LDO, so that LDO is in the off state. Compared with the prior art, the present application includes the following advantages:

In this application, the control chip in the power supply monitoring system compares the received digital voltage signal with the reserved threshold voltage, and controls the working state of the LDO according to the comparison result. Since the control chip in this application can have a preset voltage threshold inside, and control the working state of the LDO after comparing the preset voltage threshold with the digital voltage signal, the power supply monitoring system can directly modify the internal The preset voltage threshold, such as directly changing the preset voltage threshold through software programming. The control chip can directly use software programming to change the preset voltage threshold, which is easier to change than comparator monitoring and changing components, and facilitates the adjustment of the power supply monitoring system, so that the same power supply monitoring system is convenient for monitoring different sub-boards.

Of course, implementing any product of the present application does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is a schematic structural diagram of a power supply monitoring system in the present application;

Fig. 2 is a schematic structural diagram of a power supply monitoring system acquisition circuit in the present application;

Fig. 3 is a specific structural schematic diagram of a power supply monitoring system in the present application;

Fig. 4 is a schematic structural diagram of a power supply monitoring system monitoring multiple power supplies of the present application;

Fig. 5 is a flowchart of a power supply monitoring method of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

an embodiment

The present application provides a power supply monitoring system. The core part of the power supply monitoring system is a control chip, through which the signal collected by the front end can be analyzed to control the power supply state of the circuit.

Please refer to FIG. 1, which shows a schematic structural diagram of a power supply monitoring system proposed in this application, which may include: a linear voltage regulator (LDO, low dropout regulator) 101, an acquisition circuit 102, and an analog-to-digital converter (ADC) 103 and control chip 104 . in:

LDO101 is used to convert the power of the motherboard into a stable power output and provide power for the daughter board. The input terminal of the LDO101 is connected to the power supply output terminal of the motherboard, so as to output the power supply stably. And the selected LDO101 has the function of adjustable output, that is, it can adjust the size of the power output by itself, and the output voltage can be adjusted according to the needs of the daughter board.

The collection circuit 102 collects the current output by the LDO101 and converts it into an analog voltage signal.

In this embodiment, the acquisition circuit 102 of the power supply monitoring system includes: a detection resistor 105 and a current detection amplifier 106; please refer to FIG. 2 for a schematic structural diagram thereof. in,

One end of the detection resistor 105 is connected to the output end of the LDO 101 , and the other end is used as the output end of the sub-board power supply. That is to say, during the actual use of the power supply monitoring system, one end of the detection resistor 105 is connected to the output end of the LDO101, and the other end is used as the power output end of the daughter board to connect to the daughter board, so as to provide the power outputted by the LDO101 to the daughter board. And the detection resistor 105 is connected in series in the power supply line, and its current is the same as that of the power supply line.

The current sense amplifier 106 is connected in parallel to both ends of the sense resistor 105 . The current detection amplifier 106 can collect the voltage across the detection resistor 105 and amplify the collected voltage with a preset ratio. The current magnification factor designed in the preset ratio during the design process of the current detection amplifier 106 is related to its own model, and the magnification factor cannot be adjusted after the model is confirmed.

It should be noted that in this embodiment, the current detection amplifier 106 amplifies the voltage collected by the detection resistor to facilitate current transmission, as well as the collection and analysis by the ADC 103 and the control chip 104 .

ADC103, for converting the analog voltage signal into a digital voltage signal

The control chip 104 is used to receive the digital voltage signal converted by the ADC103, compare the received digital voltage signal with the preset voltage threshold stored in itself, and control the working state of the LDO101 according to the comparison result.

Wherein the control chip 104 can control the working state of the LDO101 according to the comparison result: if the digital voltage signal is within the preset voltage threshold range, control the LDO101 to be in the on state; if the digital voltage signal is higher than the preset voltage threshold, Control LDO101 is off.

The LDO101 has an enabling terminal, and the control chip 104 may control the working state of the LDO101 by controlling the enabling terminal when controlling the working state of the LDO101 according to the comparison result. Specifically, if the enabling terminal of LDO101 is high effective, then if the digital voltage signal is within the preset voltage threshold range, the control chip 104 keeps outputting a high level to the enabling terminal of LDO101, so that LDO101 is in the On state: if the digital voltage signal is higher than the preset voltage threshold, the control chip 104 outputs a low level to the enable terminal of the LDO101, so that the LDO101 is in the off state. If the enabling terminal of LDO101 is low effective, then if the digital voltage signal is within the preset voltage threshold range, the control chip 104 keeps outputting a low level to the enabling terminal of LDO101, so that LDO101 is in an open state; If the digital voltage signal is higher than the preset voltage threshold, the control chip 104 outputs a high level to the enable terminal of the LDO101, so that the LDO101 is in an off state. In this embodiment, the preset voltage threshold is set according to the power demand of the sub-board, and the control chip can set different preset voltage thresholds for different sub-boards.

Applying the above technology, after the acquisition circuit 102 acquires the analog voltage at both ends of the detection resistor 105, the analog voltage signal is amplified by a certain ratio, and sent to the input terminal of the ADC103, and the ADC103 converts the analog voltage signal, After being converted into a digital voltage signal, it is sent to the control chip 104. The control chip 104 can set a preset voltage threshold inside, and control the working state of the LDO101 after comparing the preset voltage threshold with the digital voltage signal, so the power supply monitoring system is monitoring For different sub-boards, the internal preset voltage threshold can be directly modified, such as directly changing the preset voltage threshold through software programming. The control chip 104 can directly use software programming to change the preset voltage threshold, which is easier to change than comparator monitoring and changing components, and facilitates the adjustment of the power supply monitoring system, so that the same power supply monitoring system is convenient for monitoring different sub-boards.

In the above-mentioned embodiment, the current detection amplifier 106 can be a MAX4173F of MIXIM with a gain amplification factor of 50 times. After receiving the voltage across the detection resistor 105, the MAX4173F will amplify it by 50 times and then send it to the ADC103; The resistance value of the resistor 105 is 20mΩ, and the resistance value is selected according to the maximum current that may be reached in the line circuit connected to itself, and the comprehensively selected current detection amplifier MAX4173F is selected.

In the above-mentioned embodiment, the ADC103 uses TI's 12-bit single-channel ADC121S101 with a sampling frequency of 500ksps to 1Msps. ADC121S101 converts the analog voltage signal into a digital voltage signal and sends it to the control chip 104 .

The control chip 104 is a programmable logic device (FPGA, Field-Programmable GateArray). FPGA is a control chip 104 that can control input and output signals through software programming. After receiving the digital voltage signal sent by ADC103, FPGA compares it with the preset voltage threshold set inside itself, and controls the working state of LDO101 according to the comparison result. FPGA is the core chip in this embodiment, and can accurately and conveniently control the size of the preset voltage threshold through software programming, so as to facilitate the modification of the preset voltage threshold. Further FPGA is also used to control the sampling frequency of ADC.

It should be noted that the FPGA can control the enable terminal of the LDO101 according to the comparison result between the digital voltage signal and the preset voltage threshold. In addition, FPGA can also conveniently control LDO101 according to needs through software programming at any time when needed. If it is necessary to disconnect the power supply of LDO101 to the sub-board at a certain moment, the FPGA can output high level or low level to the enable terminal of LDO101 at this moment through software programming. It depends on the effective level.

The first pin of the current detection amplifier 106 is connected to one end of the detection resistor 105 connected to the LDO101; the second pin of the current detection amplifier is connected to the other end of the detection resistor 105; the third pin of the current detection amplifier 106 is used as a current detection The output of the amplifier 106 is connected to the third pin of the ADC 103 . The FPGA controls the acquisition and conversion speed of the ADC by providing signals to the first pin and the second pin of the ADC. Please refer to FIG. 3 , which shows the connection relationship of the specific circuit of the power supply monitoring system provided by the present application. The output end of LDO101 is connected to one end of the detection resistor 105 , and the other end of the detection resistor 105 is used as the output end of the sub-board power supply. The first pin of the current sense amplifier MAX4173F is the RS+ pin connected to one end of the detection resistor connected to LDO101; the second pin of MAX4173F is the RS- pin connected to the other end of the detection resistor; the third pin of MAX4173F is the OUT pin The pin is connected to the third pin Vin pin of ADC121S101 as the output end of MAX4173F.

引脚连接FPGA，FPGA通过为ADC121S101的第一引脚SCLK及第二引脚

提供信号控制ADC103的采集转换速度，ADC121S101的第四引脚SDATA引脚作为FPGA的一个输入端，与FPGA连接；LDO101的使能端EN是由FPGA控制的，连接在FPGA的一个输出引脚上。The Vin pin of ADC121S101 is connected to the output terminal OUT pin of MAX4173F, the SCLK pin and

The pin is connected to the FPGA, and the FPGA is the first pin SCLK and the second pin of the ADC121S101

Provide signals to control the acquisition and conversion speed of ADC103. The fourth pin SDATA pin of ADC121S101 is used as an input terminal of FPGA and connected to FPGA; the enable terminal EN of LDO101 is controlled by FPGA and connected to an output pin of FPGA. .

引脚连接FPGA时连接不同的引脚，这样多路供电监控系统在采集信号时候的频率是可以相互独立的。每路监控电路中ADC103的输出端各自连接FPGA的一个引脚，且LDO101的使能端也各自连接FPGA的一个引脚。The power supply monitoring system provided in this embodiment can simultaneously monitor the motherboard to supply power to multiple daughter boards, and the circuit diagram of each monitoring circuit is the same, as shown in FIG. 4 . And the simultaneous monitoring of multiple sub-boards can be controlled by the same FPGA. Please refer to FIG. 4 , which shows the circuit connection relationship when the power supply monitoring system provided by the present application simultaneously monitors the power supply system of multiple motherboards for daughter boards. Wherein each road acquisition circuit is the same, including: detection resistor 105 and circuit detection amplifier 106, after the current detection amplifier 106 collects the analog voltage signal at the two ends of the detection resistor 105, after the analog voltage signal is amplified by a certain ratio, it is sent to ADC103, by ADC103 Convert the analog voltage signal into a digital voltage signal, ADC103 sends the converted digital voltage signal to FPGA, FPGA compares the received digital voltage signal with the preset voltage threshold stored in itself, and controls the operation of LDO101 according to the comparison result state. In the multi-channel monitoring system, the SCLK pin of the ADC103 of the multi-channel monitoring circuit and

Different pins are connected when the pins are connected to the FPGA, so that the frequency of the multi-channel power supply monitoring system can be independent of each other when collecting signals. The output ends of the ADC103 in each monitoring circuit are respectively connected to a pin of the FPGA, and the enable ends of the LDO101 are also respectively connected to a pin of the FPGA.

Corresponding to the above-mentioned power supply monitoring system, the present application proposes a power supply monitoring method, please refer to FIG. 5, which shows a flow chart of the power supply monitoring method provided by the present application, including the following steps:

Step 501: Power on the system to make the LDO in the open state.

Step 502: Receive a digital voltage signal sent by the ADC.

Wherein the digital voltage signal sent by the ADC is that the ADC converts it into a digital voltage signal after receiving the analog voltage signal sent by the current detection amplifier; After the analog voltage signal is amplified by a certain ratio, the analog voltage signal is obtained.

Step 503: Compare the digital voltage signal with a preset voltage threshold, and control the working state of the LDO according to the comparison result.

In this embodiment, controlling the working state of the LDO according to the comparison result includes: if the LDO enable terminal is active high, if the digital voltage signal is within the preset voltage threshold range, controlling the LDO to be in the on state; if the When the digital voltage signal is higher than the preset voltage threshold, the control LDO is turned off. The LDO is in the on state when the enable terminal of the LDO is kept at a high level, that is, the FPGA always inputs a high level for the enable terminal of the LDO. The LDO is in the off state, that is, the enable terminal of the LDO inputs a low level. If the LDO enable terminal is active low, the LDO is turned on only when the LDO enable terminal remains low, that is, the FPGA always inputs a low level to the LDO enable terminal. The LDO is in the off state, that is, the enable terminal of the LDO inputs a high level.

A power supply monitoring system and method provided by this application has been introduced in detail above. In this paper, specific examples are used to illustrate the principle and implementation of this application. The description of the above embodiments is only used to help understand the method of this application. and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation and application scope. limits.

Claims (8)

1. A power supply monitoring system, characterized in that, comprising: linear regulator (LDO); A collection circuit for collecting the current output by the LDO and converting it into an analog voltage signal; connected with the acquisition circuit, and used for converting the analog voltage signal into an analog-to-digital converter (ADC) of a digital voltage signal; A control chip connected to the ADC for receiving the digital voltage signal converted by the ADC, comparing the received digital voltage signal with a preset voltage threshold stored in itself, and controlling the working state of the LDO according to the comparison result. 2 . The power supply monitoring system according to claim 1 , wherein the control chip comprises: a programmable logic device (FPGA), and the FPGA controls the enable terminal of the LDO to control the working state of the LDO. 3. The power supply monitoring system according to claim 2, wherein the FPGA controls the acquisition and conversion speed of the ADC by providing signals for the first pin and the second pin of the ADC. 4. The power supply monitoring system according to claim 2, wherein the acquisition circuit comprises: a detection resistor and a current detection amplifier; wherein, One end of the detection resistor is connected to the output end of the LDO, and the other end is used as the output end of the sub-board power supply; A current sense amplifier is connected in parallel across the sense resistor. 5. The power supply monitoring system according to claim 4, wherein the first pin of the current detection amplifier is connected to one end of the detection resistor connected to the LDO; the second pin of the current detection amplifier is connected to the other end of the detection resistor One end; the third pin of the current sense amplifier is connected to the third pin of the ADC as the output of the current sense amplifier. 6. A power supply monitoring method, characterized in that, comprising: Receive the digital voltage signal sent by the ADC; Comparing the digital voltage signal with the reserved threshold voltage, and controlling the working state of the LDO according to the comparison result; wherein the controlling the working state of the LDO according to the comparison result includes: if the digital voltage signal is within the preset voltage threshold range Inside, the control LDO is in the on state; if the digital voltage signal is higher than the preset voltage threshold, the control LDO is in the off state. 7. The power supply monitoring method according to claim 6, wherein, if the enabling terminal of the selected LDO is high effective, the working state of the control LDO includes: Output a high level to the enable terminal of the LDO, so that the LDO is in the open state; Output low level to the enable terminal of LDO, so that LDO is in the off state. 8. The power supply monitoring method according to claim 6, wherein, if the enable terminal of the selected LDO is active low, the working state of the control LDO includes: Output low level to the enable terminal of LDO, so that LDO is in the open state; Output high level to the enable terminal of LDO, so that LDO is in the off state.

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