CN103081018A - Cell-state determination in phase-change memory - Google Patents
Cell-state determination in phase-change memory Download PDFInfo
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Abstract
Methods and apparatus are provided for determining the state of a phase-change memory cell. A plurality of measurements are made on the cell, the measurements being dependent on the sub-threshold current-versus-voltage characteristic of the cell. The measurements are processed to obtain a metric which is dependent on the slope of the sub- threshold current-versus-voltage characteristic. The state of the cell is then determined in dependence on this metric which, unlike absolute cell resistance,is substantially unaffected by drift.
Description
Technical field
The present invention mainly relates to phase transition storage, and relates more specifically to the method and apparatus for the state of determining phase-changing memory unit.
Background technology
Phase transition storage (PCM) is to utilize some chalcogenide material in the novel non-volatile solid state memory technology with the reversible switching between at least two states of different conductances.PCM fast, have fine indwelling and durable attribute and shown and upgrade in the future lithography node.Think for those reasons its potential alternative or additional main flow storer of today and the storage flash memory in using.
Commercially in the available PCM device, can basic storage cell (" unit ") be arranged to one of crystalline state and these two states of amorphous state by applying heat.In representing the amorphous state state of Binary Zero, the resistance of unit is high.The temperature of chalcogenide material more than being heated to its crystallization point is transformed into conduction crystalline state state when then cooling off.This low resistive state represents binary one.If then the unit is heated to the high temperature more than the chalkogenide fusing point, then chalcogenide material returns to its amorphous state state when cooling off rapidly.For to PCM unit data writing, apply voltage or current impulse to the unit chalcogenide material is heated to proper temperature after cooling, to cause the location mode of hope.For reading unit, come the state of determining unit as tolerance with cell resistance.By unit biasing is flow through its electric current or comes measuring unit resistance by the voltage that transmits steady current and measurement leap unit formation in a certain constant voltage level and measurement.In subthreshold value (sub-threshold) zone of the current ratio voltage characteristic of unit, ((be the voltage of chalkogenide when switching to conduction " connection " state at the threshold value switched voltage namely, electric current can be crossed the unit heating it by Joule heating at this state flow, therefore causes potentially phase transformation) in the following zone) carry out this measurement.In this subthreshold value scope, can reading unit and do not affect location mode, high resistance measurement indication Binary Zero and low-resistance is measured the indication binary one.
The key request that PCM becomes main flow be make cost/potential drop to multi-level unit (MLC) ability of the level of MLC flash memory technology competition.Multilevel memory cell can be configured to s different resistance stages, and therefore s＞2 wherein allow each unit storage more than one position.For example the NOR flash memory can be stored level Four, namely two in each unit.Can come every single flash memory cells store four figures current available according to the MLC nand flash memory chip of (namely 16 grades) with the 43nm technology.In the PCM unit, realize the MLC operation by the part amorphous state state that utilizes the chalkogenide unit.Can the different units level be set by the active volume that changes the amorphous state state in the chalcogenide material.This is change unit resistance then.Although only one of current each unit storage of commercial available PCM chip, each unit storage is four in the PCM chip of having demonstrated experimentally.
Problem in the PCM device is the physical phenomenon that is called short-term resistance drift or structure Relaxation, and this phenomenon is often referred to as " drift ".This problem especially significantly and to the reliable MLC ability among the PCM is brought remarkable technology barrier in the MLC device.Think structure Relaxation owing to the local atomic rearrangement in the Amorphous Phase of phase-change material, thereby affect their conductance.Particularly, among the MLC PCM at the amorphous state state or at the resistance of the PCM unit of part amorphous state state programming in time upward displacement and also temperature influence.Therefore, the trend of increase fluctuates according to increasing along with the time in the cell resistance of different time instantaneous measurement in observation.Be random to this resistance contributive event that is shifted in character and time of occurrence, therefore be difficult to prediction and alleviate.Because resistance displacement, therefore can be overlapped in random time moment from different resistance stages corresponding to different units state (configuration of the amorphous state in enlivening volume/crystalline material phase), thus cause the definite random error of location mode.
Many technology have been proposed to solve resistance displacement problem.A kind of technology relates to the use reference unit, the purpose that wherein alleviates for drift and certain overall part of retain stored device unit.Each reference unit in these reference units is programmed to the discrete cell state, and monitors that according to regular intervals the resistance of these unit is used for the estimation of the resistance drift of other unit (unit that namely is used for the actual user data storage) with observation.Then, to obtain resistance stages without the drift impact as purpose, remove the drift of estimating from the measurement to subscriber unit.The state that the effect of offsetting based on the drift of reference level so mainly depends on similar units shows the hypothesis of similar drift characteristic.Yet when existing inevitably changeability between remarkable unit (being caused by the change in process in more junior unit yardstick increase) and unit intrinsic parameter to change (mainly being caused by changes in material), cause defective drift to be offset thereby the validity of this hypothesis is doubtful.
It is another proposal of drifting about for reply that drift is accelerated.During to memory cell programming (perhaps), in a certain (enough low) temperature annealed a period of time in the unit, to accelerate the drift impact according to Arrhenius relation (Arrhenius relation) thus.Suppose cell resistance not significantly drift after annealing.Experiment not yet fully confirms the validity of this mode.In addition because the hot activation phase transition phenomena, so unit annealing may cause the location mode disturbance do not expected.
Coding techniques has also been proposed with the reply drift.Here, not individually but in cell block (code word), programme and the read memory unit.The redundancy of adding in these code words is intended to make code word not affected by drift, and is provided at the inerrancy of when decoding and fetches information.Although the drift coding can be potential powerful technology, its validity is stretched along with the redundancy of used code usually.More highly redundant is unfavorable for can be used for storing the memory span of actual user data.Usually only allow minimum redundancy, and this may reduce the validity of code when the reply drift.
Summary of the invention
An embodiment of one aspect of the invention provides a kind of method of the state for determining phase-changing memory unit.The method comprises:
Depend on a plurality of measurements of the subthreshold current comparison voltage characteristic of unit;
Process and measure to obtain to depend on described current ratio to the tolerance of the slope of voltage characteristic; And
State according to described tolerance determining unit.
In some embodiments of the invention, use following tolerance, this tolerance depends on the slope of subthreshold current comparison voltage (I/V) characteristic of unit, i.e. I/V characteristic slope below the threshold value switched voltage.The slope dependent of subthreshold value I/V characteristic in resistance differential (being the resistance derivative), but do not rely on any absolute resistance value.Although cell resistance is as discussed above like that along with the time marked change, the slope of I/V characteristic keeps along with the time is almost constant in the subthreshold value scope.This is because subthreshold value I/V slope is the function of the active volume of the Amorphous Phase in the unit.Effectively the amorphous state volume is again the good measurement of location mode and is the measurement that is not subjected to drift about and affects in particular, because known drift does not affect the geometric configuration (suppose to drift about and bury in oblivion, still do not affect total amorphous state volume owing to the defective in the Amorphous Phase) of Amorphous Phase.
Embody certain methods of the present invention and utilize the location mode tolerance of subthreshold value I/V slope to obtain basically not change along with drift.Particularly, the tolerance of using is not in some embodiments of the invention affected by drift basically, and namely it keeps along with the time substantial constant except inevitable noise fluctuations.Because subthreshold value I/V slope is the function of the effective amorphous state volume the unit in, and therefore be the function that location mode is measured, so aforementioned tolerance also is the characteristic of location mode and so can be used for distinguishing between the different conditions in MLC PCM then.As described further below like that, to the experimental result of actual PCM cell array the demonstrate validity of this statement and the efficient that this tolerance is measured as location mode.Therefore, by using the tolerance of describing, the mode that the information that some embodiments of the present invention are provided for fetching is not drifted about to be affected is determined the method for the state of PCM unit.Method according to some embodiments of the invention can be not in relation to drift character itself and carry out any hypothesis, and can not cause the inherence loss of user's memory capacity.Thereby the MLC ability that the definite generally promotion of the location mode that therefore some embodiments of the present invention can provide improvement to be used for the PCM array strengthens and the efficient operation of PCM device.
Aforementioned tolerance can directly or indirectly depend on various ways the slope of subthreshold value I/V characteristic according to this slope.Main points are that tolerance is relevant with subthreshold value I/V slope in a certain mode, and therefore directly do not depend on the absolute resistance of unit, and the latter is as discussed above affected by drift.In other words, according to some embodiments of the present invention, can determine the PCM location mode based on tolerance independent or that basically be independent of absolute unit resistance.According to some embodiments of the present invention, for the tolerance of deriving, the unit is carried out at least two measurements, these measurements (direct or indirect) depend on subthreshold value I/V slope.As described further below such, can carry out more than two measurements to allow average and to improve accuracy.Then can process the final tolerance that gained measures to obtain the evaluation unit state with various ways.For example, some embodiment can comprise a plurality of measurements of carrying out cell current with the different units bias voltage, and tolerance depends on the function difference of the cell current of measuring with different bias voltages.Similarly, can cross over for different applying unit current measurements the voltage of unit, and tolerance can depend on the function difference of the cell voltage of measurement.Alternatively, for example can carry out a plurality of measurements of cell resistance by the difference on subthreshold value I/V curve, and tolerance can depend on the function difference of the cell resistance of measuring at described difference.In these examples, the specified function of the measured value of discussion can be measured value itself simply or can be a certain more complicated function of this value, for example logarithm.
Concrete mode according to tolerance determining unit state also can change in different embodiment.The details of this step can depend on the precise forms of cell type (progression), tolerance itself, and any technology that except the Elementary Measures derivation method, can also use, for example be used for further strengthening any additional correction technology that reads accuracy.In some preferred embodiments, can be simply tolerance (have or without any further processing) by relatively deriving come the determining unit state with one or more reference value of indicating the different units state.Although some embodiments of the present invention can be applied to two-stage PCM unit, be applied to multi-level unit especially favourable, more be a problem because drift in the MLC device.When being applied to determine the state of multi-level unit (being s level unit, wherein s＞2), method for optimizing can comprise the state that comes determining unit by a plurality of reference values of the s level of the tolerance of relatively deriving and indicating member.Such reference value can be used various ways, for example limit cell level aspect predetermined threshold, and these predetermined thresholds are defined for the border of measurement range, and these measurement ranges are mapped to the difference level that reads back.
An embodiment of second aspect present invention provides a kind of device of the state for determining phase-changing memory unit.This device comprises:
Metering circuit is for a plurality of measurements of the subthreshold current comparison voltage characteristic that depends on the unit; And
Controller, to obtain depending on described current ratio to the tolerance of the slope of voltage characteristic, its middle controller is suitable for the state according to described tolerance determining unit for the treatment of described measurement.
According to still another embodiment of the invention, determine the PCM location mode based on tolerance independent or that basically be independent of absolute unit resistance.
An embodiment of third aspect present invention provides a kind of phase change memory device, and this phase change memory device comprises:
Storer comprises a plurality of phase-changing memory units; And
Read/write device is used for reading the data with the recording phase change memory unit, and wherein read/write device comprises the device of state that is used for determining described memory cell according to second aspect present invention.
Description of drawings
Generally speaking, during here with reference to realization method Expressive Features of the present invention, can in embodying device of the present invention or equipment, provide character pair.
By example the preferred embodiments of the present invention are described now with reference to the following drawings:
Fig. 1 is the schematic block diagram that embodies phase change memory device of the present invention;
Fig. 2 shows the average programming curve for eight grades of PCM unit;
Fig. 3 illustrates the time dependence of executing alive PCM cell resistance in difference;
Fig. 4 shows the simple difference value metric counting circuit that is used for the generation unit state measurement in the device of Fig. 1;
Fig. 5 shows the result of the Fig. 3 after average is removed process;
Fig. 6 a and Fig. 6 b illustrated respectively the difference metric used before average is removed and time dependence afterwards in the device of Fig. 1;
The time dependence of Fig. 7 comparing unit resistance and the time dependence of difference metric;
Fig. 8 a and Fig. 8 b illustrate respectively the operation of Digital and analog implementation of metering circuit of the device of Fig. 1;
Fig. 9 relatively uses the impact on the drift that is used for location mode measurement not at the same level of difference metric of the device of original resistance tolerance and Fig. 1.
How Figure 10 changes along with the cell level of storage if showing mean difference tolerance; And
Figure 11 is the schematic diagram of PCM unit, effective amorphous state thickness of this schematic diagram indicating member.
Embodiment
Fig. 1 is the rough schematic view that embodies phase change memory device of the present invention.Device 1 comprises for the phase transition storage 2 of storing data at one or more integrated array of multistage PCM unit.Be single although show in the drawings, generally speaking, storer 2 can comprise the configuration of any hope of PCM storage unit, and the scope of this configuration is a plurality of storage sets from one single chip or nude film to each self-contained a plurality of storage chip packaging body for example.Read and carried out by read/write device 3 to storer 2 data writings.Device 3 comprises for thereby permission determining unit state is measured in the unit and the data of the data of the storage of therefore reading back write and read metering circuit 4 to PCM unit data writing and for carrying out.Circuit 4 can apply appropriate voltage by the word line in storer overall 2 and bit line array for the purpose that writes and read to be come indivedual PCM element address.Carry out this process with the known manner except the mode of following stationery volume description.As hereinafter more specifically as described in, read/write controller 5 is the operation of control device 3 generally, and comprises for measuring the derivation unit state measurement and be used for this tolerance is used for the function that location mode is determined (i.e. level detection) according to reading.Generally speaking, can in hardware or software or its combination, implement the function of controller 5, but for the former thereby general preferred use hardwired logic circuit of operating speed.Suitably implementation will be clear by those skilled in the art according to the description here.Shown in the piece 6 among Fig. 6, to the user data of equipment 1 input usually in the processing that writes that is subject to a certain form as data writing before read/write device 3 supplies, such as the coding that is used for the error correction purpose.Similarly, the readback data of device 3 outputs generally processes to recover former input user data by the processing module 7 that reads of for example carrying out codeword detection and error-correction operation.Module 6 and such processing of 7 are independent of location mode gauging system to be described, and need not here specifically to be discussed.
Each multi-level unit in the multi-level unit in the storer 2 can be arranged to s the predefine resistance stages that different amorphous states/the crystalline state state is corresponding from the unit, wherein s＞2.Limit the common interval of resistance value not at the same level and do not wait, typically drop in the log-domain.In this object lesson, s=8, wherein each unit can be stored eight grades, thereby three storages of each unit are provided.For to given unit data writing, circuit 4 applies potential pulse the unit is arranged to the state corresponding with the proper resistor level.How Fig. 2 changes along with being used for the applying voltage of PCM unit if illustrating cell resistance.This width of cloth illustrates for the average programming curve of 60 8 grades of PCM cellular arraies and is the logarithm that applies (on average) cell resistance R that potential pulse obtains for increasing degree Vg.Eight predefine resistance stages R0 to R7 are indicated by the horizontal line among the figure.The resistance of the left side of programming curve (in the left side of the dotted line vertical line of Vg=1.5 volt) demonstration programming is how initially along with voltage increases and reduces from 0 volt.This increases owing to the crystallization in the chalcogenide material of unit.The Vg=1.5 volt at this corresponding to maximum crystalline state.Subsequently, increase voltage and cause the increase fusing, thus the larger active volume of the Amorphous Phase in the generation unit.This increases the resistance of programming along right programming curve shown in the right side of the dotted line vertical line among the figure.According to conventional way, by programming comes unit data writing in the device of Fig. 1 to the unit on the right programming slope of the curve of Fig. 2.
The read memory unit relates to the state of determining unit, and namely detecting unit is configured to which the predefine level among the predefine level R0 to R7.In conventional device, this finishes by the direct measurement of carrying out cell resistance.Particularly, for the given measurement that voltage carries out cell current that applies, and calculate and use cell resistance as and the predefine level relatively with the location mode tolerance of determining unit state.In the subthreshold value zone of current ratio voltage (I/V) characteristic of unit, carry out this measurement, do not affect location mode thereby measure.The I/V characteristic is strong nonlinearity in the subthreshold value zone, wherein will measure different resistance at different bias voltages.Become clear in the drawing of the logarithm R of this comparison time from Fig. 3, the measuring resistance that wherein shows the PCM unit increases and reduces along with applying voltage.This width of cloth figure also clearly illustrates drift to the impact of resistance measurement.Particularly, the resistance of Amorphous Phase approx according to following formula along with the time increases: R (t)=R
0(t/t
0)
v, log R (t)=logR wherein
0+ Vlog (t/t
0), wherein v is the proportional drift index of volume of the Amorphous Phase in the active regions that is considered to the PCM unit.The drift index has been shown to be increased and increases along with temperature.Drift is the chance phenomenon that can be considered as nonstationary noise, therefore is difficult to prediction.
The device 1 of Fig. 1 uses a kind of method for the determining unit state, and the method is used the tolerance of the slope that depends on subthreshold value I/V characteristic.This can provide the tolerance that is independent of absolute unit resistance.For reading unit, read a plurality of measurements that metering circuit 4 depends on the subthreshold value I/V characteristic of unit.In this example embodiment, obtaining the simple metric relevant with subthreshold value I/V slope is at a certain bias voltage V
1Cell resistance R
1Logarithm from different voltage V
2Cell resistance R
2Logarithm between difference.Because subthreshold value I/V slope keeps along with the time is almost constant, so difference metric LogR
1-LogR
2To have same nature.In fact, although LogR
1And LogR
2The two will significantly fluctuate and increase along with the time on average, but their fluctuation with they are subtracted each other with remove them because the such mode of the common component due to the drift is relevant in a large number.Residual components is owing to mainly haveing nothing to do and not being noise and other fluctuation that is caused by drift.Note, this mode is not specifically supposed about the drift character as the function of time.Can effectively remove any any drift characteristic (being considered as the function of time).
In the read operation of device 1, metering circuit 4 detects and is applying first (subthreshold value) voltage V
1The time flow through the electric current I of unit
1With applying second (subthreshold value) voltage V
2The time electric current I
2To controller 5 output gained resistance measurement R
1=V
1/ I
1And R
2=V
2/ I
2 Controller 5 is calculated difference tolerance logR then
1-logR
2This can be implemented in the controller 5 in numeral or analog domain via simple differencing amplifier circuit as shown in Figure 4.Because gained tolerance depends on resistance difference, so tolerance depends on the slope of I/V characteristic, but do not rely on any absolute resistance (therefore being absolute current or voltage) value.As more early discussing, subthreshold value I/V slope is the function of the effective amorphous state volume in the unit and therefore is that location mode is measured.Then difference metric also is the characteristic of location mode.Therefore difference metric can be used for distinguishing between different storage levels and for explained above former thereby not affected by drift.This incites somebody to action by experiment result's following explanation and demonstrates.
First review Fig. 3, the measurement of the log that observes at different voltages ((t)) only differs constant.Therefore, the structure Relaxation of material (drift) should be independent of voltage in low-voltage (without annealing) at least.Employing is measured with explanation with drag:
r(t，V
i)＝R
i+w(t)
Wherein w (t) is the zero-mean function of time, R
iOnly depend on V
i, and r () is used for representing log (R ()).Therefore:
The average E of average that obtains with respect to the time is provided by following formula:
E[r(t，V
i)]＝Ri，
And therefore:
R (t, V
i)-E[r (t, V
i)]=w (t) for all (i).
This figure shows the result of the Fig. 3 after average is removed by Fig. 5 support.If consider at different voltage V now
i, V
kDifference DR (t, V between the paired r (t) that measures
I, k):
DR(t，V
i，k)＝r(t，V
i)-r(t，V
k)＝R
i-R
k
This difference is independent of (t), and namely comparison time is constant.Therefore, all waveform DR (t, V
I, k) should constant along with the time (slope=0).Note, this difference metric is not supposed drift characteristic anyly knows (being that w (t) can be arbitrarily).These predictions clearly are subject to Fig. 6 a and Fig. 6 b supports.Fig. 6 a for different voltages to V
i, V
kDrawn difference metric by logarithmic time, and Fig. 6 b shows at average removal (DR (t, V
I, k)-E[DR (t, V
I, k)]) afterwards identical result.
Fig. 7 shows as the difference metric D of the function of logarithmic time and the direct comparison between the conventional original resistance measurement (pressing the absolute resistance of logarithmic scale).Solid line provides the fitting a straight line for the result of each trace.This difference metric of more clearly demonstrating still less depends on original tolerance.Therefore difference metric can provide and basically not change with drift and do not understand still exercisable measurement of drift characteristic (for example whether logR (t) is proportional with log (t) or any other drift model).
Although above use naive model to measure with explanation, the model of more refining (jointly drift model) of the R (t) in different voltage measurements is considered in the power law behavior that can suppose the R comparison time.According to the standard drift model:
Log[R (t)]=α (R
0)+vlogt, wherein R
0=R (0), v: drift power law index, and hypothesis t
0=1 and be without loss of generality.
The use model of refining:
log[R(t，V
i)]＝α(R
0，V
i)+(v+w
i)logt
Average E wherein
i{
Wi}=0, v depends on the R level, and w
i＜＜v, difference metric is got following form:
log[R(t，V
i)]-log[R(t，V
k)]＝[α(R
0，V
i)-α(R
0，V
k)]+(w
i-w
k)logt。
In square bracket first here is the measurement of R (0) and has along with | V
i-V
k| the value of growth.Second is the minorant (w of time
i＜＜v).Then can be by the quality (time invariance, variance) that on average improves tolerance:
E{log[R(t，V
i)]-log[R(t，V
k)]}＝E[α(R
0，V
i)-α(R
0，V
k)]
This formula illustrates without time dependence.Here can average to Vi, Vk to a plurality of different voltages.Can in the device of Fig. 1, implement such averaging process with plain mode.At the unit during read operations, metering circuit 4 detects the cell current that applies bit line (BL) voltage in some differences.This is illustrated for the simulation embodiment for the digital circuit mode and in Fig. 8 b in Fig. 8 a.To the gained resistance measurement (V/I) of controller 5 supply at each voltage, this controller calculate the paired difference between these resistance values and with the result on average to obtain final mean difference tolerance.
Fig. 9 will compare for the slope of the mean difference of different units level tolerance comparison time waveform and the slope that is used for the equivalent waveform that original (definitely) resistance measures.These slopes are estimations of drift index, and the result is clearly shown that the more dominance energy of mean difference tolerance.
Drift-the resistance of the difference metric of having demonstrated is that location mode is measured, and solves now level differentiation problem.For effectively, measure the level detection that certainly must depend on level and realize ideally having good nargin.How Figure 10 changes along with the resistance stages of storage if showing mean difference tolerance, wherein described above like that to a plurality of voltages to being averaged.This demonstration difference metric is fully distinguished between the memory resistor level that will measure as effective location mode.Can be by comparing execution level to detect with a plurality of predetermined reference values for the mean difference tolerance that the unit obtains in the controller 5 of device 1.Reference value can be for example corresponding to the precalculated metric that limits the different units level or such as lower threshold value, these threshold values are limited to the border between the corresponding metric scope that is considered as being mapped to the different units level.Therefore the simple tolerance of relatively calculating and reference value produce the cell level of storage in controller 5.As discussed above such, then the gained readback data is used for further reading by controller 5 outputs processes so that restoring user data.
To understand, by utilizing the location mode tolerance of describing, above-described embodiment can be implemented a kind of for the definite new technology of PCM location mode, and the information of wherein fetching is not affected by drift basically.This technology can not carried out any hypothesis about drift character itself, and it does not cause any inherent user's memory capacity loss yet.Therefore device 1 can consist of novel MLCPCM device, and the new location mode measurement technology of this devices use is to provide and strengthening the property that the implementation simplicity is combined.
Certainly will understand and to carry out many changes and modification to above-described example embodiment.For example it is contemplated that various other tolerance that depend on PCM unit subthreshold value I/V characteristic.Can obtain another simply is measured as in the difference between the logarithm of the cell current of different bias voltage Vi, Vk or equivalence and is the difference between the logarithm in the measuring voltage of different steady current level.Although use the logarithm of the quantity detect here, can when measuring, calculated difference use other function or even the value that detects itself of these quantity.In addition, although simple difference measurements provides the rough figure of I/V slope is approached (yet this rough figure approach have the characteristic similar to the I/V slope (time invariance, R level dependence)), if hope can use better numerical value to approach and the better numerical value of this utilization approaches the accuracy that raising can be provided.It is the theme that does much research on that the numerical value of function derivative is approached, and the various possibilities here will be clear by those skilled in the art.Other relevant with subthreshold value I/V slope may be measured in the consideration of the difference metric that proposes from this background of analysis expression to the above conduction the subthreshold value scope and become clear.Hereinafter with reference to Figure 11 object lesson is described.
Figure 11 is the schematic diagram of PCM unit, wherein shade hemisphere representative unit, thickness is t
GstThe active volume of enlivening the Amorphous Phase in the volume.The amorphous state volume has as shown in FIG. net thickness u
aThink that the conduction in the amorphous state chalkogenide jumps owing to the hot activation of charge carrier between local defect state (trap).Two main models that are used for the conduction that is subjected to the trap restriction of Amorphous Phase be for high defect concentration pul (Poole) conduction (Ielmini-Zhang) and for pul-Frank (Poole-Frenkel) conduction of fabricating low-defect-density.These models are at temperature T, effective amorphous state thickness U
aExpress cell current I to applying the dependence of voltage V with various other parameter aspects.Aspect the pul conduction model, can show difference metric:
Wherein dz is distance between the average trap, k
BBe Boltzmann constant, and q is the electric charge on the electronics.Similarly, can estimate u
aFor:
The effective amorphous state thickness u that estimates in this way
aCan in alternative of the present invention, be used as location mode tolerance.
Similarity analysis for pul-Frank model shows difference metric:
Wherein ε is effective dielectric constant.Similarly, can estimate
For:
The parameter of estimating in this way
Also can in alternative, be used as location mode tolerance.
If note wishing, then embodiments of the invention can utilize other technology to improve performance with above-described location mode gauging system.Location mode gauging system and other technology make up to tackle the performance that drift can be given special enhancing advisably such as coding.As another example, can take based on the correction technology of reference unit or model as the basis, on dynamic basis, for example be updated in termly the reference value that level is used in detecting.Also can be by the uncorrelated noise in along route discussed above the result on average being suppressed to measure.
Can carry out many other changes and modification and do not depart from the scope of the present invention the example embodiment of describing.
Claims (15)
1. method of be used for determining the state of phase-changing memory unit, described method comprises:
Depend on a plurality of measurements of the subthreshold current comparison voltage characteristic of described unit;
Process described measurement to obtain depending on described current ratio to the tolerance of the slope of voltage characteristic; And
Determine the state of described unit according to described tolerance.
2. the method for claim 1 is used for determining the state of s level phase-changing memory unit, s＞2 wherein, and described method comprises by described tolerance and a plurality of reference values of the described s level of the described unit of indication being compared to determine the state of described unit.
3. such as claim 1 or 2 described methods, be included in a plurality of measurements that the different units bias voltage carries out cell current, wherein said tolerance depends on the difference at the function of the measured cell current at described different bias voltages place.
4. such as claim 1 or 2 described methods, comprise a plurality of measurements of crossing over the voltage of described unit for described different applying unit electric current, wherein said tolerance depends on the difference at the function of the described different measured cell voltage that applies the electric current place.
5. such as claim 1 or 2 described methods, be included in described current ratio is carried out cell resistance to the difference place on the voltage characteristic a plurality of measurements, wherein said tolerance depends on the difference at the function of the measured cell resistance at described difference place.
6. such as the described method of arbitrary claim in the claim 3 to 5, the function of wherein said measured value comprises the logarithm of this value.
7. such as the described method of arbitrary aforementioned claim, wherein said tolerance depends on the effective amorphous state thickness (u in the described unit
a).
8. method as claimed in claim 7, wherein said tolerance comprises the effective amorphous state thickness (u in the described unit
a) estimation.
9. such as the described method of arbitrary aforementioned claim, carry out the described measurement more than two, wherein said processing comprises meaning process.
10. device of be used for determining the state of phase-changing memory unit, described device comprises:
Metering circuit (4) is for a plurality of measurements of the subthreshold current comparison voltage characteristic that depends on described unit; And
Controller (5), to obtain depending on described current ratio to the tolerance of the slope of voltage characteristic, wherein said controller (5) is suitable for determining according to described tolerance the state of described unit for the treatment of described measurement.
11. device as claimed in claim 10, be used for determining the state of s level phase-changing memory unit, s＞2 wherein, described controller (5) are suitable for by described tolerance and a plurality of reference values of the described s level of the described unit of indication being compared to determine the state of described unit.
12. such as claim 10 or 11 described devices, wherein said metering circuit (4) is suitable for carrying out at different units bias voltage place a plurality of measurements of cell current, and wherein said tolerance depends on the difference in the function of the measured cell current at described different bias voltages place.
13. such as claim 10 or 11 described devices, wherein said metering circuit (4) is suitable for a plurality of measurements of crossing over the voltage of described unit for described different applying unit electric current, and wherein said tolerance depends on the difference at the function of the described different measured cell voltage that applies the electric current place.
14. such as claim 10 or 11 described devices, wherein said metering circuit (4) is suitable in described current ratio the difference place on the voltage characteristic being carried out a plurality of measurements of cell resistance, and wherein said tolerance depends on the function difference in the measured cell resistance at described difference place.
15. a phase change memory device (1) comprising:
Storer (2) comprises a plurality of phase-changing memory units; And
Read/write device (3), be used for reading and writing the data of described phase-changing memory unit, wherein said read/write device (3) comprises the device such as the described state for memory cell as described in determining of the arbitrary claim in the claim 10 to 14.
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| EP10174613.9 | 2010-08-31 | ||
| EP10174613 | 2010-08-31 | ||
| PCT/IB2011/053757 WO2012029007A1 (en) | 2010-08-31 | 2011-08-26 | Cell-state determination in phase-change memory |
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| CN (1) | CN103081018B (en) |
| DE (1) | DE112011102156T5 (en) |
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| DE102022125340A1 (en) * | 2022-09-30 | 2024-04-04 | TechIFab GmbH | DEVICES AND METHODS FOR READING A MEMRISTIVE COMPONENT |
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| US20100182827A1 (en) * | 2009-01-22 | 2010-07-22 | Sergey Kostylev | High Margin Multilevel Phase-Change Memory via Pulse Width Programming |
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| DE10036140C1 (en) * | 2000-07-25 | 2001-12-20 | Infineon Technologies Ag | Non-destructive read-out of MRAM memory cells involves normalizing actual cell resistance, comparing normalized and normal resistance values, detecting content from the result |
| US6650562B2 (en) * | 2002-01-23 | 2003-11-18 | Hewlett-Packard Development Company, L.P. | System and method for determining the logic state of a memory cell in a magnetic tunnel junction memory device |
| US8116123B2 (en) * | 2008-06-27 | 2012-02-14 | Seagate Technology Llc | Spin-transfer torque memory non-destructive self-reference read method |
| US7929338B2 (en) * | 2009-02-24 | 2011-04-19 | International Business Machines Corporation | Memory reading method for resistance drift mitigation |
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| US20100182827A1 (en) * | 2009-01-22 | 2010-07-22 | Sergey Kostylev | High Margin Multilevel Phase-Change Memory via Pulse Width Programming |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109074842A (en) * | 2016-04-07 | 2018-12-21 | 赫姆霍兹-森德拉姆德雷斯顿-罗森多夫研究中心 | For running the method and device and its as the purposes of artificial synapse of the resistance switch for the memristor that can reconstruct to complementary simulation |
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| CN103081018B (en) | 2016-06-22 |
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| GB2496822A (en) | 2013-05-22 |
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