CN103077901B - Packaging method of semiconductor package and semiconductor package formed by using same - Google Patents

Abstract

A packaging method of a semiconductor package and a semiconductor package formed by applying the same are provided. The semiconductor package comprises a substrate, a chip and a package body. The chip is provided with a first surface facing the substrate and a second surface far away from the substrate. The packaging body wraps the chip and is provided with a groove and an upper surface, the upper surface of the packaging body is higher than or aligned to the second surface of the chip, the groove is connected with the upper surface of the packaging body and is exposed out of the second surface of the chip, and the bottom surface of the groove is lower than the second surface of the chip.

Description

Packaging method of semiconductor package and semiconductor package formed by using same

technical field

The present invention relates to a packaging method of a semiconductor package and a semiconductor package formed using the same, and in particular to a packaging method of a semiconductor package that improves heat dissipation and a semiconductor package formed using the same.

Background technique

A conventional semiconductor package includes a chip and a package. In order to protect the chip, the package usually covers the side and upper surface of the chip. However, such a complete encapsulation is not easy to dissipate the heat of the chip.

In addition, if the upper surface and side edges of the chip are completely exposed to the outside world, although it has a better heat dissipation effect, it is easy to cause the risk of damage to the chip due to external force collision.

Contents of the invention

The invention relates to a semiconductor package. In one embodiment, the known problem of poor heat dissipation of the chip can be improved and the risk of the chip being damaged by external impact can be reduced.

According to the present invention, a packaging method for a semiconductor package is provided. A packaging method for a semiconductor package includes the following steps. Provide an upper mold and a lower mold, the upper mold includes a deformable element; set a substrate and a chip on the lower mold, wherein the chip is arranged on the substrate and is located directly below the deformable element and has an upper surface; The upper mold forms a mold cavity, so that the deformable element squeezes the chip to form a ring-shaped protrusion. A bottom surface of the ring-shaped protrusion is lower than the upper surface of the chip, and after the lower mold and the upper mold are closed, the mold cavity A top surface of the upper mold is aligned with or higher than the upper surface of the chip; and, a packaging material is filled in the mold cavity between the upper mold and the lower mold, wherein the packaging material wraps the chip and covers the top surface of the mold cavity.

According to the present invention, a semiconductor package is proposed. The semiconductor package includes a substrate, a chip and a package. The chip has a first surface facing the substrate and a second surface away from the substrate. The package covers the chip and has a groove and an upper surface, the upper surface of the package is higher than or aligned with the second surface of the chip, wherein the groove is connected to the upper surface of the package and exposes the second surface of the chip, and The bottom surface of the groove is lower than the second surface of the chip.

In order to make the above content of the present invention more obvious and understandable, the following specific examples are given in conjunction with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1A is an external view of a semiconductor package according to an embodiment of the invention.

Fig. 1B is a cross-sectional view along the direction 1B-1B' in Fig. 1A.

FIG. 2 is a schematic diagram of the test semiconductor package of FIG. 1B .

3A to 3C are diagrams illustrating the manufacturing process of the semiconductor package shown in FIG. 1B .

Description of main component symbols:

100: semiconductor package

110: Substrate

110u, 130u: upper surface

120: chip

120b: first surface

120u: second surface

120s: side

121, 140: electrical contacts

130: Encapsulation

130': Encapsulation material

130b, 221b, 2131b: bottom surface

130r: groove

130r1: first subgroove

130r2: second subgroove

130s: medial side

150: platen

160: Test pin

210: upper mold

211: Upper Phantom

212: Middle plate

212r, 221r: concave part

213: Deformable elements

213s1: outside

213s2: inside

2131: Annular protrusion

220: lower mold

221: Lower mold body

222: Loading board

230r: mold cavity

230u, 212u: top surface

2131: Annulus

D1, D2: inner diameter

H1, H2, H3, H4, H5: Distance

P: compressed thickness

S: mold flow space

T1, T2: Thickness

Detailed ways

Please refer to FIG. 1A , which shows an appearance view of a semiconductor package according to an embodiment of the present invention. The semiconductor package 100 includes a substrate 110 , a chip 120 , a package 130 and at least one electrical contact 140 .

The substrate 110 may be an organic substrate, a ceramic substrate 110 , a silicon substrate, a metal carrier or an interposer substrate. In addition, the substrate 110 may be a single-layer or multi-layer circuit substrate.

Please refer to FIG. 1B, which shows a cross-sectional view along the direction 1B-1B' in FIG. 1A. The chip 120 is disposed on the upper surface 110u of the substrate 110 with its active surface (for example, the first surface 120b of the chip 120 facing the substrate 110 ) facing downwards, and is electrically connected to the substrate 110 through at least one electrical contact 121. Such a chip 120 is called a flip chip. The electrical contacts 121 are, for example, bumps, solder balls or conductive pillars.

The package body 130 covers the side surface 120s of the chip 120 and has a groove 130r. The groove 130r exposes the second surface 120u of the chip 120 away from the substrate 110 . In this example, the groove 130r exposes the entire second surface 120u of the chip 120 so as to provide a maximum exposed area to quickly dissipate the heat of the chip 120 to the outside of the semiconductor package 100 .

The bottom surface 130b of the groove 130r is lower than the second surface 120u of the chip 120 but higher than the first surface 120b of the chip 120 . Since the bottom surface 130b of the groove 130r is higher than the first surface 120b of the chip 120 , a mold flow space S is formed between the bottom surface 130b of the groove 130r and the first surface 120b of the chip 120 . During the packaging process, the flowing packaging material 130 ′ ( FIG. 3C ) can smoothly fill the space between the first surface 120 b of the chip 120 and the upper surface 110 u of the substrate 110 through the mold flow space S to cover the circuit board. sex contact 121 .

In one example, the distance H1 between the upper surface 130u of the package 130 and the second surface 120u of the chip 120 is between 0 and 110 microns, and the distance H2 between the second surface 120u of the chip 120 and the bottom surface 130b of the groove 130r is between Between 0 and 110 micrometers, the distance H3 between the upper surface 130 u of the package body 130 and the bottom surface 130 b of the groove 130 r (the sum of the distances H1 and H2 ) is between 0 and 220 micrometers. In addition, the thickness T1 of the chip 120 is about 800 microns, but it can also be thinner or thicker. The values of the distances H1, H2 and H3 can also be adjusted according to the thickness of the chip. According to an embodiment of the present invention, the distances H2 and H1 are lower than the distance H3, which can avoid the problem of lower reliability caused by the exposure of the upper surface of the substrate.

The groove 130r extends from the upper surface 130u of the package 130 toward the chip 120 and the substrate 110 , so that the groove 130r is connected to the upper surface 130u of the package 130 and exposes the second surface 120u of the chip 120 . The groove 130r includes a first sub-groove 130r1 and a second sub-groove 130r2. The first sub-recess 130r1 communicates with the second sub-recess 130r2 and exposes the second surface 120u of the chip 120 , for example, exposing the entire second surface 120u of the chip 120 , so as to improve the cooling effect on the chip 120 .

The inner diameter D1 of the second sub-groove 130r2 is tapered from the upper surface 130u of the package body 130 to the bottom surface 130b of the groove 130r to form a bowl-shaped groove, a V-shaped groove or other suitable groove contours. In this example Take the bowl-shaped groove as an example. Regarding the profile of the second sub-groove 130r2, the inner surface 130s of the second sub-groove 130r2 extends from the upper surface 130u of the package body 130 toward the substrate 110 for a distance H3, and then extends toward the second surface 120u of the chip 120. The direction extends to the side 120s of the chip 120 . When the contact between the inner surface 130s of the second sub-recess 130r2 and the side surface 120s is closer to the second surface 120u of the chip 120 , the package body 130 covers a larger area of the side surface 120s of the chip 120 . In this example, the inner surface 130s of the second sub-recess 130r2 contacts the corner of the second surface 120u and the side surface 120s of the chip 120 , so that the package body 130 can cover the entire side surface 120s of the chip 120 .

Please refer to FIG. 2 , which is a schematic diagram of the test semiconductor package shown in FIG. 1B . When the semiconductor package 100 is tested, the pressure plate 150 is pressed against the semiconductor package 100 so that the electrical contacts 140 are electrically contacted with the test pins 160 . Since the upper surface 130u of the package body 130 in this embodiment is higher than the second surface 120u of the chip 120, the pressure plate 150 contacts the upper surface 130u of the package body 130 without directly pressing against the chip 120, thereby reducing the probability of damage to the chip 120 .

In another example, the upper surface 130u of the package body 130 and the second surface 120u of the chip 120 may be substantially aligned, eg coplanar. Under this design, the pressure plate 150 presses against the second surface 120u of the chip 120 and the upper surface 130u of the package body 130 at the same time, so that the chip 120 and the package body 130 share the compressive stress, thus reducing the compressive stress of the chip 120 itself , thereby reducing the probability of damage to the chip 120 .

Please refer to FIG. 3A to FIG. 3B , which illustrate the manufacturing process of the semiconductor package shown in FIG. 1B .

As shown in FIG. 3A , an upper mold 210 and a lower mold 220 are provided. The upper mold 210 includes an upper mold body 211, a middle plate 212 and a deformable element 213, wherein the middle plate 212 is arranged on the upper mold body 211, the middle plate 212 has a recess 212r with an opening facing the lower mold 220, and the deformable element 213 is set on the top surface 212u of the concave portion 212r of the middle plate 212 . The inner diameter D2 of the concave portion 212r is tapered from the top surface 212u of the concave portion 212r toward the opening direction of the concave portion 212r, so that the deformable element 213 disposed therein will not be easily dropped. The deformable element 213 is, for example, made of rubber or a suitable elastic material. With this material property, the deformable element 213 is easily installed in the concave portion 212r of the middle plate 212, and after being installed in the concave portion 212r, a resilient force is produced. The wall surface of the concave portion 212r is pressed, and further stabilized in the concave portion 212r.

The lower mold 220 includes a lower mold body 221 and a supporting plate 222 . The lower mold body 221 has a concave portion 221r, and the bearing plate 222 can be disposed on the bottom surface 221b of the concave portion 221r. The supporting plate 222 can be lifted up and down to adjust the height position of the substrate 110 disposed thereon.

As shown in FIG. 3A , the substrate 110 and the chip 120 are disposed at the bottom of the lower mold 220 , wherein the substrate 110 is disposed on the carrier plate 22 , and the chip 120 is disposed on the substrate 110 through electrical contacts 121 and is located directly below the deformable element 213 .

As shown in FIG. 3B , the lower mold 220 and the upper mold 210 are clamped. For example, the upper mold 210 moves toward the direction of the lower mold 220 to close the mold. During the process, the deformable element 213 is pressed by the chip 120 to form an annular protrusion 2131 on the side surface 120s of the chip 120, wherein the annular protrusion 2131- The ring-shaped protrusion surrounds the side surface 120s of the chip 120 and the bottom surface 2131b of the ring-shaped protrusion 2131 is lower than the second surface 120u of the chip 120 .

After the upper mold 210 and the lower mold 220 are closed, the deformable element 213 is compressed to a compressed thickness P, and the compressed thickness P can be determined by the following formula (1).

P=(T2+H5)-H4................................... ........(1)

In formula (1), thickness T2 ( FIG. 3A ) is the initial thickness of the deformable element 213, the distance from the top surface 212u of the plate 212 to the upper surface 110u of the substrate 110 in distance H4, and the distance from the second surface 120u to the second surface 120u of the chip 120 in distance H5 The distance from the upper surface 110u of the substrate 110 . Through proper design of the compression thickness P (i.e. design of the compressibility of the deformable element 213), the deformable element 213 is tightly pressed against the second surface 120u of the chip 120, so as to avoid or reduce the fluid packaging material 130' in the subsequent process. ( FIG. 3C ) flows between the deformable element 213 and the chip 120 to cover the second surface 120u of the chip 120 .

In this example, the compressed thickness P is smaller than the thickness T1 of the chip 120 , so that the bottom surface 2131 b of the annular protrusion 2131 is higher than the first surface 120 b of the chip 120 . In one example, the thickness T1 of the chip 120 is, for example, about 800 microns; however, a thinner or thicker chip can also be used. If so, the thickness T2 and the compressive thickness P of the deformable element 213 can be adjusted to obtain a desired or preset The geometry of the annular protrusion 2131. Since the bottom surface 2131b of the annular protrusion 2131 is higher than the first surface 120b of the chip 120, a mold flow space S is formed between the bottom surface 2131b of the annular protrusion 2131 and the first surface 120b of the chip 120. The mold flow space S The fluid packaging material 130 ′ ( FIG. 3C ) can smoothly flow to the space between the first surface 120 b of the chip 120 and the substrate 110 .

After the upper mold 210 and the lower mold 220 are molded together, the top surface 230u of the middle plate 212 is higher than or substantially aligned with the second surface 120u of the chip 120 . In one example, the distance H1 between the top surface 230u of the middle plate 212 and the second surface 120u of the chip 120 is between 0 and 110 microns, and the distance H2 between the second surface 120u of the chip 120 and the bottom surface 2131b of the annular protrusion 2131 The distance between the top surface 230u of the middle plate 212 and the bottom surface 2131b of the annular protrusion 2131 is between 0 and 110 microns, and the distance is between 0 and 220 microns.

When the upper mold 210 and the lower mold 220 are closed, a cavity 230 r is formed between the middle plate 212 of the upper mold 210 and the supporting plate 222 of the lower mold 220 . The contour of the mold cavity 230r can determine the outer contour of the subsequently formed package body 130, but the embodiment of the present invention does not limit the contour shape of the mold cavity 230r, so the outer contour of the package body 130 can have various geometric forms.

As shown in FIG. 3C, the packaging material 130' of high temperature fluidity is filled in the mold cavity 230r, wherein the packaging material 130', after contacting the outer side 213s1 of the annular protrusion 2131, bypasses the bottom surface 2131b of the annular protrusion 2131 to the annular protrusion The inner side 213s2 of the portion 2131 covers at least a part of the side surface 120s of the chip 120 . In addition, the packaging material 130' also enters the space between the first surface 120b of the chip 120 and the upper surface 110u of the substrate 110 through the mold flow space S between the bottom surface 2131b of the annular protrusion 2131 and the upper surface 110u of the substrate 110, For covering the electrical contacts 121 , under this design, the extra underfill can be omitted. In addition, after the packaging material 130' is filled, the packaging material 130' covers the top surface 230u of the mold cavity 230r to form the upper surface 130u of the packaging material 130'. The encapsulation material 130' is cooled and solidified to become the encapsulation body 130 shown in FIG. 1B . So far, the semiconductor package 100 as shown in FIG. 1A is formed.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (11)

1. a method for packing for semiconductor package part, is characterized in that, comprising:

There is provided a patrix and a counterdie, this patrix comprises one can deformation element;

Arrange a substrate and a chip on this counterdie, wherein this chip to be located on this substrate and to be positioned at this and can have a upper surface immediately below deformation element;

This counterdie of matched moulds and this patrix form a die cavity, this can extrude this chip and forms a ring-type teat by deformation element, one bottom surface of this ring-type teat is lower than this upper surface of this chip, and this counterdie and this patrix are after matched moulds, end face alignment or this upper surface higher than this chip of this die cavity; And

Fill in an encapsulating material this die cavity between this counterdie and this patrix, wherein this encapsulating material this chip coated and cover this end face of this die cavity.

2. method for packing as claimed in claim 1, is characterized in that, in the step of this counterdie of matched moulds and this patrix, this bottom surface of this ring-type teat is higher than a lower surface of this chip.

3. method for packing as claimed in claim 1, is characterized in that, in arranging this chip and this substrate in the step of this counterdie, this chip is located on this substrate with an electrical contact; In filling in this encapsulating material this step in this die cavity, this encapsulating material is filled in this electrical contact coated between this chip and this substrate.

4. method for packing as claimed in claim 1, it is characterized in that, this counterdie comprises:

One lower mold body, has a recess; And

One loading plate, is located at this recess of this lower mold body;

In arranging this chip and this substrate in this step of this counterdie, this substrate is located on this loading plate.

5. method for packing as claimed in claim 1, it is characterized in that, this can be made up of rubber by deformation element.

6. a semiconductor package part, is characterized in that, comprising:

One substrate, has a upper surface;

One chip, have one in the face of the first surface and of substrate is away from the second surface of this substrate, the first surface of this chip is located at the upper surface of this substrate and is electrically connected at this substrate; And

One packaging body, this chip coated, this packaging body has a groove and a upper surface, this upper surface of this packaging body higher than or be aligned in this second surface of this chip, this groove has a bottom surface, wherein this groove is connected with this upper surface of this packaging body and exposes this second surface of this chip, and this bottom surface of this groove is lower than this second surface of this chip.

7. semiconductor package part as claimed in claim 6, it is characterized in that, this groove exposes this second surface whole of this chip.

8. semiconductor package part as claimed in claim 6, it is characterized in that, this chip has a side, and this packaging body covers this side of this chip at least partially.

9. semiconductor package part as claimed in claim 6, it is characterized in that, this groove comprises one first sub-groove and one second sub-groove, and this first sub-groove exposes this second surface of this chip, and this second sub-groove is around a side of this chip.

10. semiconductor package part as claimed in claim 6, is characterized in that, this bottom surface of this groove is higher than the lower surface of this chip.

11. semiconductor package parts as claimed in claim 6, is characterized in that, more comprise:

One electrical contact, is electrically connected this chip and this substrate between this first surface and this substrate of this chip;

Wherein, this packaging body is formed at this electrical contact coated between this chip and this substrate.