CN103077736B - A kind of can the OCD module of compatible DDR2 and DDR3 - Google Patents
A kind of can the OCD module of compatible DDR2 and DDR3 Download PDFInfo
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- CN103077736B CN103077736B CN201210563555.8A CN201210563555A CN103077736B CN 103077736 B CN103077736 B CN 103077736B CN 201210563555 A CN201210563555 A CN 201210563555A CN 103077736 B CN103077736 B CN 103077736B
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Abstract
The invention provides a kind of can the OCD module of compatible DDR2 and DDR3, comprising: the driver element of DDR3 dispensing unit, DDR3 alignment unit and multiple parallel connection, also comprises DDR2 dispensing unit, DDR2 alignment unit and alternative unit; Alternative unit comprises configuration alternative unit and calibration alternative unit; DDR2 dispensing unit and DDR3 dispensing unit are connected with configuration alternative unit respectively; DDR2 alignment unit and DDR3 alignment unit are connected with calibration alternative unit respectively; Configuration alternative unit is connected with the driver element of multiple parallel connection respectively with calibration alternative unit; Is this invention than existing relevant DDR3? is DRAM output module technical compatibility good, and switches to DDR2? DRAM output module is simple, low price.
Description
Technical field
The invention belongs to chip design field, relate to a kind of can the OCD module of compatible DDR2 and DDR3.
Background technology
The OCD of DRAM is the output interface module that dram chip communicates with the external world, and the output interface characteristic difference of DDR3DRAM and DDR2DRAM is large, and the OCD linearity of usual DDR3DRAM, frequency of operation is all high than DDR2DRAM.
Existing traditional DDR3OCD module see Fig. 1, by DDR3 drive arrangements unit, DDR3 alignment unit and 8 driver elements (numbering 1 ~ 8) in parallel;
8 driver elements are just the same, and they determine the final output resistance of OCD.The input data signal of 8 driver elements all links data_in, and outputting data signals all links data_out; Input data (data_in) is also high level for OCD during high level exports (data_out), and when data_in is low level, data_out is also low level; 8 drive unit drives resistance are all determined by driving resistance signalization strength<5:0>; The selection of 8 driver elements is respectively by sel<1>, sel<2> ... sel<8> controls; When sel<n> is high level, represent the n-th driver element work, when sel<n> is low level, represent that the n-th driver element is closed;
Produced by DDR3 dispensing unit see Fig. 2, sel<8:1>; DDR3 dispensing unit can arrange total how many driver module job; The DDR3DRAM of standard must provide 2 kinds of configurations, is controlled by control signal mode_34, and when mode_34 is low level (0), output impedance is 40 ohm; When mode_34 is high level (1), output impedance is 34.3 ohm;
Alignment unit arranges the output resistance of each driver element, it ensures when any voltage, temperature and process deviation by producing signal strength<5:0>, and the output resistance of each driver element is RZQ (normally 240 ohm);
See Fig. 3, existing traditional DDR2OCD module only has a driver element, and it determines the final output resistance of OCD; The input data signal of driver element links data_in, and outputting data signals links data_out; Input data (data_in) is also high level for OCD during high level exports (data_out), and when data_in is low level, data_out is also low level; Drive unit drives resistance is all determined by driving resistance signalization strength_d<5:0>;
See Fig. 4, the DDR2OCD of standard must provide complete and drive and half drive pattern, and dispensing unit realizes full driving and half setting driven by producing strenghth_d<5:0> to control signal strength<5:0> recompile; When mode setting signal mode_half is low level (0), OCD is set to full drive pattern, and output resistance is 20 ohms; When mode_half is high level (1), OCD is set to half drive pattern, and output resistance is 40 ohms;
Alignment unit arranges the output resistance of driver element, it ensures when any voltage, temperature and process deviation by producing signal strength<5:0>, and the output resistance of driver element is 20 ohm (full drive patterns) or 40 ohm (half drive pattern);
The price of the DDR2 of identical capacity is often higher than DDR3DRAM a lot of in the market, so be badly in need of design one can just seem quite have marketable value by compatible DDR2 and DDR3DRAM.
Summary of the invention
In order to solve the technical matters existed in background technology, the invention provides a kind of can the OCD module of compatible DDR2 and DDR3; When the price of DDR2DRAM price higher than DDR3DRAM, by simple setting, the OCD of DDR3 can be switched to the OCD of DDR2;
Technical solution of the present invention is:
The invention provides a kind of can the OCD module of compatible DDR2 and DDR3, comprising: the driver element of DDR3 dispensing unit, DDR3 alignment unit and multiple parallel connection, its special character is: also comprise DDR2 dispensing unit, DDR2 alignment unit and alternative unit; Above-mentioned alternative unit comprises configuration alternative unit and calibration alternative unit; Above-mentioned DDR2 dispensing unit and DDR3 dispensing unit are connected with configuration alternative unit respectively; Above-mentioned DDR2 alignment unit and DDR3 alignment unit are connected with calibration alternative unit respectively; Above-mentioned configuration alternative unit is connected with the driver element of multiple parallel connection respectively with calibration alternative unit; Above-mentioned DDR3 dispensing unit is for selecting the production of signal; Above-mentioned DDR3 alignment unit is for arranging the output resistance of each driver element;
The control signal of above-mentioned calibration alternative unit and configuration alternative unit, OCD is set to DDR3OCD pattern or DDR2OCD pattern with configuration alternative unit by the Automatic level control calibration alternative unit according to control signal, wherein, when DDR3OCD or DDR2OCD pattern, use DDR3 alignment unit or DDR2 alignment unit that the resistance value of multiple driver element is set respectively, and, when DDR3OCD pattern, DDR3 dispensing unit is used to select 7 (RZQ/7 patterns) or 6 (RZQ/6 pattern) driver element work, when DDR2OCD pattern, DDR2 dispensing unit is used to select 8 (full drive patterns) or 4 (half drive pattern) driver element work,
Above-mentioned configuration alternative unit and the equal right and wrong gate circuit of calibration alternative unit.
Advantage of the present invention:
1, the present invention is good to existing relevant DDR3DRAM output module technical compatibility, and it is simple to switch to DDR2DRAM output module;
2, to compare DDR2 and DDR3DRAM of identical capacity on market cheaply a lot of for price;
Accompanying drawing explanation
Fig. 1 is existing traditional DDR3OCD module;
Fig. 2 is the dispensing unit table of existing traditional DDR3OCD;
Fig. 3 is existing traditional DDR2OCD module;
Fig. 4 is the dispensing unit table of existing traditional DDR2OCD;
Fig. 5 be of the present invention provided can the OCD module of compatible DDR2 and DDR3;
Fig. 6 be of the present invention provided can the dispensing unit table of OCD of compatible DDR2 and DDR3.
Embodiment
See Fig. 5-Fig. 6, invention provide a kind of can the OCD module of compatible DDR2 and DDR3, comprising: the driver element of DDR3 dispensing unit, DDR3 alignment unit and multiple parallel connection, DDR2 dispensing unit, DDR2 alignment unit and alternative unit; Alternative unit comprises configuration alternative unit and calibration alternative unit; DDR2 dispensing unit and DDR3 dispensing unit are connected with configuration alternative unit respectively; DDR2 alignment unit and DDR3 alignment unit are connected with calibration alternative unit respectively; Configuration alternative unit is connected with the driver element of multiple parallel connection respectively with calibration alternative unit; Alternative unit is other circuit of NAND gate circuit or other alternatives;
When control signal config_ddr2 is low level (0), OCD is set to DDR3OCD, the same with traditional DDR3OCD; When control signal config_ddr2 is high level (1), OCD is set to DDR2OCD;
When OCD is DDR3 pattern, DDR3 alignment unit is set to 240 ohm the output resistance of 8 driver elements simultaneously; And when OCD is DDR2 pattern, DDR2 alignment unit is set to 160 ohm the output resistance of 8 driver elements simultaneously;
When OCD is DDR3 pattern, DDR3 dispensing unit selects 7 (RZQ/7 patterns) or 6 (RZQ/6 pattern) driver element work; When OCD is DDR2 pattern, DDR2 dispensing unit selects 8 (full drive patterns) or 4 (half drive pattern) driver element work; When OCD will switch to DDR2 application from DDR3, only needing control signal config_ddr2 from low transition is that high level is just passable.
Claims (2)
1. can an OCD module of compatible DDR2 and DDR3, comprising: the driver element of DDR3 dispensing unit, DDR3 alignment unit and multiple parallel connection, is characterized in that: also comprise DDR2 dispensing unit, DDR2 alignment unit and alternative unit; Described alternative unit comprises configuration alternative unit and calibration alternative unit; Described DDR2 dispensing unit and DDR3 dispensing unit are connected with configuration alternative unit respectively; Described DDR2 alignment unit and DDR3 alignment unit are connected with calibration alternative unit respectively; Described configuration alternative unit is connected with the driver element of multiple parallel connection respectively with calibration alternative unit; Described DDR3 dispensing unit is for selecting the production of signal; Described DDR3 alignment unit is for arranging the output resistance of each driver element;
The control signal of described calibration alternative unit and configuration alternative unit, OCD is set to DDR3OCD pattern or DDR2OCD pattern with configuration alternative unit by the Automatic level control calibration alternative unit according to control signal, wherein, when DDR3OCD or DDR2OCD pattern, use DDR3 alignment unit or DDR2 alignment unit that the resistance value of multiple driver element is set respectively, and, when DDR3OCD pattern, DDR3 dispensing unit is used to select i.e. 7 driver elements or RZQ/6 pattern i.e. 6 the driver element work of RZQ/7 pattern, when DDR2OCD pattern, DDR2 dispensing unit is used to select full drive pattern i.e. 8 driver elements or half drive pattern i.e. 4 driver element work.
2. according to claim 1 can the OCD module of compatible DDR2 and DDR3, it is characterized in that: described configuration alternative unit and the equal right and wrong gate circuit of calibration alternative unit.
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| CN201210563555.8A CN103077736B (en) | 2012-12-21 | 2012-12-21 | A kind of can the OCD module of compatible DDR2 and DDR3 |
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| CN201210563555.8A CN103077736B (en) | 2012-12-21 | 2012-12-21 | A kind of can the OCD module of compatible DDR2 and DDR3 |
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| CN103077736A CN103077736A (en) | 2013-05-01 |
| CN103077736B true CN103077736B (en) | 2015-12-09 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1707693A (en) * | 2004-05-10 | 2005-12-14 | 海力士半导体有限公司 | Semiconductor memory device capable of adjusting impedance of data output driver |
| CN101779373A (en) * | 2007-06-08 | 2010-07-14 | 莫塞德技术公司 | Dynamic impedance control for input/output buffers |
| CN203085183U (en) * | 2012-12-21 | 2013-07-24 | 西安华芯半导体有限公司 | OCD (Output Command Data) unit compatible with DDR2 (Double Data Rate 2) and DDR3 (Double Data Rate 3) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4537145B2 (en) * | 2004-07-30 | 2010-09-01 | 富士通株式会社 | Interface circuit and configuration method thereof |
| KR100640158B1 (en) * | 2005-09-27 | 2006-11-01 | 주식회사 하이닉스반도체 | Semiconductor memory device that can adjust impedance of data output driver |
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- 2012-12-21 CN CN201210563555.8A patent/CN103077736B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1707693A (en) * | 2004-05-10 | 2005-12-14 | 海力士半导体有限公司 | Semiconductor memory device capable of adjusting impedance of data output driver |
| CN101779373A (en) * | 2007-06-08 | 2010-07-14 | 莫塞德技术公司 | Dynamic impedance control for input/output buffers |
| CN203085183U (en) * | 2012-12-21 | 2013-07-24 | 西安华芯半导体有限公司 | OCD (Output Command Data) unit compatible with DDR2 (Double Data Rate 2) and DDR3 (Double Data Rate 3) |
Non-Patent Citations (1)
| Title |
|---|
| 一种高性能DDR2控制器的设计与实现;夏军等;《计算机工程与科学》;20100715;第32卷(第7期);第62-64页 * |
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Address after: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee after: XI'AN UNIIC SEMICONDUCTORS Co.,Ltd. Address before: 710055 Shaanxi City, Xi'an province high tech Road No. 38, innovation center, A, block, floor 4 Patentee before: Xi'an Sinochip Semiconductors Co., Ltd. |