CN103066074A - Double capture-silicon oxide nitride oxide semiconductor (SONOS) memorizer with double layer dielectric charge trapping layer and preparation method thereof - Google Patents

Abstract

The invention relates to the field of semiconductor charge trapping memory, and discloses a DC-SONOS nonvolatile memory with a double-layer dielectric charge trapping layer, including a semiconductor substrate with a channel on a channel surface, and a source end adjacent to the channel and the drain terminal; the gate; a dielectric stack between the gate and the surface of the channel; and spacers on both sides of the gate and the dielectric stack. The dielectric stack includes: a tunneling layer in contact with the surface of the channel; a charge trapping layer stacked above the tunneling layer; the charge trapping layer is a composite structure of double-layer dielectric; a barrier layer stacked above the charge trapping layer, and a gate pole contact. Wherein, the charge trapping layer includes: the first layer of dielectric contacting the tunneling layer, its composition is Si ₃ N ₄ , and its thickness is 1-30 Å; the second layer of dielectric adjacent to the first layer, its composition is SiN, its thickness is 1-50?. The DC-SONOS memory with the double-layer dielectric charge trapping layer of the present invention improves the performance of the traditional SONOS non-volatile memory, improves the data retention characteristics of the memory, and is beneficial to obtain a higher data retention characteristic under relatively harsh working conditions. memory.

Description

A double-layer dielectric charge-trapping layer DC-SONOS Memories and methods of making them

technical field

The invention relates to the field of semiconductor charge trapping memory, in particular to a DC-SONOS memory with a double-layer dielectric charge trapping layer and a preparation method thereof.

Background technique

In the field of semiconductor memory, flash memory is a kind of non-volatile memory technology. Traditional flash memory uses floating gates as charge storage units. However, with the continuous development of flash memory technology, the storage density continues to increase, and the distance between floating gates If it is reduced, there will be mutual influence between the stored charges of adjacent floating gates, which hinders the increase of storage density for floating gate flash memory technology. The SONOS (silicon-silicon dioxide-silicon nitride-silicon dioxide-silicon) memory uses an insulating charge trapping layer to replace the floating gate, completely avoiding the interaction between the stored charges, and it also has its unique The ONO structure makes flash memory have the characteristics of good stability, high reliability, low power consumption, strong radiation resistance, and easy compatibility with standard CMOS processes. It is considered to be the most potential high-density memory technology. In addition, compared with other embedded non-volatile memory (NVM) technologies, the SONOS manufacturing process requires fewer masks and is more cost-effective; this technology also inherits the achievements of flash memory technology accumulated over decades, with The characteristics of good reliability, high integration and compatibility with the substrate CMOS process; at the same time, the particularity of its ONO structure and discrete charge storage technologies make the memory cells and reliability performance that can be realized by SONOS technology continuously improved.

FIG. 1A is a schematic cross-sectional view of a prior art SONOS non-volatile memory. Its structure includes a substrate 1 , a source terminal and a drain terminal 2 , a gate 3 , a dielectric stack 4 between the gate and the substrate, and sidewalls 5 . Among them, as shown in FIG. 1B, the dielectric stack 4 of the memory is respectively a charge blocking layer (SiO ₂ ) 4-1, a charge trapping layer (Si ₃ N ₄ ) 4-2, and a tunneling layer (SiO 2 ) from top to bottom. ₂ ) 4-3.

The existing "SONOS" type memory refers to a non-volatile memory device in which the charge trapping layer is a single medium and a single structure. The structure of the memory is silicon substrate, silicon dioxide tunneling layer, silicon nitride charge layer from bottom to top. Storage layer (charge trapping layer), silicon dioxide charge blocking layer and gate. At room temperature, the charge loss of traditional SONOS memory is mainly caused by the defects introduced in the tunneling layer silicon dioxide by the P/E cycle; as the operating temperature increases, the influence of this factor gradually decreases, and the charge trapping layer nitride Hole vertical transport and hole accumulation in silicon become the main factors of charge loss in conventional SONOS memory. In the harsh environment of high temperature (greater than or equal to 250 degrees Celsius), there are special storage devices that have extremely high requirements for data retention. Conventional SONOS devices cannot provide sufficient data retention performance due to their single charge-trapping layer structure.

The present invention overcomes the limitation that the charge trapping layer of the prior art is a single structure, and proposes a DC-SONOS memory with a double-layer dielectric charge trapping layer. By changing the device structure, the data retention characteristics of the memory are improved, which is beneficial to obtain SONOS non-volatile memory that maintains high data retention characteristics under harsh conditions. At the same time, the two layers of charge trapping layers of the memory of the present invention are prepared by LPCVD and PECVD respectively, and the silicon nitride of the lower layer is deposited by LPCVD process, and the film quality is high, which can improve the erasing speed and erasing resistance of the device. Ability; the upper layer of silicon nitride is deposited by PECVD process, and the defect density is increased, which is beneficial to the trapping of charges; therefore, the performance of the DC-SONOS non-volatile memory of the present invention is improved.

Contents of the invention

The present invention proposes a DC-SONOS memory with a double-layer dielectric charge trapping layer, comprising:

a semiconductor substrate including a channel having a channel surface, and source and drain terminals adjacent to the channel;

grid;

a dielectric stack between the gate and the channel surface; and

sidewalls on both sides of the gate and dielectric stack;

Wherein, the dielectric stack includes:

a tunneling layer in contact with the channel surface;

A charge trapping layer stacked above the tunneling layer; the charge trapping layer is a composite structure of double-layer dielectrics;

A blocking layer overlying the charge trapping layer is in contact with the gate.

Wherein, the charge trapping layer comprises:

The first dielectric layer in contact with the tunneling layer is composed of Si ₃ N ₄ and has a thickness of 1-30Å;

A second layer of dielectric adjacent to the first layer is composed of SiN and has a thickness of 1-50Å.

The present invention also proposes a preparation method of the DC-SONOS memory, wherein the tunneling layer is formed by dry oxygen oxidation above the semiconductor substrate, and then the charge trapping layer is formed above the tunneling layer, A barrier layer is formed above the charge trapping layer by LPCVD, a gate is formed above the barrier layer by LPCVD, sidewalls are formed on both sides of the gate, and source and drain are finally formed by self-aligned ion implantation end. Among them, the first layer of dielectric in the charge trapping layer is prepared by depositing PECVD at a temperature of 300-500°C, and the second layer of dielectric is deposited by LPCVD at a temperature of 500-900°C.

The "DC-SONOS" of the present invention refers to a Double Capture-SONOS memory, which is a memory that uses a double-layer dielectric structure "silicon tetranitride-silicon nitride" as a charge trapping layer.

The invention proposes a DC-SONOS memory with a double-layer dielectric charge trapping layer on the basis of the existing SONOS type non-volatile memory device structure. The invention not only adopts different manufacturing processes for the double-layer dielectric charge trapping layer, but also can obtain better data retention characteristics, so that the device can work under severe environmental conditions. At the same time, in the traditional SONOS memory, when the thickness of the silicon nitride charge trapping layer is less than 7nm, its data retention characteristics and the ability to capture carriers decrease with the decrease of the thickness of the charge trapping layer. When the thickness of the trapping layer is reduced to about 3nm, its data retention characteristics and carrier trapping rate are almost negligible. The invention improves the data retention characteristics of the memory and the ability to capture carriers by adopting a double-layer dielectric charge trapping layer.

The invention proposes an improved technology for the structure of the charge trapping layer based on the device structure of the SONOS type nonvolatile memory, that is, a DC-SONOS nonvolatile memory with a double-layer dielectric charge trapping layer structure. Compared with the prior art, the DC-SONOS memory with the double-layer dielectric charge trapping layer of the present invention overcomes the problem of insufficient data retention characteristics of the traditional SONOS memory when it works in harsh environments such as high temperature. Only LPCVD method is used in the preparation of the charge trapping layer of traditional SONOS devices. It has a double-layer dielectric compound charge trapping structure. The two charge trapping layers are prepared by LPCVD and PECVD respectively. The lower silicon nitride is deposited by LPCVD. The high-quality film can improve the erasing speed and anti-erasing ability of the device; while the upper layer of silicon nitride is deposited by PECVD, the defect density increases, which is conducive to the capture of charges; therefore, the DC-SONOS of the present invention is improved. type non-volatile memory performance. At the same time, there are many defects in the interface between the two layers of silicon nitride in the composite charge trapping layer of the present invention, which is conducive to the storage of more charges, and at the same time inhibits the vertical transport of holes at high temperatures, which can slow down the charge leakage and improve the performance of the device. Data retention characteristics.

Description of drawings

FIG. 1A is a schematic cross-sectional view of a conventional SONOS type non-volatile memory.

FIG. 1B is an enlarged schematic diagram of a dielectric stack in a conventional SONOS type non-volatile memory.

FIG. 2 is a DC-SONOS memory with a double-layer dielectric charge trapping layer according to the present invention. 2A is a schematic cross-sectional view of the memory of the present invention, and FIG. 2B is an enlarged schematic view of the dielectric stack in the memory of the present invention.

Detailed ways

The present invention will be described in further detail in conjunction with the following specific examples and accompanying drawings, and the protection content of the present invention is not limited to the following examples. Without departing from the spirit and scope of the inventive concept, changes and advantages conceivable by those skilled in the art are all included in the present invention, and the appended claims are the protection scope.

As shown in Figure 2, 1-semiconductor substrate, 2-source terminal and drain terminal, 3-gate, 5-sidewall, 6-dielectric stack of DC-SONOS type memory of the present invention, 6-1 dielectric Barrier layer in stack, 6-2 Composite charge trapping layer in dielectric stack, 6-2a First dielectric layer in composite charge trapping layer, 6-2b Second dielectric layer in composite charge trapping layer, 6 -3 Tunneling layers in the dielectric stack.

As shown in Figure 2, the present invention has the DC-SONOS memory of double-layer dielectric charge trapping layer, comprises: semiconductor substrate 1, the channel that has channel surface on it, and the source end and drain adjacent to said channel terminal 2; gate 3; a dielectric laminate 6 between the gate 3 and the surface of the channel; The source terminal 2 and the drain terminal 2 are connected.

Among them, the dielectric stack includes: a tunneling layer 6-3, which is in contact with the surface of the channel; a charge trapping layer 6-2 superimposed on the tunneling layer 6-3; the charge trapping layer 6-2 is a composite of a double-layer dielectric Structure; a blocking layer 6-1 stacked on the charge trapping layer 6-2, and in contact with the gate 3.

Among them, the charge trapping layer 6-2 includes: a first layer of dielectric 6-2a in contact with the tunneling layer, the composition of which is Si ₃ N ₄ , and a thickness of 1-30Å; a second layer of dielectric 6-2b adjacent to the first layer , whose composition is SiN, with a thickness of 1–50Å.

Compared with the traditional SONOS type non-volatile memory, the novelty of the DC-SONOS memory with double dielectric charge trapping layer of the present invention lies in the composite charge trapping layer 6-2. Simple Si3N4 is used in the traditional SONOS nonvolatile memory device structure, but the novel structure SONOS nonvolatile memory device provided by the present invention uses a charge trapping layer of a double-layer composite dielectric of Si3N4 and SiN.

Example 1:

This embodiment provides a specific preparation method of the memory of the present invention.

First, a semiconductor substrate 1 is provided, and then a layer of SiO ₂ is formed by dry oxygen oxidation on the substrate, the thickness of which is 54 Å, which is the tunneling layer 6-3. Then use LPCVD technology to form 20Å Si3N4 successively, which is the first layer of dielectric 6-2a. Then use PECVD technology to form a layer of SiN on top of it, which is the second layer of dielectric 6-2b, with a thickness of 40 Å. These two layers together form a composite charge trapping layer 6-2. Then use LPCVD technology to form a 60Å SiO2 blocking layer 6-1 above the charge trapping layer. Then a gate 3 is formed on it by LPCVD, and sidewalls 5 are formed on both sides of the gate 3 . Finally, the source terminal and the drain terminal 2 are formed by self-aligned ion implantation.

In actual use of the DC-SONOS memory of the present invention, when there is a bias voltage, carriers are injected from the silicon substrate into the silicon nitride layer through the silicon dioxide tunneling layer, wherein the carriers are firstly injected into the silicon nitride layer by the tunneling layer two The surface traps formed between silicon oxide and the charge trapping layer silicon nitride are trapped, and then the remaining carriers are injected into the charge trapping layer. Due to the large number of trap charges in the charge trapping layer, most The carriers are all stored in the charge trapping layer, and the carriers trapped by the surface traps are almost negligible. In the double-layer dielectric compound charge trapping structure of the DC-SONOS memory of the present invention, the silicon nitride of the lower layer is deposited using LPCVD, and the film quality is high, which can improve the erasing speed and anti-erasing ability of the device; ₃ N ₄ silicon nitride is deposited by PECVD. The temperature required for the manufacture of silicon nitride by PECVD technology is low, and the thickness is not subject to any restrictions. Silicon nitride may also contain a small amount of hydrogen impurities. The ideal match for silicon nitride The ratio will not be as ideal as the result of LPCVD, so the defect density increases, which is conducive to the trapping of charges; at the same time, compared with the single-layer silicon nitride in the traditional memory, the interface between the two layers of silicon nitride in the present invention is relatively small. Multiple defects, which greatly increase the carrier capture ability and carrier storage ability. When there is no bias voltage, it is difficult for carriers to cross the barrier height of the silicon dioxide tunneling layer, and trap-assisted tunneling becomes the main leakage mechanism. Most of the traps for trap-assisted tunneling are shallow surface traps, and the two layers of nitride The traps introduced by silicon are all deep traps, and the trap-assisted tunneling of carriers is very difficult, which inhibits the vertical transport of carriers at high temperatures, can slow down charge leakage, and improve the data retention characteristics of devices.

Compared with the traditional SONOS non-volatile memory, the present invention has a double-layer dielectric charge trapping layer, the structure increases the effective trap density, the number of traps is increased by about 5 times, and the storage capacity of carriers is also increased by 3 times , the operating window is also increased by about 1V. For traditional SONOS memory, the operating window is greater than 0.5V to work normally, so the increased 1V operating window greatly improves the data retention characteristics of the memory, and the memory of the present invention also has a lifespan of more than 10 years in the extremely harsh 120°C high temperature environment At the same time, due to the increase of carrier storage capacity, a small amount of lost carriers can be completely ignored compared with the total stored carriers. The working stability and anti-erasing ability of the memory of the present invention are improved. Improving the memory of the present invention can be applied in some fields that require very high performance of the memory. For traditional SONOS non-volatile memory, although silicon nitride charge storage has an ideal charge capture capability when its thickness is greater than 7nm, its charge capture capability drops sharply when its thickness decreases, and its data retention characteristics are also very low. When its thickness drops to about 3nm, its charge trapping ability and data retention ability are almost negligible. At the same time, with the continuous development of microelectronics technology and the continuous improvement of chip integration, the horizontal and vertical dimensions of memory devices are constantly shrinking. Therefore, traditional SONOS devices cannot overcome the problems brought about by the continuous reduction in device size. Reliability issues, and the DC-SONOS memory of the present invention also has very good data retention characteristics and charge capture capabilities when the device size is continuously reduced, and is the best choice for future memory development.

Claims (3)

1. a DC-SONOS memory with double-layer dielectric charge trapping layer, is characterized in that, comprises: a semiconductor substrate including a channel having a channel surface, and source and drain terminals adjacent to the channel; grid; a dielectric stack between the gate and the channel surface; and sidewalls on both sides of the gate and dielectric stack; Wherein, the dielectric stack includes: a tunneling layer in contact with the channel surface; A charge trapping layer stacked above the tunneling layer; the charge trapping layer is a composite structure of double-layer dielectrics; A blocking layer overlying the charge trapping layer is in contact with the gate. 2. DC-SONOS memory according to claim 1, is characterized in that, described charge trapping layer comprises: The first dielectric layer in contact with the tunneling layer is composed of Si ₃ N ₄ and has a thickness of 1-30Å; A second layer of dielectric adjacent to the first layer is composed of SiN and has a thickness of 1-50Å. 3. The method for preparing a DC-SONOS memory according to claim 1 or 2, wherein the tunneling layer is formed by dry oxygen oxidation above the semiconductor substrate, and then the tunneling layer is formed above the tunneling layer. For the charge trapping layer, a blocking layer is formed above the charge trapping layer by LPCVD, a gate is formed above the blocking layer by LPCVD, sidewalls are formed on both sides of the gate, and finally self-aligned ion implantation Forming a source terminal and a drain terminal; wherein, the first layer of dielectric in the charge trapping layer is deposited at a temperature of 500-900°C by LPCVD, and the second layer of dielectric is deposited at a temperature of 300-500°C by PECVD. Prepared by deposition.

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