CN103065681B

CN103065681B - The structure of read operation reference current in memorizer

Info

Publication number: CN103065681B
Application number: CN201110322548.4A
Authority: CN
Inventors: 郭璐; 金建明
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-10-21
Filing date: 2011-10-21
Publication date: 2016-06-08
Anticipated expiration: 2031-10-21
Also published as: CN103065681A

Abstract

The invention discloses the structure of read operation reference current in a kind of memorizer; Choose the memory element producing reference current respectively, add the row as reference current generation unit in the centre position of storage array and lower edges, on average choose N-bit unit according to X-direction Address d istribution; The reference current generating circuit unrelated with process deviation, is added the N-bit cell current chosen and averages, namely obtain this reference current. The present invention, by choosing storage array zones of different unit, the method taking its average current, effectively prevent the current deviation problem produced in technique realizes, has higher reliability, and especially in mass storage is applied, advantage becomes apparent from.

Description

The structure of read operation reference current in memorizer

Technical field

The structure that when the present invention relates to read operation in a kind of nonvolatile memory, internal reference electric current is chosen.

Background technology

Nonvolatile memory (NVM) needs a road reference current when carrying out read operation, the realization of this electric current generally has two ways: one is directly to design biasing circuit, using reference current as reference current; A kind of is utilize in memorizer the On current of memory element as reference current. The a kind of of the second reference current structure is optimized design by the present invention.

Utilize memory cell conducts electric current as the method for reference current, it is common that using a memory cell device turned on as current source in reference current generating circuit. As it is shown in figure 1, M0 is 1 bit cell in storage array, M3 is 1 memory device producing reference current, and M3 is not belonging to storage array and is not involved in operation with high pressure. By the electric current of M3 mirror image according to a certain percentage, compare with the electric current of M0, it is achieved read the operation of " 0 " reading " 1 ". Memorizer the method circuit realiration for low capacity is simple, and has certain reliability. But in Large Copacity designs, owing to memory array area is big, the memory element in zones of different can produce bigger deviation in technique realizes, thus On current deviation is also relatively big, therefore traditional reference current method for designing is it cannot be guaranteed that reliability.

When memory span is bigger, the chip area that array covers is also bigger, there is bigger process deviation between the memory element of different address so that the deviation of their On current is also relatively big, produce reference current using a memory device as current source in this case and be clearly irrational.

Summary of the invention

The technical problem to be solved is to provide in a kind of memorizer the structure of read operation reference current, and it can apply in mass storage, solves the insecure realistic problem of reference current caused due to memory cell current deviation.

In order to solve above technical problem, the invention provides the structure of read operation reference current in a kind of memorizer; Choose the memory element producing reference current respectively, add the row as reference current generation unit in the centre position of storage array and lower edges, on average choose N-bit unit according to X-direction Address d istribution;The reference current generating circuit unrelated with process deviation, is added the N-bit cell current chosen and averages, namely obtain this reference current.

The beneficial effects of the present invention is: by choosing storage array zones of different unit, the method taking its average current, effectively prevent the current deviation problem produced in technique realizes, have higher reliability, especially in mass storage is applied, advantage becomes apparent from.

There are three independent line storage unit RW0 to RW2 in storage array, are used for producing reference current, lay respectively at the lower limb of array, centre and top edge; Wherein choose 2 bit cells respectively in memory element RW0 and RW2, choose 4 bit cells in RW1 as current source.

R0 to Rn is N+1 memory cell device, and Iref is the superposition of R0 to Rn On current, and Iavg is the meansigma methods of N-bit memory cell current, and Iavg is reference current. Wherein R0 to R8 is 9 memory cell devices.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.

Fig. 1 is conventional reference electric current producing method schematic diagram;

Fig. 2 is reference current generation unit physical address schematic diagram;

Fig. 3 is the reference current generating circuit schematic diagram unrelated with process deviation;

Detailed description of the invention

The present invention proposes the producing method of a kind of internal reference electric current being applied to memory circuitry, which is by choosing storage array zones of different unit, the method taking its average current, effectively prevent the current deviation problem produced in technique realizes, having higher reliability, especially in mass storage is applied, advantage becomes apparent from.

Design principle: the storage array being Nbitx8 for columns, as in figure 2 it is shown, RW0 to RW2 is three line storage units independent in storage array, is used for producing reference current, lays respectively at the lower limb of array, centre and top edge; Choose 2 bit cells in RW0 and RW2 respectively, choose 4 bit cells in RW1 as current source, in the such as Fig. 2 of position shown in labelling R. X-direction (in row distribution) and Y-direction (in row distribution) it is mainly reflected in due to process deviation, therefore the memory element as reference current source chosen can embody the deviation of X-direction and Y-direction in array, the electric current of 8 bit cells is averaged, namely obtains reference current.

Reference current generating circuit is as it is shown on figure 3, R0 to Rn is N+1 memory cell device, and N=8 in this example, in physical location such as Fig. 2 shown in labelling R; Iref is the superposition of R0 to Rn On current, and Iavg is the meansigma methods of N-bit memory cell current, and Iavg is reference current.

The present invention is not limited to embodiment discussed above. Above the description of detailed description of the invention is intended to describe and the technical scheme that the present invention relates to being described. Apparent conversion or replacement based on present invention enlightenment should also be as being considered within protection scope of the present invention. Above detailed description of the invention is used for disclosing the best implementation of the present invention, so that those of ordinary skill in the art can apply the numerous embodiments of the present invention and multiple alternative to reach the purpose of the present invention.

Claims

1. the structure of read operation reference current in a memorizer; It is characterized in that,

Choose the memory element producing reference current respectively, add the row as reference current generation unit in the centre position of storage array and lower edges, on average choose N-bit unit according to X-direction Address d istribution;

The reference current generating circuit unrelated with process deviation, is added the N-bit cell current chosen and averages, namely obtain this reference current;

There are three independent line storage unit RW0 to RW2 in described storage array, are used for producing reference current, lay respectively at the lower limb of array, centre and top edge; Wherein choose 2 bit cells respectively in memory element RW0 and RW2, choose 4 bit cells in RW1 as current source.

2. the structure of read operation reference current in memorizer as claimed in claim 1; It is characterized in that, R0 to Rn is N+1 memory cell device, and Iref is the superposition of R0 to Rn On current, and Iavg is the meansigma methods of N-bit memory cell current, and Iavg is reference current.

3. the structure of read operation reference current in memorizer as claimed in claim 2; It is characterized in that, wherein R0 to R8 is 9 memory cell devices.